1edc61147SHawking Zhang /*
2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc.
3edc61147SHawking Zhang *
4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a
5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"),
6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation
7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the
9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions:
10edc61147SHawking Zhang *
11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in
12edc61147SHawking Zhang * all copies or substantial portions of the Software.
13edc61147SHawking Zhang *
14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE.
21edc61147SHawking Zhang *
22edc61147SHawking Zhang */
23edc61147SHawking Zhang
24b23b2e9eSAlex Deucher #include <linux/pci.h>
25b23b2e9eSAlex Deucher
26edc61147SHawking Zhang #include "amdgpu.h"
27edc61147SHawking Zhang #include "amdgpu_ih.h"
28edc61147SHawking Zhang
29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h"
30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h"
31edc61147SHawking Zhang
32edc61147SHawking Zhang #include "soc15_common.h"
33edc61147SHawking Zhang #include "navi10_ih.h"
34edc61147SHawking Zhang
35022b6518SSamir Dhume #define MAX_REARM_RETRY 10
36edc61147SHawking Zhang
37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d
38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0
39757b3af8SLikun Gao
40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
41edc61147SHawking Zhang
42edc61147SHawking Zhang /**
435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings
445212d163SHawking Zhang *
455212d163SHawking Zhang * @adev: amdgpu_device pointer
465212d163SHawking Zhang *
475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10).
485212d163SHawking Zhang */
navi10_ih_init_register_offset(struct amdgpu_device * adev)495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev)
505212d163SHawking Zhang {
515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs;
525212d163SHawking Zhang
535212d163SHawking Zhang if (adev->irq.ih.ring_size) {
545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs;
555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
645212d163SHawking Zhang }
655212d163SHawking Zhang
665212d163SHawking Zhang if (adev->irq.ih1.ring_size) {
675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs;
685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
755212d163SHawking Zhang }
765212d163SHawking Zhang
775212d163SHawking Zhang if (adev->irq.ih2.ring_size) {
785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs;
795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
865212d163SHawking Zhang }
875212d163SHawking Zhang }
885212d163SHawking Zhang
895212d163SHawking Zhang /**
905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt
915ea6f9c2SChengming Gui *
925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer
935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting
945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting
955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism
965ea6f9c2SChengming Gui *
975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0,
985ea6f9c2SChengming Gui * real_threshold = 2^threshold
995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8,
1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq)
1015ea6f9c2SChengming Gui *
1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
1035ea6f9c2SChengming Gui */
1045ea6f9c2SChengming Gui static void
force_update_wptr_for_self_int(struct amdgpu_device * adev,u32 threshold,u32 timeout,bool enabled)1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev,
1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled)
1075ea6f9c2SChengming Gui {
1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl;
1095ea6f9c2SChengming Gui
1101d789535SAlex Deucher if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
1115ea6f9c2SChengming Gui return;
1125ea6f9c2SChengming Gui
1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
1155ea6f9c2SChengming Gui
1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold);
1225ea6f9c2SChengming Gui
1232b9ced5aSRohit Khaire if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
1242b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
1252b9ced5aSRohit Khaire return;
1262b9ced5aSRohit Khaire } else {
1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
1282b9ced5aSRohit Khaire }
1292b9ced5aSRohit Khaire
1305ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
1315ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
1325ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold);
1332b9ced5aSRohit Khaire if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
1342b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
1352b9ced5aSRohit Khaire return;
1362b9ced5aSRohit Khaire } else {
1375ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
1382b9ced5aSRohit Khaire }
1392b9ced5aSRohit Khaire
1405ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
1415ea6f9c2SChengming Gui }
1425ea6f9c2SChengming Gui
1435ea6f9c2SChengming Gui /**
1441ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
1451ce6940eSHawking Zhang *
1461ce6940eSHawking Zhang * @adev: amdgpu_device pointer
1471ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet
1481ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts
1491ce6940eSHawking Zhang *
1501ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10)
1511ce6940eSHawking Zhang */
navi10_ih_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)1521ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
1531ce6940eSHawking Zhang struct amdgpu_ih_ring *ih,
1541ce6940eSHawking Zhang bool enable)
1551ce6940eSHawking Zhang {
1561ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs;
1571ce6940eSHawking Zhang uint32_t tmp;
1581ce6940eSHawking Zhang
1591ce6940eSHawking Zhang ih_regs = &ih->ih_regs;
1601ce6940eSHawking Zhang
1611ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl);
1621ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
16371ee9236SPhilip Yang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
1641ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */
1651ce6940eSHawking Zhang if (ih == &adev->irq.ih)
1661ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
1674aa7e6e0SYuBiao Wang
1684aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
1692b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
1704aa7e6e0SYuBiao Wang return -ETIMEDOUT;
1714aa7e6e0SYuBiao Wang } else {
1721ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp);
1734aa7e6e0SYuBiao Wang }
1741ce6940eSHawking Zhang
1751ce6940eSHawking Zhang if (enable) {
1761ce6940eSHawking Zhang ih->enabled = true;
1771ce6940eSHawking Zhang } else {
1781ce6940eSHawking Zhang /* set rptr, wptr to 0 */
1791ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0);
1801ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0);
1811ce6940eSHawking Zhang ih->enabled = false;
1821ce6940eSHawking Zhang ih->rptr = 0;
1831ce6940eSHawking Zhang }
1841ce6940eSHawking Zhang
1851ce6940eSHawking Zhang return 0;
1861ce6940eSHawking Zhang }
1871ce6940eSHawking Zhang
1886e7b7c7fSHawking Zhang /**
1896e7b7c7fSHawking Zhang * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
1906e7b7c7fSHawking Zhang *
1916e7b7c7fSHawking Zhang * @adev: amdgpu_device pointer
1926e7b7c7fSHawking Zhang * @enable: enable or disable interrupt ring buffers
1936e7b7c7fSHawking Zhang *
1946e7b7c7fSHawking Zhang * Toggle all the available interrupt ring buffers (NAVI10).
1956e7b7c7fSHawking Zhang */
navi10_ih_toggle_interrupts(struct amdgpu_device * adev,bool enable)1966e7b7c7fSHawking Zhang static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
1976e7b7c7fSHawking Zhang {
1986e7b7c7fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
1996e7b7c7fSHawking Zhang int i;
2006e7b7c7fSHawking Zhang int r;
2016e7b7c7fSHawking Zhang
2026e7b7c7fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) {
2036e7b7c7fSHawking Zhang if (ih[i]->ring_size) {
2046e7b7c7fSHawking Zhang r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable);
2056e7b7c7fSHawking Zhang if (r)
2066e7b7c7fSHawking Zhang return r;
2076e7b7c7fSHawking Zhang }
2086e7b7c7fSHawking Zhang }
2096e7b7c7fSHawking Zhang
2106e7b7c7fSHawking Zhang return 0;
2116e7b7c7fSHawking Zhang }
2126e7b7c7fSHawking Zhang
navi10_ih_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)213edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
214edc61147SHawking Zhang {
215edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4);
216edc61147SHawking Zhang
217edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
218edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4);
219edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
220edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1);
221edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
222edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1);
223edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
224edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
225edc61147SHawking Zhang * value is written to memory
226edc61147SHawking Zhang */
227edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
228edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1);
229edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
230edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
231edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
232edc61147SHawking Zhang
233edc61147SHawking Zhang return ih_rb_cntl;
234edc61147SHawking Zhang }
235edc61147SHawking Zhang
navi10_ih_doorbell_rptr(struct amdgpu_ih_ring * ih)236ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
237ab518012SAlex Sierra {
238ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0;
239ab518012SAlex Sierra
240ab518012SAlex Sierra if (ih->use_doorbell) {
241ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
242ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET,
243ab518012SAlex Sierra ih->doorbell_index);
244ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
245ab518012SAlex Sierra IH_DOORBELL_RPTR,
246ab518012SAlex Sierra ENABLE, 1);
247ab518012SAlex Sierra } else {
248ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
249ab518012SAlex Sierra IH_DOORBELL_RPTR,
250ab518012SAlex Sierra ENABLE, 0);
251ab518012SAlex Sierra }
252ab518012SAlex Sierra return ih_doorbell_rtpr;
253ab518012SAlex Sierra }
254ab518012SAlex Sierra
2551514cb7dSHawking Zhang /**
2561514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer
2571514cb7dSHawking Zhang *
2581514cb7dSHawking Zhang * @adev: amdgpu_device pointer
2591514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer
2601514cb7dSHawking Zhang *
2611514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10)
2621514cb7dSHawking Zhang */
navi10_ih_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)2631514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev,
2641514cb7dSHawking Zhang struct amdgpu_ih_ring *ih)
2651514cb7dSHawking Zhang {
2661514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs;
2671514cb7dSHawking Zhang uint32_t tmp;
2681514cb7dSHawking Zhang
2691514cb7dSHawking Zhang ih_regs = &ih->ih_regs;
2701514cb7dSHawking Zhang
2711514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
2721514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
2731514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
2741514cb7dSHawking Zhang
2751514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl);
2761514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp);
2771514cb7dSHawking Zhang if (ih == &adev->irq.ih)
2781514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
27923eb4925SPhilip Yang if (ih == &adev->irq.ih1)
2801514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
2814aa7e6e0SYuBiao Wang
2824aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
2834aa7e6e0SYuBiao Wang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
2844aa7e6e0SYuBiao Wang DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
2854aa7e6e0SYuBiao Wang return -ETIMEDOUT;
2864aa7e6e0SYuBiao Wang }
2874aa7e6e0SYuBiao Wang } else {
2881514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp);
2894aa7e6e0SYuBiao Wang }
2901514cb7dSHawking Zhang
2911514cb7dSHawking Zhang if (ih == &adev->irq.ih) {
2921514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */
2931514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
2941514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
2951514cb7dSHawking Zhang }
2961514cb7dSHawking Zhang
2971514cb7dSHawking Zhang /* set rptr, wptr to 0 */
2981514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0);
2991514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0);
3001514cb7dSHawking Zhang
3011514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
3021514cb7dSHawking Zhang
3031514cb7dSHawking Zhang return 0;
3041514cb7dSHawking Zhang }
3051514cb7dSHawking Zhang
306edc61147SHawking Zhang /**
307edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring
308edc61147SHawking Zhang *
309edc61147SHawking Zhang * @adev: amdgpu_device pointer
310edc61147SHawking Zhang *
311edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller,
312edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH
313edc61147SHawking Zhang * ring buffer and enable it (NAVI).
314edc61147SHawking Zhang * Called at device load and reume.
315edc61147SHawking Zhang * Returns 0 for success, errors for failure.
316edc61147SHawking Zhang */
navi10_ih_irq_init(struct amdgpu_device * adev)317edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev)
318edc61147SHawking Zhang {
319fc4aa19fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
320fc4aa19fSHawking Zhang u32 ih_chicken;
3216e7b7c7fSHawking Zhang int ret;
322fc4aa19fSHawking Zhang int i;
323edc61147SHawking Zhang
324edc61147SHawking Zhang /* disable irqs */
3256e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, false);
3266e7b7c7fSHawking Zhang if (ret)
3276e7b7c7fSHawking Zhang return ret;
328edc61147SHawking Zhang
329bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev);
330edc61147SHawking Zhang
331edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
332fc4aa19fSHawking Zhang if (ih[0]->use_bus_addr) {
3331d789535SAlex Deucher switch (adev->ip_versions[OSSSYS_HWIP][0]) {
3347c69d615SAlex Deucher case IP_VERSION(5, 0, 3):
3357c69d615SAlex Deucher case IP_VERSION(5, 2, 0):
3367c69d615SAlex Deucher case IP_VERSION(5, 2, 1):
337757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
338757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken,
339757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
340757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
341757b3af8SLikun Gao break;
342757b3af8SLikun Gao default:
343edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
344edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken,
345edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
346edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
347757b3af8SLikun Gao break;
348757b3af8SLikun Gao }
349edc61147SHawking Zhang }
350edc61147SHawking Zhang }
351edc61147SHawking Zhang
352fc4aa19fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) {
353fc4aa19fSHawking Zhang if (ih[i]->ring_size) {
354fc4aa19fSHawking Zhang ret = navi10_ih_enable_ring(adev, ih[i]);
355fc4aa19fSHawking Zhang if (ret)
356fc4aa19fSHawking Zhang return ret;
3570ab176e6SAlex Sierra }
358ab518012SAlex Sierra }
359ab518012SAlex Sierra
360fc4aa19fSHawking Zhang /* update doorbell range for ih ring 0*/
361fc4aa19fSHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
362fc4aa19fSHawking Zhang ih[0]->doorbell_index);
363ab518012SAlex Sierra
364edc61147SHawking Zhang pci_set_master(adev->pdev);
365edc61147SHawking Zhang
366edc61147SHawking Zhang /* enable interrupts */
3676e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, true);
3686e7b7c7fSHawking Zhang if (ret)
3696e7b7c7fSHawking Zhang return ret;
3705ea6f9c2SChengming Gui /* enable wptr force update for self int */
3715ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true);
372edc61147SHawking Zhang
3737f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size)
3747f03b148SHawking Zhang adev->irq.ih_soft.enabled = true;
3757f03b148SHawking Zhang
3767eca4006SMa Feng return 0;
377edc61147SHawking Zhang }
378edc61147SHawking Zhang
379edc61147SHawking Zhang /**
380edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts
381edc61147SHawking Zhang *
382edc61147SHawking Zhang * @adev: amdgpu_device pointer
383edc61147SHawking Zhang *
384edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10).
385edc61147SHawking Zhang */
navi10_ih_irq_disable(struct amdgpu_device * adev)386edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev)
387edc61147SHawking Zhang {
3885ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false);
3896e7b7c7fSHawking Zhang navi10_ih_toggle_interrupts(adev, false);
390edc61147SHawking Zhang
391edc61147SHawking Zhang /* Wait and acknowledge irq */
392edc61147SHawking Zhang mdelay(1);
393edc61147SHawking Zhang }
394edc61147SHawking Zhang
395edc61147SHawking Zhang /**
396edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr
397edc61147SHawking Zhang *
398edc61147SHawking Zhang * @adev: amdgpu_device pointer
399c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr
400edc61147SHawking Zhang *
401edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register
402edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for
403edc61147SHawking Zhang * ring buffer overflow and deal with it.
404edc61147SHawking Zhang * Returns the value of the wptr.
405edc61147SHawking Zhang */
navi10_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)406edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
407edc61147SHawking Zhang struct amdgpu_ih_ring *ih)
408edc61147SHawking Zhang {
4092d2fbf68SHawking Zhang u32 wptr, tmp;
4102d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs;
411edc61147SHawking Zhang
412de8341eeSMukul Joshi if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
41323eb4925SPhilip Yang /* Only ring0 supports writeback. On other rings fall back
41423eb4925SPhilip Yang * to register-based code with overflow checking below.
415de8341eeSMukul Joshi * ih_soft ring doesn't have any backing hardware registers,
416de8341eeSMukul Joshi * update wptr and return.
41723eb4925SPhilip Yang */
418edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu);
419edc61147SHawking Zhang
420edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
421edc61147SHawking Zhang goto out;
42223eb4925SPhilip Yang }
423edc61147SHawking Zhang
42423eb4925SPhilip Yang ih_regs = &ih->ih_regs;
42523eb4925SPhilip Yang
42623eb4925SPhilip Yang /* Double check that the overflow wasn't already cleared. */
4272d2fbf68SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
428edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
429edc61147SHawking Zhang goto out;
430edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
431edc61147SHawking Zhang
432edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt
433edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully
434edc61147SHawking Zhang * this should allow us to catch up.
435edc61147SHawking Zhang */
436edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask;
437edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow "
438edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n",
439edc61147SHawking Zhang wptr, ih->rptr, tmp);
440edc61147SHawking Zhang ih->rptr = tmp;
441edc61147SHawking Zhang
4422d2fbf68SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
443edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
4442d2fbf68SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
445*89833979SFriedrich Vock
446*89833979SFriedrich Vock /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
447*89833979SFriedrich Vock * can be detected.
448*89833979SFriedrich Vock */
449*89833979SFriedrich Vock tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
450*89833979SFriedrich Vock WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
451edc61147SHawking Zhang out:
452edc61147SHawking Zhang return (wptr & ih->ptr_mask);
453edc61147SHawking Zhang }
454edc61147SHawking Zhang
455edc61147SHawking Zhang /**
456022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost
457022b6518SSamir Dhume *
458022b6518SSamir Dhume * @adev: amdgpu_device pointer
459c56fb081SLee Jones * @ih: IH ring to match
460022b6518SSamir Dhume *
461022b6518SSamir Dhume */
navi10_ih_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)462022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
463022b6518SSamir Dhume struct amdgpu_ih_ring *ih)
464022b6518SSamir Dhume {
465022b6518SSamir Dhume uint32_t v = 0;
466022b6518SSamir Dhume uint32_t i = 0;
4672d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs;
468022b6518SSamir Dhume
4692d2fbf68SHawking Zhang ih_regs = &ih->ih_regs;
470022b6518SSamir Dhume
471022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */
472022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) {
4732d2fbf68SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
474022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr))
475022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr);
476022b6518SSamir Dhume else
477022b6518SSamir Dhume break;
478022b6518SSamir Dhume }
479022b6518SSamir Dhume }
480022b6518SSamir Dhume
481022b6518SSamir Dhume /**
482edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr
483edc61147SHawking Zhang *
484edc61147SHawking Zhang * @adev: amdgpu_device pointer
485edc61147SHawking Zhang *
486c56fb081SLee Jones * @ih: IH ring buffer to set rptr
487edc61147SHawking Zhang * Set the IH ring buffer rptr.
488edc61147SHawking Zhang */
navi10_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)489edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev,
490edc61147SHawking Zhang struct amdgpu_ih_ring *ih)
491edc61147SHawking Zhang {
4922d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs;
4932d2fbf68SHawking Zhang
494de8341eeSMukul Joshi if (ih == &adev->irq.ih_soft)
495de8341eeSMukul Joshi return;
496de8341eeSMukul Joshi
497edc61147SHawking Zhang if (ih->use_doorbell) {
498edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */
499edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr;
500edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr);
501022b6518SSamir Dhume
502022b6518SSamir Dhume if (amdgpu_sriov_vf(adev))
503022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih);
5042d2fbf68SHawking Zhang } else {
5052d2fbf68SHawking Zhang ih_regs = &ih->ih_regs;
5062d2fbf68SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr);
507ab518012SAlex Sierra }
508ab518012SAlex Sierra }
509ab518012SAlex Sierra
510ab518012SAlex Sierra /**
511ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2
512ab518012SAlex Sierra *
513ab518012SAlex Sierra * @adev: amdgpu_device pointer
514ab518012SAlex Sierra * @source: irq source
515ab518012SAlex Sierra * @entry: IV with WPTR update
516ab518012SAlex Sierra *
517ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries.
518ab518012SAlex Sierra */
navi10_ih_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)519ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev,
520ab518012SAlex Sierra struct amdgpu_irq_src *source,
521ab518012SAlex Sierra struct amdgpu_iv_entry *entry)
522ab518012SAlex Sierra {
523ab518012SAlex Sierra switch (entry->ring_id) {
524ab518012SAlex Sierra case 1:
525ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work);
526ab518012SAlex Sierra break;
527ab518012SAlex Sierra case 2:
528ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work);
529ab518012SAlex Sierra break;
530ab518012SAlex Sierra default: break;
531ab518012SAlex Sierra }
532ab518012SAlex Sierra return 0;
533ab518012SAlex Sierra }
534ab518012SAlex Sierra
535ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = {
536ab518012SAlex Sierra .process = navi10_ih_self_irq,
537ab518012SAlex Sierra };
538ab518012SAlex Sierra
navi10_ih_set_self_irq_funcs(struct amdgpu_device * adev)539ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
540ab518012SAlex Sierra {
541ab518012SAlex Sierra adev->irq.self_irq.num_types = 0;
542ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs;
543edc61147SHawking Zhang }
544edc61147SHawking Zhang
navi10_ih_early_init(void * handle)545edc61147SHawking Zhang static int navi10_ih_early_init(void *handle)
546edc61147SHawking Zhang {
547edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
548edc61147SHawking Zhang
549edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev);
550ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev);
551edc61147SHawking Zhang return 0;
552edc61147SHawking Zhang }
553edc61147SHawking Zhang
navi10_ih_sw_init(void * handle)554edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle)
555edc61147SHawking Zhang {
556edc61147SHawking Zhang int r;
557edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558edc61147SHawking Zhang bool use_bus_addr;
559edc61147SHawking Zhang
560ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
561ab518012SAlex Sierra &adev->irq.self_irq);
562ab518012SAlex Sierra
563ab518012SAlex Sierra if (r)
564ab518012SAlex Sierra return r;
565ab518012SAlex Sierra
566edc61147SHawking Zhang /* use gpu virtual address for ih ring
567edc61147SHawking Zhang * until ih_checken is programmed to allow
568edc61147SHawking Zhang * use bus address for ih ring by psp bl */
569bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) ||
570bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
571bf13cb1fSHuang Rui use_bus_addr = false;
572bf13cb1fSHuang Rui else
573bf13cb1fSHuang Rui use_bus_addr = true;
574bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
575edc61147SHawking Zhang if (r)
576edc61147SHawking Zhang return r;
577edc61147SHawking Zhang
578edc61147SHawking Zhang adev->irq.ih.use_doorbell = true;
579edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
580edc61147SHawking Zhang
581abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0;
582abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0;
583abb6fccbSAlex Sierra
584a362976bSHawking Zhang /* initialize ih control registers offset */
585a362976bSHawking Zhang navi10_ih_init_register_offset(adev);
586a362976bSHawking Zhang
587bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
588d4581f7dSChristian König if (r)
589d4581f7dSChristian König return r;
590d4581f7dSChristian König
591edc61147SHawking Zhang r = amdgpu_irq_init(adev);
592edc61147SHawking Zhang
593edc61147SHawking Zhang return r;
594edc61147SHawking Zhang }
595edc61147SHawking Zhang
navi10_ih_sw_fini(void * handle)596edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle)
597edc61147SHawking Zhang {
598edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599edc61147SHawking Zhang
60072c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev);
601edc61147SHawking Zhang
602edc61147SHawking Zhang return 0;
603edc61147SHawking Zhang }
604edc61147SHawking Zhang
navi10_ih_hw_init(void * handle)605edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle)
606edc61147SHawking Zhang {
607edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608edc61147SHawking Zhang
609364d453fSMinghao Chi return navi10_ih_irq_init(adev);
610edc61147SHawking Zhang }
611edc61147SHawking Zhang
navi10_ih_hw_fini(void * handle)612edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle)
613edc61147SHawking Zhang {
614edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
615edc61147SHawking Zhang
616edc61147SHawking Zhang navi10_ih_irq_disable(adev);
617edc61147SHawking Zhang
618edc61147SHawking Zhang return 0;
619edc61147SHawking Zhang }
620edc61147SHawking Zhang
navi10_ih_suspend(void * handle)621edc61147SHawking Zhang static int navi10_ih_suspend(void *handle)
622edc61147SHawking Zhang {
623edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624edc61147SHawking Zhang
625edc61147SHawking Zhang return navi10_ih_hw_fini(adev);
626edc61147SHawking Zhang }
627edc61147SHawking Zhang
navi10_ih_resume(void * handle)628edc61147SHawking Zhang static int navi10_ih_resume(void *handle)
629edc61147SHawking Zhang {
630edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
631edc61147SHawking Zhang
632edc61147SHawking Zhang return navi10_ih_hw_init(adev);
633edc61147SHawking Zhang }
634edc61147SHawking Zhang
navi10_ih_is_idle(void * handle)635edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle)
636edc61147SHawking Zhang {
637edc61147SHawking Zhang /* todo */
638edc61147SHawking Zhang return true;
639edc61147SHawking Zhang }
640edc61147SHawking Zhang
navi10_ih_wait_for_idle(void * handle)641edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle)
642edc61147SHawking Zhang {
643edc61147SHawking Zhang /* todo */
644edc61147SHawking Zhang return -ETIMEDOUT;
645edc61147SHawking Zhang }
646edc61147SHawking Zhang
navi10_ih_soft_reset(void * handle)647edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle)
648edc61147SHawking Zhang {
649edc61147SHawking Zhang /* todo */
650edc61147SHawking Zhang return 0;
651edc61147SHawking Zhang }
652edc61147SHawking Zhang
navi10_ih_update_clockgating_state(struct amdgpu_device * adev,bool enable)653edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
654edc61147SHawking Zhang bool enable)
655edc61147SHawking Zhang {
656edc61147SHawking Zhang uint32_t data, def, field_val;
657edc61147SHawking Zhang
658edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
659edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
660edc61147SHawking Zhang field_val = enable ? 0 : 1;
661edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL,
662edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
663edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL,
664edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
665edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL,
666edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
667edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL,
668edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val);
669edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL,
670edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val);
671edc61147SHawking Zhang if (def != data)
672edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
673edc61147SHawking Zhang }
674edc61147SHawking Zhang
675edc61147SHawking Zhang return;
676edc61147SHawking Zhang }
677edc61147SHawking Zhang
navi10_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)678edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle,
679edc61147SHawking Zhang enum amd_clockgating_state state)
680edc61147SHawking Zhang {
681edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
682edc61147SHawking Zhang
683edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev,
684a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE);
685edc61147SHawking Zhang return 0;
686edc61147SHawking Zhang }
687edc61147SHawking Zhang
navi10_ih_set_powergating_state(void * handle,enum amd_powergating_state state)688edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle,
689edc61147SHawking Zhang enum amd_powergating_state state)
690edc61147SHawking Zhang {
691edc61147SHawking Zhang return 0;
692edc61147SHawking Zhang }
693edc61147SHawking Zhang
navi10_ih_get_clockgating_state(void * handle,u64 * flags)69425faeddcSEvan Quan static void navi10_ih_get_clockgating_state(void *handle, u64 *flags)
695edc61147SHawking Zhang {
696edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
697edc61147SHawking Zhang
698edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
699edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG;
700edc61147SHawking Zhang
701edc61147SHawking Zhang return;
702edc61147SHawking Zhang }
703edc61147SHawking Zhang
704edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = {
705edc61147SHawking Zhang .name = "navi10_ih",
706edc61147SHawking Zhang .early_init = navi10_ih_early_init,
707edc61147SHawking Zhang .late_init = NULL,
708edc61147SHawking Zhang .sw_init = navi10_ih_sw_init,
709edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini,
710edc61147SHawking Zhang .hw_init = navi10_ih_hw_init,
711edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini,
712edc61147SHawking Zhang .suspend = navi10_ih_suspend,
713edc61147SHawking Zhang .resume = navi10_ih_resume,
714edc61147SHawking Zhang .is_idle = navi10_ih_is_idle,
715edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle,
716edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset,
717edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state,
718edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state,
719edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state,
720edc61147SHawking Zhang };
721edc61147SHawking Zhang
722edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = {
723edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr,
72440838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper,
7253c2d6ea2SPhilip Yang .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
726edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr
727edc61147SHawking Zhang };
728edc61147SHawking Zhang
navi10_ih_set_interrupt_funcs(struct amdgpu_device * adev)729edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
730edc61147SHawking Zhang {
731edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL)
732edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs;
733edc61147SHawking Zhang }
734edc61147SHawking Zhang
735edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block =
736edc61147SHawking Zhang {
737edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH,
738edc61147SHawking Zhang .major = 5,
739edc61147SHawking Zhang .minor = 0,
740edc61147SHawking Zhang .rev = 0,
741edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs,
742edc61147SHawking Zhang };
743