1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 43edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 44edc61147SHawking Zhang * 45edc61147SHawking Zhang * @adev: amdgpu_device pointer 46edc61147SHawking Zhang * 47edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 48edc61147SHawking Zhang */ 49edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 50edc61147SHawking Zhang { 51edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 52edc61147SHawking Zhang 53edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 54edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 55193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 560ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 570ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 580ab176e6SAlex Sierra return; 590ab176e6SAlex Sierra } 600ab176e6SAlex Sierra } else { 61edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 620ab176e6SAlex Sierra } 630ab176e6SAlex Sierra 64edc61147SHawking Zhang adev->irq.ih.enabled = true; 65ab518012SAlex Sierra 66ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 67ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 68ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 69ab518012SAlex Sierra RB_ENABLE, 1); 70193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 710ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 720ab176e6SAlex Sierra ih_rb_cntl)) { 730ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 740ab176e6SAlex Sierra return; 750ab176e6SAlex Sierra } 760ab176e6SAlex Sierra } else { 77ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 780ab176e6SAlex Sierra } 79ab518012SAlex Sierra adev->irq.ih1.enabled = true; 80ab518012SAlex Sierra } 81ab518012SAlex Sierra 82ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 83ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 84ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 85ab518012SAlex Sierra RB_ENABLE, 1); 86193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 870ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 880ab176e6SAlex Sierra ih_rb_cntl)) { 890ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 900ab176e6SAlex Sierra return; 910ab176e6SAlex Sierra } 920ab176e6SAlex Sierra } else { 93ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 940ab176e6SAlex Sierra } 95ab518012SAlex Sierra adev->irq.ih2.enabled = true; 96ab518012SAlex Sierra } 97edc61147SHawking Zhang } 98edc61147SHawking Zhang 99edc61147SHawking Zhang /** 100edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 101edc61147SHawking Zhang * 102edc61147SHawking Zhang * @adev: amdgpu_device pointer 103edc61147SHawking Zhang * 104edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 105edc61147SHawking Zhang */ 106edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 107edc61147SHawking Zhang { 108edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 109edc61147SHawking Zhang 110edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 111edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 112193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1130ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 1140ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1150ab176e6SAlex Sierra return; 1160ab176e6SAlex Sierra } 1170ab176e6SAlex Sierra } else { 118edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1190ab176e6SAlex Sierra } 1200ab176e6SAlex Sierra 121edc61147SHawking Zhang /* set rptr, wptr to 0 */ 122edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 123edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 124edc61147SHawking Zhang adev->irq.ih.enabled = false; 125edc61147SHawking Zhang adev->irq.ih.rptr = 0; 126ab518012SAlex Sierra 127ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 128ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 129ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 130ab518012SAlex Sierra RB_ENABLE, 0); 131193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1320ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1330ab176e6SAlex Sierra ih_rb_cntl)) { 1340ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1350ab176e6SAlex Sierra return; 1360ab176e6SAlex Sierra } 1370ab176e6SAlex Sierra } else { 138ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1390ab176e6SAlex Sierra } 140ab518012SAlex Sierra /* set rptr, wptr to 0 */ 141ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 142ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 143ab518012SAlex Sierra adev->irq.ih1.enabled = false; 144ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 145ab518012SAlex Sierra } 146ab518012SAlex Sierra 147ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 148ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 149ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 150ab518012SAlex Sierra RB_ENABLE, 0); 151193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1520ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1530ab176e6SAlex Sierra ih_rb_cntl)) { 1540ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1550ab176e6SAlex Sierra return; 1560ab176e6SAlex Sierra } 1570ab176e6SAlex Sierra } else { 158ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1590ab176e6SAlex Sierra } 160ab518012SAlex Sierra /* set rptr, wptr to 0 */ 161ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 162ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 163ab518012SAlex Sierra adev->irq.ih2.enabled = false; 164ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 165ab518012SAlex Sierra } 166ab518012SAlex Sierra 167edc61147SHawking Zhang } 168edc61147SHawking Zhang 169edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 170edc61147SHawking Zhang { 171edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 172edc61147SHawking Zhang 173edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 175edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 177edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 178edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 179edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 180edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 181edc61147SHawking Zhang * value is written to memory 182edc61147SHawking Zhang */ 183edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 184edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 185edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 186edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 187edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 188edc61147SHawking Zhang 189edc61147SHawking Zhang return ih_rb_cntl; 190edc61147SHawking Zhang } 191edc61147SHawking Zhang 192ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 193ab518012SAlex Sierra { 194ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 195ab518012SAlex Sierra 196ab518012SAlex Sierra if (ih->use_doorbell) { 197ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 199ab518012SAlex Sierra ih->doorbell_index); 200ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 201ab518012SAlex Sierra IH_DOORBELL_RPTR, 202ab518012SAlex Sierra ENABLE, 1); 203ab518012SAlex Sierra } else { 204ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 205ab518012SAlex Sierra IH_DOORBELL_RPTR, 206ab518012SAlex Sierra ENABLE, 0); 207ab518012SAlex Sierra } 208ab518012SAlex Sierra return ih_doorbell_rtpr; 209ab518012SAlex Sierra } 210ab518012SAlex Sierra 2119e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 2129e94ff33SAlex Sierra { 2139e94ff33SAlex Sierra uint32_t tmp; 2149e94ff33SAlex Sierra 2159e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 2169e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 2179e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2189e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 2199e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2209e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2219e94ff33SAlex Sierra 2229e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 2239e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 2249e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2259e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2269e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2279e94ff33SAlex Sierra } 2289e94ff33SAlex Sierra 229edc61147SHawking Zhang /** 230edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 231edc61147SHawking Zhang * 232edc61147SHawking Zhang * @adev: amdgpu_device pointer 233edc61147SHawking Zhang * 234edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 235edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 236edc61147SHawking Zhang * ring buffer and enable it (NAVI). 237edc61147SHawking Zhang * Called at device load and reume. 238edc61147SHawking Zhang * Returns 0 for success, errors for failure. 239edc61147SHawking Zhang */ 240edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 241edc61147SHawking Zhang { 242edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 243ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 244edc61147SHawking Zhang u32 tmp; 245edc61147SHawking Zhang 246edc61147SHawking Zhang /* disable irqs */ 247edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 248edc61147SHawking Zhang 249bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 250edc61147SHawking Zhang 251edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 252edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 253edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 254edc61147SHawking Zhang 255edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 256edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 257edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 258edc61147SHawking Zhang !!adev->irq.msi_enabled); 259193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 2600ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 2610ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 2620ab176e6SAlex Sierra return -ETIMEDOUT; 2630ab176e6SAlex Sierra } 2640ab176e6SAlex Sierra } else { 2650ab176e6SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 2660ab176e6SAlex Sierra } 2679e94ff33SAlex Sierra navi10_ih_reroute_ih(adev); 268edc61147SHawking Zhang 269edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 270edc61147SHawking Zhang if (ih->use_bus_addr) { 271757b3af8SLikun Gao switch (adev->asic_type) { 272757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 273757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 274757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 275757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 276757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 277757b3af8SLikun Gao break; 278757b3af8SLikun Gao default: 279edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 280edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 281edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 282edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 283757b3af8SLikun Gao break; 284757b3af8SLikun Gao } 285edc61147SHawking Zhang } 286edc61147SHawking Zhang } 287edc61147SHawking Zhang 288edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 289edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 290edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 291edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 292edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 293edc61147SHawking Zhang 294edc61147SHawking Zhang /* set rptr, wptr to 0 */ 295edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 296edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 297edc61147SHawking Zhang 298ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 299ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 300edc61147SHawking Zhang 301bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 302edc61147SHawking Zhang ih->doorbell_index); 303edc61147SHawking Zhang 304ab518012SAlex Sierra ih = &adev->irq.ih1; 305ab518012SAlex Sierra if (ih->ring_size) { 306ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 307ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 308ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 309ab518012SAlex Sierra 310ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 311ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 312ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 313ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 314ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 315ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 316193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3170ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 3180ab176e6SAlex Sierra ih_rb_cntl)) { 3190ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 3200ab176e6SAlex Sierra return -ETIMEDOUT; 3210ab176e6SAlex Sierra } 3220ab176e6SAlex Sierra } else { 323ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 3240ab176e6SAlex Sierra } 325ab518012SAlex Sierra /* set rptr, wptr to 0 */ 326ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 327ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 328ab518012SAlex Sierra 329ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 330ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 331ab518012SAlex Sierra } 332ab518012SAlex Sierra 333ab518012SAlex Sierra ih = &adev->irq.ih2; 334ab518012SAlex Sierra if (ih->ring_size) { 335ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 336ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 337ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 338ab518012SAlex Sierra 339ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 340ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 341ab518012SAlex Sierra 342193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3430ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 3440ab176e6SAlex Sierra ih_rb_cntl)) { 3450ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 3460ab176e6SAlex Sierra return -ETIMEDOUT; 3470ab176e6SAlex Sierra } 3480ab176e6SAlex Sierra } else { 349ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 3500ab176e6SAlex Sierra } 351ab518012SAlex Sierra /* set rptr, wptr to 0 */ 352ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 353ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 354ab518012SAlex Sierra 355ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 356ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 357ab518012SAlex Sierra } 358ab518012SAlex Sierra 359ab518012SAlex Sierra 360edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 361edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 362edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 363edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 364edc61147SHawking Zhang 365edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 366edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 367edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 368edc61147SHawking Zhang 369edc61147SHawking Zhang pci_set_master(adev->pdev); 370edc61147SHawking Zhang 371edc61147SHawking Zhang /* enable interrupts */ 372edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 373edc61147SHawking Zhang 3747eca4006SMa Feng return 0; 375edc61147SHawking Zhang } 376edc61147SHawking Zhang 377edc61147SHawking Zhang /** 378edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 379edc61147SHawking Zhang * 380edc61147SHawking Zhang * @adev: amdgpu_device pointer 381edc61147SHawking Zhang * 382edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 383edc61147SHawking Zhang */ 384edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 385edc61147SHawking Zhang { 386edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 387edc61147SHawking Zhang 388edc61147SHawking Zhang /* Wait and acknowledge irq */ 389edc61147SHawking Zhang mdelay(1); 390edc61147SHawking Zhang } 391edc61147SHawking Zhang 392edc61147SHawking Zhang /** 393edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 394edc61147SHawking Zhang * 395edc61147SHawking Zhang * @adev: amdgpu_device pointer 396edc61147SHawking Zhang * 397edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 398edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 399edc61147SHawking Zhang * ring buffer overflow and deal with it. 400edc61147SHawking Zhang * Returns the value of the wptr. 401edc61147SHawking Zhang */ 402edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 403edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 404edc61147SHawking Zhang { 405edc61147SHawking Zhang u32 wptr, reg, tmp; 406edc61147SHawking Zhang 407edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 408edc61147SHawking Zhang 409edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 410edc61147SHawking Zhang goto out; 411edc61147SHawking Zhang 412ab518012SAlex Sierra if (ih == &adev->irq.ih) 413edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 414ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 415ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 416ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 417ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 418ab518012SAlex Sierra else 419ab518012SAlex Sierra BUG(); 420ab518012SAlex Sierra 421edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 422edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 423edc61147SHawking Zhang goto out; 424edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 425edc61147SHawking Zhang 426edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 427edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 428edc61147SHawking Zhang * this should allow us to catch up. 429edc61147SHawking Zhang */ 430edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 431edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 432edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 433edc61147SHawking Zhang wptr, ih->rptr, tmp); 434edc61147SHawking Zhang ih->rptr = tmp; 435edc61147SHawking Zhang 436ab518012SAlex Sierra if (ih == &adev->irq.ih) 437edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 438ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 439ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 440ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 441ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 442ab518012SAlex Sierra else 443ab518012SAlex Sierra BUG(); 444ab518012SAlex Sierra 445edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 446edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 447edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 448edc61147SHawking Zhang out: 449edc61147SHawking Zhang return (wptr & ih->ptr_mask); 450edc61147SHawking Zhang } 451edc61147SHawking Zhang 452edc61147SHawking Zhang /** 453edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 454edc61147SHawking Zhang * 455edc61147SHawking Zhang * @adev: amdgpu_device pointer 456edc61147SHawking Zhang * 457edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 458edc61147SHawking Zhang * position and also advance the position. 459edc61147SHawking Zhang */ 460edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 461edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 462edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 463edc61147SHawking Zhang { 464edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 465edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 466edc61147SHawking Zhang uint32_t dw[8]; 467edc61147SHawking Zhang 468edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 469edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 470edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 471edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 472edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 473edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 474edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 475edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 476edc61147SHawking Zhang 477edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 478edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 479edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 480edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 481edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 482edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 483edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 484edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 485edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 486edc61147SHawking Zhang entry->src_data[0] = dw[4]; 487edc61147SHawking Zhang entry->src_data[1] = dw[5]; 488edc61147SHawking Zhang entry->src_data[2] = dw[6]; 489edc61147SHawking Zhang entry->src_data[3] = dw[7]; 490edc61147SHawking Zhang 491edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 492edc61147SHawking Zhang ih->rptr += 32; 493edc61147SHawking Zhang } 494edc61147SHawking Zhang 495edc61147SHawking Zhang /** 496022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 497022b6518SSamir Dhume * 498022b6518SSamir Dhume * @adev: amdgpu_device pointer 499022b6518SSamir Dhume * 500022b6518SSamir Dhume */ 501022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 502022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 503022b6518SSamir Dhume { 504022b6518SSamir Dhume uint32_t reg_rptr = 0; 505022b6518SSamir Dhume uint32_t v = 0; 506022b6518SSamir Dhume uint32_t i = 0; 507022b6518SSamir Dhume 508022b6518SSamir Dhume if (ih == &adev->irq.ih) 509022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 510022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 511022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 512022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 513022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 514022b6518SSamir Dhume else 515022b6518SSamir Dhume return; 516022b6518SSamir Dhume 517022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 518022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 519022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 520022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 521022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 522022b6518SSamir Dhume else 523022b6518SSamir Dhume break; 524022b6518SSamir Dhume } 525022b6518SSamir Dhume } 526022b6518SSamir Dhume 527022b6518SSamir Dhume /** 528edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 529edc61147SHawking Zhang * 530edc61147SHawking Zhang * @adev: amdgpu_device pointer 531edc61147SHawking Zhang * 532edc61147SHawking Zhang * Set the IH ring buffer rptr. 533edc61147SHawking Zhang */ 534edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 535edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 536edc61147SHawking Zhang { 537edc61147SHawking Zhang if (ih->use_doorbell) { 538edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 539edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 540edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 541022b6518SSamir Dhume 542022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 543022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 544ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 545edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 546ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 547ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 548ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 549ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 550ab518012SAlex Sierra } 551ab518012SAlex Sierra } 552ab518012SAlex Sierra 553ab518012SAlex Sierra /** 554ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 555ab518012SAlex Sierra * 556ab518012SAlex Sierra * @adev: amdgpu_device pointer 557ab518012SAlex Sierra * @source: irq source 558ab518012SAlex Sierra * @entry: IV with WPTR update 559ab518012SAlex Sierra * 560ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 561ab518012SAlex Sierra */ 562ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 563ab518012SAlex Sierra struct amdgpu_irq_src *source, 564ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 565ab518012SAlex Sierra { 566ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 567ab518012SAlex Sierra 568ab518012SAlex Sierra switch (entry->ring_id) { 569ab518012SAlex Sierra case 1: 570ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 571ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 572ab518012SAlex Sierra break; 573ab518012SAlex Sierra case 2: 574ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 575ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 576ab518012SAlex Sierra break; 577ab518012SAlex Sierra default: break; 578ab518012SAlex Sierra } 579ab518012SAlex Sierra return 0; 580ab518012SAlex Sierra } 581ab518012SAlex Sierra 582ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 583ab518012SAlex Sierra .process = navi10_ih_self_irq, 584ab518012SAlex Sierra }; 585ab518012SAlex Sierra 586ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 587ab518012SAlex Sierra { 588ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 589ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 590edc61147SHawking Zhang } 591edc61147SHawking Zhang 592edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 593edc61147SHawking Zhang { 594edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 595edc61147SHawking Zhang 596edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 597ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 598edc61147SHawking Zhang return 0; 599edc61147SHawking Zhang } 600edc61147SHawking Zhang 601edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 602edc61147SHawking Zhang { 603edc61147SHawking Zhang int r; 604edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 605edc61147SHawking Zhang bool use_bus_addr; 606edc61147SHawking Zhang 607ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 608ab518012SAlex Sierra &adev->irq.self_irq); 609ab518012SAlex Sierra 610ab518012SAlex Sierra if (r) 611ab518012SAlex Sierra return r; 612ab518012SAlex Sierra 613edc61147SHawking Zhang /* use gpu virtual address for ih ring 614edc61147SHawking Zhang * until ih_checken is programmed to allow 615edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 616edc61147SHawking Zhang use_bus_addr = 617edc61147SHawking Zhang (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 618edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 619edc61147SHawking Zhang if (r) 620edc61147SHawking Zhang return r; 621edc61147SHawking Zhang 622edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 623edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 624edc61147SHawking Zhang 625ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 626ab518012SAlex Sierra if (r) 627ab518012SAlex Sierra return r; 628ab518012SAlex Sierra 629ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 630ab518012SAlex Sierra adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 631ab518012SAlex Sierra 632ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 633ab518012SAlex Sierra if (r) 634ab518012SAlex Sierra return r; 635ab518012SAlex Sierra 636ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 637ab518012SAlex Sierra adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 638ab518012SAlex Sierra 639edc61147SHawking Zhang r = amdgpu_irq_init(adev); 640edc61147SHawking Zhang 641edc61147SHawking Zhang return r; 642edc61147SHawking Zhang } 643edc61147SHawking Zhang 644edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 645edc61147SHawking Zhang { 646edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 647edc61147SHawking Zhang 648edc61147SHawking Zhang amdgpu_irq_fini(adev); 649ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 650ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 651edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 652edc61147SHawking Zhang 653edc61147SHawking Zhang return 0; 654edc61147SHawking Zhang } 655edc61147SHawking Zhang 656edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 657edc61147SHawking Zhang { 658edc61147SHawking Zhang int r; 659edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660edc61147SHawking Zhang 661edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 662edc61147SHawking Zhang if (r) 663edc61147SHawking Zhang return r; 664edc61147SHawking Zhang 665edc61147SHawking Zhang return 0; 666edc61147SHawking Zhang } 667edc61147SHawking Zhang 668edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 669edc61147SHawking Zhang { 670edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 671edc61147SHawking Zhang 672edc61147SHawking Zhang navi10_ih_irq_disable(adev); 673edc61147SHawking Zhang 674edc61147SHawking Zhang return 0; 675edc61147SHawking Zhang } 676edc61147SHawking Zhang 677edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 678edc61147SHawking Zhang { 679edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 680edc61147SHawking Zhang 681edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 682edc61147SHawking Zhang } 683edc61147SHawking Zhang 684edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 685edc61147SHawking Zhang { 686edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687edc61147SHawking Zhang 688edc61147SHawking Zhang return navi10_ih_hw_init(adev); 689edc61147SHawking Zhang } 690edc61147SHawking Zhang 691edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 692edc61147SHawking Zhang { 693edc61147SHawking Zhang /* todo */ 694edc61147SHawking Zhang return true; 695edc61147SHawking Zhang } 696edc61147SHawking Zhang 697edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 698edc61147SHawking Zhang { 699edc61147SHawking Zhang /* todo */ 700edc61147SHawking Zhang return -ETIMEDOUT; 701edc61147SHawking Zhang } 702edc61147SHawking Zhang 703edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 704edc61147SHawking Zhang { 705edc61147SHawking Zhang /* todo */ 706edc61147SHawking Zhang return 0; 707edc61147SHawking Zhang } 708edc61147SHawking Zhang 709edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 710edc61147SHawking Zhang bool enable) 711edc61147SHawking Zhang { 712edc61147SHawking Zhang uint32_t data, def, field_val; 713edc61147SHawking Zhang 714edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 715edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 716edc61147SHawking Zhang field_val = enable ? 0 : 1; 717edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 718edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 719edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 720edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 721edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 722edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 723edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 724edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 725edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 726edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 727edc61147SHawking Zhang if (def != data) 728edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 729edc61147SHawking Zhang } 730edc61147SHawking Zhang 731edc61147SHawking Zhang return; 732edc61147SHawking Zhang } 733edc61147SHawking Zhang 734edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 735edc61147SHawking Zhang enum amd_clockgating_state state) 736edc61147SHawking Zhang { 737edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 738edc61147SHawking Zhang 739edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 740a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 741edc61147SHawking Zhang return 0; 742edc61147SHawking Zhang } 743edc61147SHawking Zhang 744edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 745edc61147SHawking Zhang enum amd_powergating_state state) 746edc61147SHawking Zhang { 747edc61147SHawking Zhang return 0; 748edc61147SHawking Zhang } 749edc61147SHawking Zhang 750edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 751edc61147SHawking Zhang { 752edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 753edc61147SHawking Zhang 754edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 755edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 756edc61147SHawking Zhang 757edc61147SHawking Zhang return; 758edc61147SHawking Zhang } 759edc61147SHawking Zhang 760edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 761edc61147SHawking Zhang .name = "navi10_ih", 762edc61147SHawking Zhang .early_init = navi10_ih_early_init, 763edc61147SHawking Zhang .late_init = NULL, 764edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 765edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 766edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 767edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 768edc61147SHawking Zhang .suspend = navi10_ih_suspend, 769edc61147SHawking Zhang .resume = navi10_ih_resume, 770edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 771edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 772edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 773edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 774edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 775edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 776edc61147SHawking Zhang }; 777edc61147SHawking Zhang 778edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 779edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 780edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 781edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 782edc61147SHawking Zhang }; 783edc61147SHawking Zhang 784edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 785edc61147SHawking Zhang { 786edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 787edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 788edc61147SHawking Zhang } 789edc61147SHawking Zhang 790edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 791edc61147SHawking Zhang { 792edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 793edc61147SHawking Zhang .major = 5, 794edc61147SHawking Zhang .minor = 0, 795edc61147SHawking Zhang .rev = 0, 796edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 797edc61147SHawking Zhang }; 798