1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings 445212d163SHawking Zhang * 455212d163SHawking Zhang * @adev: amdgpu_device pointer 465212d163SHawking Zhang * 475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10). 485212d163SHawking Zhang */ 495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 505212d163SHawking Zhang { 515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs; 525212d163SHawking Zhang 535212d163SHawking Zhang if (adev->irq.ih.ring_size) { 545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 645212d163SHawking Zhang } 655212d163SHawking Zhang 665212d163SHawking Zhang if (adev->irq.ih1.ring_size) { 675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 755212d163SHawking Zhang } 765212d163SHawking Zhang 775212d163SHawking Zhang if (adev->irq.ih2.ring_size) { 785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 865212d163SHawking Zhang } 875212d163SHawking Zhang } 885212d163SHawking Zhang 895212d163SHawking Zhang /** 905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 915ea6f9c2SChengming Gui * 925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 965ea6f9c2SChengming Gui * 975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 985ea6f9c2SChengming Gui * real_threshold = 2^threshold 995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 1015ea6f9c2SChengming Gui * 1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 1035ea6f9c2SChengming Gui */ 1045ea6f9c2SChengming Gui static void 1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 1075ea6f9c2SChengming Gui { 1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 1095ea6f9c2SChengming Gui 1105ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 1115ea6f9c2SChengming Gui return; 1125ea6f9c2SChengming Gui 1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 1155ea6f9c2SChengming Gui 1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1225ea6f9c2SChengming Gui 1235ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1245ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 1255ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 1265ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1285ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 1295ea6f9c2SChengming Gui } 1305ea6f9c2SChengming Gui 1315ea6f9c2SChengming Gui /** 1321ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 1331ce6940eSHawking Zhang * 1341ce6940eSHawking Zhang * @adev: amdgpu_device pointer 1351ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet 1361ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 1371ce6940eSHawking Zhang * 1381ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10) 1391ce6940eSHawking Zhang */ 1401ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 1411ce6940eSHawking Zhang struct amdgpu_ih_ring *ih, 1421ce6940eSHawking Zhang bool enable) 1431ce6940eSHawking Zhang { 1441ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs; 1451ce6940eSHawking Zhang uint32_t tmp; 1461ce6940eSHawking Zhang 1471ce6940eSHawking Zhang ih_regs = &ih->ih_regs; 1481ce6940eSHawking Zhang 1491ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 1501ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1511ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */ 1521ce6940eSHawking Zhang if (ih == &adev->irq.ih) 1531ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154*4aa7e6e0SYuBiao Wang 155*4aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 156*4aa7e6e0SYuBiao Wang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 157*4aa7e6e0SYuBiao Wang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 158*4aa7e6e0SYuBiao Wang return -ETIMEDOUT; 159*4aa7e6e0SYuBiao Wang } 160*4aa7e6e0SYuBiao Wang } else { 1611ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 162*4aa7e6e0SYuBiao Wang } 1631ce6940eSHawking Zhang 1641ce6940eSHawking Zhang if (enable) { 1651ce6940eSHawking Zhang ih->enabled = true; 1661ce6940eSHawking Zhang } else { 1671ce6940eSHawking Zhang /* set rptr, wptr to 0 */ 1681ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 1691ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 1701ce6940eSHawking Zhang ih->enabled = false; 1711ce6940eSHawking Zhang ih->rptr = 0; 1721ce6940eSHawking Zhang } 1731ce6940eSHawking Zhang 1741ce6940eSHawking Zhang return 0; 1751ce6940eSHawking Zhang } 1761ce6940eSHawking Zhang 1776e7b7c7fSHawking Zhang /** 1786e7b7c7fSHawking Zhang * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 1796e7b7c7fSHawking Zhang * 1806e7b7c7fSHawking Zhang * @adev: amdgpu_device pointer 1816e7b7c7fSHawking Zhang * @enable: enable or disable interrupt ring buffers 1826e7b7c7fSHawking Zhang * 1836e7b7c7fSHawking Zhang * Toggle all the available interrupt ring buffers (NAVI10). 1846e7b7c7fSHawking Zhang */ 1856e7b7c7fSHawking Zhang static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 1866e7b7c7fSHawking Zhang { 1876e7b7c7fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 1886e7b7c7fSHawking Zhang int i; 1896e7b7c7fSHawking Zhang int r; 1906e7b7c7fSHawking Zhang 1916e7b7c7fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 1926e7b7c7fSHawking Zhang if (ih[i]->ring_size) { 1936e7b7c7fSHawking Zhang r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 1946e7b7c7fSHawking Zhang if (r) 1956e7b7c7fSHawking Zhang return r; 1966e7b7c7fSHawking Zhang } 1976e7b7c7fSHawking Zhang } 1986e7b7c7fSHawking Zhang 1996e7b7c7fSHawking Zhang return 0; 2006e7b7c7fSHawking Zhang } 2016e7b7c7fSHawking Zhang 202edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 203edc61147SHawking Zhang { 204edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 205edc61147SHawking Zhang 206edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 207edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 208edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 209edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 210edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 211edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 212edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 213edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 214edc61147SHawking Zhang * value is written to memory 215edc61147SHawking Zhang */ 216edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 217edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 218edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 219edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 220edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 221edc61147SHawking Zhang 222edc61147SHawking Zhang return ih_rb_cntl; 223edc61147SHawking Zhang } 224edc61147SHawking Zhang 225ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 226ab518012SAlex Sierra { 227ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 228ab518012SAlex Sierra 229ab518012SAlex Sierra if (ih->use_doorbell) { 230ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 231ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 232ab518012SAlex Sierra ih->doorbell_index); 233ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 234ab518012SAlex Sierra IH_DOORBELL_RPTR, 235ab518012SAlex Sierra ENABLE, 1); 236ab518012SAlex Sierra } else { 237ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 238ab518012SAlex Sierra IH_DOORBELL_RPTR, 239ab518012SAlex Sierra ENABLE, 0); 240ab518012SAlex Sierra } 241ab518012SAlex Sierra return ih_doorbell_rtpr; 242ab518012SAlex Sierra } 243ab518012SAlex Sierra 2441514cb7dSHawking Zhang /** 2451514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer 2461514cb7dSHawking Zhang * 2471514cb7dSHawking Zhang * @adev: amdgpu_device pointer 2481514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer 2491514cb7dSHawking Zhang * 2501514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10) 2511514cb7dSHawking Zhang */ 2521514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev, 2531514cb7dSHawking Zhang struct amdgpu_ih_ring *ih) 2541514cb7dSHawking Zhang { 2551514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs; 2561514cb7dSHawking Zhang uint32_t tmp; 2571514cb7dSHawking Zhang 2581514cb7dSHawking Zhang ih_regs = &ih->ih_regs; 2591514cb7dSHawking Zhang 2601514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 2611514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 2621514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 2631514cb7dSHawking Zhang 2641514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 2651514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp); 2661514cb7dSHawking Zhang if (ih == &adev->irq.ih) 2671514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 2681514cb7dSHawking Zhang if (ih == &adev->irq.ih1) { 2691514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 2701514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 2711514cb7dSHawking Zhang } 272*4aa7e6e0SYuBiao Wang 273*4aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 274*4aa7e6e0SYuBiao Wang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 275*4aa7e6e0SYuBiao Wang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 276*4aa7e6e0SYuBiao Wang return -ETIMEDOUT; 277*4aa7e6e0SYuBiao Wang } 278*4aa7e6e0SYuBiao Wang } else { 2791514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 280*4aa7e6e0SYuBiao Wang } 2811514cb7dSHawking Zhang 2821514cb7dSHawking Zhang if (ih == &adev->irq.ih) { 2831514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 2841514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 2851514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 2861514cb7dSHawking Zhang } 2871514cb7dSHawking Zhang 2881514cb7dSHawking Zhang /* set rptr, wptr to 0 */ 2891514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 2901514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 2911514cb7dSHawking Zhang 2921514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 2931514cb7dSHawking Zhang 2941514cb7dSHawking Zhang return 0; 2951514cb7dSHawking Zhang } 2961514cb7dSHawking Zhang 297edc61147SHawking Zhang /** 298edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 299edc61147SHawking Zhang * 300edc61147SHawking Zhang * @adev: amdgpu_device pointer 301edc61147SHawking Zhang * 302edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 303edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 304edc61147SHawking Zhang * ring buffer and enable it (NAVI). 305edc61147SHawking Zhang * Called at device load and reume. 306edc61147SHawking Zhang * Returns 0 for success, errors for failure. 307edc61147SHawking Zhang */ 308edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 309edc61147SHawking Zhang { 310fc4aa19fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 311fc4aa19fSHawking Zhang u32 ih_chicken; 312edc61147SHawking Zhang u32 tmp; 3136e7b7c7fSHawking Zhang int ret; 314fc4aa19fSHawking Zhang int i; 315edc61147SHawking Zhang 316edc61147SHawking Zhang /* disable irqs */ 3176e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, false); 3186e7b7c7fSHawking Zhang if (ret) 3196e7b7c7fSHawking Zhang return ret; 320edc61147SHawking Zhang 321bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 322edc61147SHawking Zhang 323edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 324fc4aa19fSHawking Zhang if (ih[0]->use_bus_addr) { 325757b3af8SLikun Gao switch (adev->asic_type) { 326757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 327026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 328bd4f2811SHuang Rui case CHIP_VANGOGH: 329771cc67eSTao Zhou case CHIP_DIMGREY_CAVEFISH: 330a1dede36SChengming Gui case CHIP_BEIGE_GOBY: 331757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 332757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 333757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 334757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 335757b3af8SLikun Gao break; 336757b3af8SLikun Gao default: 337edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 338edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 339edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 340edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 341757b3af8SLikun Gao break; 342757b3af8SLikun Gao } 343edc61147SHawking Zhang } 344edc61147SHawking Zhang } 345edc61147SHawking Zhang 346fc4aa19fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 347fc4aa19fSHawking Zhang if (ih[i]->ring_size) { 348fc4aa19fSHawking Zhang ret = navi10_ih_enable_ring(adev, ih[i]); 349fc4aa19fSHawking Zhang if (ret) 350fc4aa19fSHawking Zhang return ret; 3510ab176e6SAlex Sierra } 352ab518012SAlex Sierra } 353ab518012SAlex Sierra 354fc4aa19fSHawking Zhang /* update doorbell range for ih ring 0*/ 355fc4aa19fSHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 356fc4aa19fSHawking Zhang ih[0]->doorbell_index); 357ab518012SAlex Sierra 358edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 359edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 360edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 361edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 362edc61147SHawking Zhang 363edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 364edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 365edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 366edc61147SHawking Zhang 367edc61147SHawking Zhang pci_set_master(adev->pdev); 368edc61147SHawking Zhang 369edc61147SHawking Zhang /* enable interrupts */ 3706e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, true); 3716e7b7c7fSHawking Zhang if (ret) 3726e7b7c7fSHawking Zhang return ret; 3735ea6f9c2SChengming Gui /* enable wptr force update for self int */ 3745ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 375edc61147SHawking Zhang 3767f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size) 3777f03b148SHawking Zhang adev->irq.ih_soft.enabled = true; 3787f03b148SHawking Zhang 3797eca4006SMa Feng return 0; 380edc61147SHawking Zhang } 381edc61147SHawking Zhang 382edc61147SHawking Zhang /** 383edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 384edc61147SHawking Zhang * 385edc61147SHawking Zhang * @adev: amdgpu_device pointer 386edc61147SHawking Zhang * 387edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 388edc61147SHawking Zhang */ 389edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 390edc61147SHawking Zhang { 3915ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 3926e7b7c7fSHawking Zhang navi10_ih_toggle_interrupts(adev, false); 393edc61147SHawking Zhang 394edc61147SHawking Zhang /* Wait and acknowledge irq */ 395edc61147SHawking Zhang mdelay(1); 396edc61147SHawking Zhang } 397edc61147SHawking Zhang 398edc61147SHawking Zhang /** 399edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 400edc61147SHawking Zhang * 401edc61147SHawking Zhang * @adev: amdgpu_device pointer 402c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 403edc61147SHawking Zhang * 404edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 405edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 406edc61147SHawking Zhang * ring buffer overflow and deal with it. 407edc61147SHawking Zhang * Returns the value of the wptr. 408edc61147SHawking Zhang */ 409edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 410edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 411edc61147SHawking Zhang { 4122d2fbf68SHawking Zhang u32 wptr, tmp; 4132d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 414edc61147SHawking Zhang 415edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 4162d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 417edc61147SHawking Zhang 418edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 419edc61147SHawking Zhang goto out; 420edc61147SHawking Zhang 4212d2fbf68SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 422edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 423edc61147SHawking Zhang goto out; 424edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 425edc61147SHawking Zhang 426edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 427edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 428edc61147SHawking Zhang * this should allow us to catch up. 429edc61147SHawking Zhang */ 430edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 431edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 432edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 433edc61147SHawking Zhang wptr, ih->rptr, tmp); 434edc61147SHawking Zhang ih->rptr = tmp; 435edc61147SHawking Zhang 4362d2fbf68SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 437edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 4382d2fbf68SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 439edc61147SHawking Zhang out: 440edc61147SHawking Zhang return (wptr & ih->ptr_mask); 441edc61147SHawking Zhang } 442edc61147SHawking Zhang 443edc61147SHawking Zhang /** 444022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 445022b6518SSamir Dhume * 446022b6518SSamir Dhume * @adev: amdgpu_device pointer 447c56fb081SLee Jones * @ih: IH ring to match 448022b6518SSamir Dhume * 449022b6518SSamir Dhume */ 450022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 451022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 452022b6518SSamir Dhume { 453022b6518SSamir Dhume uint32_t v = 0; 454022b6518SSamir Dhume uint32_t i = 0; 4552d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 456022b6518SSamir Dhume 4572d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 458022b6518SSamir Dhume 459022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 460022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 4612d2fbf68SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 462022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 463022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 464022b6518SSamir Dhume else 465022b6518SSamir Dhume break; 466022b6518SSamir Dhume } 467022b6518SSamir Dhume } 468022b6518SSamir Dhume 469022b6518SSamir Dhume /** 470edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 471edc61147SHawking Zhang * 472edc61147SHawking Zhang * @adev: amdgpu_device pointer 473edc61147SHawking Zhang * 474c56fb081SLee Jones * @ih: IH ring buffer to set rptr 475edc61147SHawking Zhang * Set the IH ring buffer rptr. 476edc61147SHawking Zhang */ 477edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 478edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 479edc61147SHawking Zhang { 4802d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 4812d2fbf68SHawking Zhang 482edc61147SHawking Zhang if (ih->use_doorbell) { 483edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 484edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 485edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 486022b6518SSamir Dhume 487022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 488022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 4892d2fbf68SHawking Zhang } else { 4902d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 4912d2fbf68SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 492ab518012SAlex Sierra } 493ab518012SAlex Sierra } 494ab518012SAlex Sierra 495ab518012SAlex Sierra /** 496ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 497ab518012SAlex Sierra * 498ab518012SAlex Sierra * @adev: amdgpu_device pointer 499ab518012SAlex Sierra * @source: irq source 500ab518012SAlex Sierra * @entry: IV with WPTR update 501ab518012SAlex Sierra * 502ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 503ab518012SAlex Sierra */ 504ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 505ab518012SAlex Sierra struct amdgpu_irq_src *source, 506ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 507ab518012SAlex Sierra { 508ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 509ab518012SAlex Sierra 510ab518012SAlex Sierra switch (entry->ring_id) { 511ab518012SAlex Sierra case 1: 512ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 513ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 514ab518012SAlex Sierra break; 515ab518012SAlex Sierra case 2: 516ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 517ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 518ab518012SAlex Sierra break; 519ab518012SAlex Sierra default: break; 520ab518012SAlex Sierra } 521ab518012SAlex Sierra return 0; 522ab518012SAlex Sierra } 523ab518012SAlex Sierra 524ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 525ab518012SAlex Sierra .process = navi10_ih_self_irq, 526ab518012SAlex Sierra }; 527ab518012SAlex Sierra 528ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 529ab518012SAlex Sierra { 530ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 531ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 532edc61147SHawking Zhang } 533edc61147SHawking Zhang 534edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 535edc61147SHawking Zhang { 536edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 537edc61147SHawking Zhang 538edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 539ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 540edc61147SHawking Zhang return 0; 541edc61147SHawking Zhang } 542edc61147SHawking Zhang 543edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 544edc61147SHawking Zhang { 545edc61147SHawking Zhang int r; 546edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 547edc61147SHawking Zhang bool use_bus_addr; 548edc61147SHawking Zhang 549ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 550ab518012SAlex Sierra &adev->irq.self_irq); 551ab518012SAlex Sierra 552ab518012SAlex Sierra if (r) 553ab518012SAlex Sierra return r; 554ab518012SAlex Sierra 555edc61147SHawking Zhang /* use gpu virtual address for ih ring 556edc61147SHawking Zhang * until ih_checken is programmed to allow 557edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 558bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 559bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 560bf13cb1fSHuang Rui use_bus_addr = false; 561bf13cb1fSHuang Rui else 562bf13cb1fSHuang Rui use_bus_addr = true; 563edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 564edc61147SHawking Zhang if (r) 565edc61147SHawking Zhang return r; 566edc61147SHawking Zhang 567edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 568edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 569edc61147SHawking Zhang 570abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 571abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 572abb6fccbSAlex Sierra 573a362976bSHawking Zhang /* initialize ih control registers offset */ 574a362976bSHawking Zhang navi10_ih_init_register_offset(adev); 575a362976bSHawking Zhang 576d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 577d4581f7dSChristian König if (r) 578d4581f7dSChristian König return r; 579d4581f7dSChristian König 580edc61147SHawking Zhang r = amdgpu_irq_init(adev); 581edc61147SHawking Zhang 582edc61147SHawking Zhang return r; 583edc61147SHawking Zhang } 584edc61147SHawking Zhang 585edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 586edc61147SHawking Zhang { 587edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 588edc61147SHawking Zhang 589edc61147SHawking Zhang amdgpu_irq_fini(adev); 5904a0a0d6dSHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 591ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 592ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 593edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 594edc61147SHawking Zhang 595edc61147SHawking Zhang return 0; 596edc61147SHawking Zhang } 597edc61147SHawking Zhang 598edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 599edc61147SHawking Zhang { 600edc61147SHawking Zhang int r; 601edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 602edc61147SHawking Zhang 603edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 604edc61147SHawking Zhang if (r) 605edc61147SHawking Zhang return r; 606edc61147SHawking Zhang 607edc61147SHawking Zhang return 0; 608edc61147SHawking Zhang } 609edc61147SHawking Zhang 610edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 611edc61147SHawking Zhang { 612edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613edc61147SHawking Zhang 614edc61147SHawking Zhang navi10_ih_irq_disable(adev); 615edc61147SHawking Zhang 616edc61147SHawking Zhang return 0; 617edc61147SHawking Zhang } 618edc61147SHawking Zhang 619edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 620edc61147SHawking Zhang { 621edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 622edc61147SHawking Zhang 623edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 624edc61147SHawking Zhang } 625edc61147SHawking Zhang 626edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 627edc61147SHawking Zhang { 628edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629edc61147SHawking Zhang 630edc61147SHawking Zhang return navi10_ih_hw_init(adev); 631edc61147SHawking Zhang } 632edc61147SHawking Zhang 633edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 634edc61147SHawking Zhang { 635edc61147SHawking Zhang /* todo */ 636edc61147SHawking Zhang return true; 637edc61147SHawking Zhang } 638edc61147SHawking Zhang 639edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 640edc61147SHawking Zhang { 641edc61147SHawking Zhang /* todo */ 642edc61147SHawking Zhang return -ETIMEDOUT; 643edc61147SHawking Zhang } 644edc61147SHawking Zhang 645edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 646edc61147SHawking Zhang { 647edc61147SHawking Zhang /* todo */ 648edc61147SHawking Zhang return 0; 649edc61147SHawking Zhang } 650edc61147SHawking Zhang 651edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 652edc61147SHawking Zhang bool enable) 653edc61147SHawking Zhang { 654edc61147SHawking Zhang uint32_t data, def, field_val; 655edc61147SHawking Zhang 656edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 657edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 658edc61147SHawking Zhang field_val = enable ? 0 : 1; 659edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 660edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 661edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 662edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 663edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 664edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 665edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 666edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 667edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 668edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 669edc61147SHawking Zhang if (def != data) 670edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 671edc61147SHawking Zhang } 672edc61147SHawking Zhang 673edc61147SHawking Zhang return; 674edc61147SHawking Zhang } 675edc61147SHawking Zhang 676edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 677edc61147SHawking Zhang enum amd_clockgating_state state) 678edc61147SHawking Zhang { 679edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 680edc61147SHawking Zhang 681edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 682a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 683edc61147SHawking Zhang return 0; 684edc61147SHawking Zhang } 685edc61147SHawking Zhang 686edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 687edc61147SHawking Zhang enum amd_powergating_state state) 688edc61147SHawking Zhang { 689edc61147SHawking Zhang return 0; 690edc61147SHawking Zhang } 691edc61147SHawking Zhang 692edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 693edc61147SHawking Zhang { 694edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 695edc61147SHawking Zhang 696edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 697edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 698edc61147SHawking Zhang 699edc61147SHawking Zhang return; 700edc61147SHawking Zhang } 701edc61147SHawking Zhang 702edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 703edc61147SHawking Zhang .name = "navi10_ih", 704edc61147SHawking Zhang .early_init = navi10_ih_early_init, 705edc61147SHawking Zhang .late_init = NULL, 706edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 707edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 708edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 709edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 710edc61147SHawking Zhang .suspend = navi10_ih_suspend, 711edc61147SHawking Zhang .resume = navi10_ih_resume, 712edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 713edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 714edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 715edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 716edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 717edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 718edc61147SHawking Zhang }; 719edc61147SHawking Zhang 720edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 721edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 72240838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 723edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 724edc61147SHawking Zhang }; 725edc61147SHawking Zhang 726edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 727edc61147SHawking Zhang { 728edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 729edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 730edc61147SHawking Zhang } 731edc61147SHawking Zhang 732edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 733edc61147SHawking Zhang { 734edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 735edc61147SHawking Zhang .major = 5, 736edc61147SHawking Zhang .minor = 0, 737edc61147SHawking Zhang .rev = 0, 738edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 739edc61147SHawking Zhang }; 740