1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings 445212d163SHawking Zhang * 455212d163SHawking Zhang * @adev: amdgpu_device pointer 465212d163SHawking Zhang * 475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10). 485212d163SHawking Zhang */ 495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 505212d163SHawking Zhang { 515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs; 525212d163SHawking Zhang 535212d163SHawking Zhang if (adev->irq.ih.ring_size) { 545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 645212d163SHawking Zhang } 655212d163SHawking Zhang 665212d163SHawking Zhang if (adev->irq.ih1.ring_size) { 675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 755212d163SHawking Zhang } 765212d163SHawking Zhang 775212d163SHawking Zhang if (adev->irq.ih2.ring_size) { 785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 865212d163SHawking Zhang } 875212d163SHawking Zhang } 885212d163SHawking Zhang 895212d163SHawking Zhang /** 905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 915ea6f9c2SChengming Gui * 925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 965ea6f9c2SChengming Gui * 975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 985ea6f9c2SChengming Gui * real_threshold = 2^threshold 995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 1015ea6f9c2SChengming Gui * 1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 1035ea6f9c2SChengming Gui */ 1045ea6f9c2SChengming Gui static void 1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 1075ea6f9c2SChengming Gui { 1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 1095ea6f9c2SChengming Gui 1105ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 1115ea6f9c2SChengming Gui return; 1125ea6f9c2SChengming Gui 1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 1155ea6f9c2SChengming Gui 1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1225ea6f9c2SChengming Gui 1235ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1245ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 1255ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 1265ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1285ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 1295ea6f9c2SChengming Gui } 1305ea6f9c2SChengming Gui 1315ea6f9c2SChengming Gui /** 1321ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 1331ce6940eSHawking Zhang * 1341ce6940eSHawking Zhang * @adev: amdgpu_device pointer 1351ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet 1361ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 1371ce6940eSHawking Zhang * 1381ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10) 1391ce6940eSHawking Zhang */ 1401ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 1411ce6940eSHawking Zhang struct amdgpu_ih_ring *ih, 1421ce6940eSHawking Zhang bool enable) 1431ce6940eSHawking Zhang { 1441ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs; 1451ce6940eSHawking Zhang uint32_t tmp; 1461ce6940eSHawking Zhang 1471ce6940eSHawking Zhang ih_regs = &ih->ih_regs; 1481ce6940eSHawking Zhang 1491ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 1501ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1511ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */ 1521ce6940eSHawking Zhang if (ih == &adev->irq.ih) 1531ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 1541ce6940eSHawking Zhang if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1551ce6940eSHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 1561ce6940eSHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 1571ce6940eSHawking Zhang return -ETIMEDOUT; 1581ce6940eSHawking Zhang } 1591ce6940eSHawking Zhang } else { 1601ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 1611ce6940eSHawking Zhang } 1621ce6940eSHawking Zhang 1631ce6940eSHawking Zhang if (enable) { 1641ce6940eSHawking Zhang ih->enabled = true; 1651ce6940eSHawking Zhang } else { 1661ce6940eSHawking Zhang /* set rptr, wptr to 0 */ 1671ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 1681ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 1691ce6940eSHawking Zhang ih->enabled = false; 1701ce6940eSHawking Zhang ih->rptr = 0; 1711ce6940eSHawking Zhang } 1721ce6940eSHawking Zhang 1731ce6940eSHawking Zhang return 0; 1741ce6940eSHawking Zhang } 1751ce6940eSHawking Zhang 1766e7b7c7fSHawking Zhang /** 1776e7b7c7fSHawking Zhang * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 1786e7b7c7fSHawking Zhang * 1796e7b7c7fSHawking Zhang * @adev: amdgpu_device pointer 1806e7b7c7fSHawking Zhang * @enable: enable or disable interrupt ring buffers 1816e7b7c7fSHawking Zhang * 1826e7b7c7fSHawking Zhang * Toggle all the available interrupt ring buffers (NAVI10). 1836e7b7c7fSHawking Zhang */ 1846e7b7c7fSHawking Zhang static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 1856e7b7c7fSHawking Zhang { 1866e7b7c7fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 1876e7b7c7fSHawking Zhang int i; 1886e7b7c7fSHawking Zhang int r; 1896e7b7c7fSHawking Zhang 1906e7b7c7fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 1916e7b7c7fSHawking Zhang if (ih[i]->ring_size) { 1926e7b7c7fSHawking Zhang r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 1936e7b7c7fSHawking Zhang if (r) 1946e7b7c7fSHawking Zhang return r; 1956e7b7c7fSHawking Zhang } 1966e7b7c7fSHawking Zhang } 1976e7b7c7fSHawking Zhang 1986e7b7c7fSHawking Zhang return 0; 1996e7b7c7fSHawking Zhang } 2006e7b7c7fSHawking Zhang 201edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 202edc61147SHawking Zhang { 203edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 204edc61147SHawking Zhang 205edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 206edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 207edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 208edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 209edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 210edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 211edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 212edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 213edc61147SHawking Zhang * value is written to memory 214edc61147SHawking Zhang */ 215edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 217edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 218edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 219edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 220edc61147SHawking Zhang 221edc61147SHawking Zhang return ih_rb_cntl; 222edc61147SHawking Zhang } 223edc61147SHawking Zhang 224ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 225ab518012SAlex Sierra { 226ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 227ab518012SAlex Sierra 228ab518012SAlex Sierra if (ih->use_doorbell) { 229ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 231ab518012SAlex Sierra ih->doorbell_index); 232ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 233ab518012SAlex Sierra IH_DOORBELL_RPTR, 234ab518012SAlex Sierra ENABLE, 1); 235ab518012SAlex Sierra } else { 236ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 237ab518012SAlex Sierra IH_DOORBELL_RPTR, 238ab518012SAlex Sierra ENABLE, 0); 239ab518012SAlex Sierra } 240ab518012SAlex Sierra return ih_doorbell_rtpr; 241ab518012SAlex Sierra } 242ab518012SAlex Sierra 2431514cb7dSHawking Zhang /** 2441514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer 2451514cb7dSHawking Zhang * 2461514cb7dSHawking Zhang * @adev: amdgpu_device pointer 2471514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer 2481514cb7dSHawking Zhang * 2491514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10) 2501514cb7dSHawking Zhang */ 2511514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev, 2521514cb7dSHawking Zhang struct amdgpu_ih_ring *ih) 2531514cb7dSHawking Zhang { 2541514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs; 2551514cb7dSHawking Zhang uint32_t tmp; 2561514cb7dSHawking Zhang 2571514cb7dSHawking Zhang ih_regs = &ih->ih_regs; 2581514cb7dSHawking Zhang 2591514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 2601514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 2611514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 2621514cb7dSHawking Zhang 2631514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 2641514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp); 2651514cb7dSHawking Zhang if (ih == &adev->irq.ih) 2661514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 2671514cb7dSHawking Zhang if (ih == &adev->irq.ih1) { 2681514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 2691514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 2701514cb7dSHawking Zhang } 2711514cb7dSHawking Zhang if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 2721514cb7dSHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 2731514cb7dSHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 2741514cb7dSHawking Zhang return -ETIMEDOUT; 2751514cb7dSHawking Zhang } 2761514cb7dSHawking Zhang } else { 2771514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 2781514cb7dSHawking Zhang } 2791514cb7dSHawking Zhang 2801514cb7dSHawking Zhang if (ih == &adev->irq.ih) { 2811514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 2821514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 2831514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 2841514cb7dSHawking Zhang } 2851514cb7dSHawking Zhang 2861514cb7dSHawking Zhang /* set rptr, wptr to 0 */ 2871514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 2881514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 2891514cb7dSHawking Zhang 2901514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 2911514cb7dSHawking Zhang 2921514cb7dSHawking Zhang return 0; 2931514cb7dSHawking Zhang } 2941514cb7dSHawking Zhang 2959e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 2969e94ff33SAlex Sierra { 2979e94ff33SAlex Sierra uint32_t tmp; 2989e94ff33SAlex Sierra 2999e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 3009e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 3019e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 3029e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 3039e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 3049e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 3059e94ff33SAlex Sierra 3069e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 3079e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 3089e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 3099e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 3109e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 3119e94ff33SAlex Sierra } 3129e94ff33SAlex Sierra 313edc61147SHawking Zhang /** 314edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 315edc61147SHawking Zhang * 316edc61147SHawking Zhang * @adev: amdgpu_device pointer 317edc61147SHawking Zhang * 318edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 319edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 320edc61147SHawking Zhang * ring buffer and enable it (NAVI). 321edc61147SHawking Zhang * Called at device load and reume. 322edc61147SHawking Zhang * Returns 0 for success, errors for failure. 323edc61147SHawking Zhang */ 324edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 325edc61147SHawking Zhang { 326fc4aa19fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 327fc4aa19fSHawking Zhang u32 ih_chicken; 328edc61147SHawking Zhang u32 tmp; 3296e7b7c7fSHawking Zhang int ret; 330fc4aa19fSHawking Zhang int i; 331edc61147SHawking Zhang 332edc61147SHawking Zhang /* disable irqs */ 3336e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, false); 3346e7b7c7fSHawking Zhang if (ret) 3356e7b7c7fSHawking Zhang return ret; 336edc61147SHawking Zhang 337bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 338edc61147SHawking Zhang 339edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 340fc4aa19fSHawking Zhang if (ih[0]->use_bus_addr) { 341757b3af8SLikun Gao switch (adev->asic_type) { 342757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 343026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 344bd4f2811SHuang Rui case CHIP_VANGOGH: 345771cc67eSTao Zhou case CHIP_DIMGREY_CAVEFISH: 346757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 347757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 348757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 349757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 350757b3af8SLikun Gao break; 351757b3af8SLikun Gao default: 352edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 353edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 354edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 355edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 356757b3af8SLikun Gao break; 357757b3af8SLikun Gao } 358edc61147SHawking Zhang } 359edc61147SHawking Zhang } 360edc61147SHawking Zhang 361fc4aa19fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 362fc4aa19fSHawking Zhang if (ih[i]->ring_size) { 363fc4aa19fSHawking Zhang ret = navi10_ih_enable_ring(adev, ih[i]); 364fc4aa19fSHawking Zhang if (ret) 365fc4aa19fSHawking Zhang return ret; 3660ab176e6SAlex Sierra } 367ab518012SAlex Sierra } 368ab518012SAlex Sierra 369fc4aa19fSHawking Zhang /* update doorbell range for ih ring 0*/ 370fc4aa19fSHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 371fc4aa19fSHawking Zhang ih[0]->doorbell_index); 372ab518012SAlex Sierra 373edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 374edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 375edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 376edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 377edc61147SHawking Zhang 378edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 379edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 380edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 381edc61147SHawking Zhang 382edc61147SHawking Zhang pci_set_master(adev->pdev); 383edc61147SHawking Zhang 384edc61147SHawking Zhang /* enable interrupts */ 3856e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, true); 3866e7b7c7fSHawking Zhang if (ret) 3876e7b7c7fSHawking Zhang return ret; 3885ea6f9c2SChengming Gui /* enable wptr force update for self int */ 3895ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 390edc61147SHawking Zhang 3917eca4006SMa Feng return 0; 392edc61147SHawking Zhang } 393edc61147SHawking Zhang 394edc61147SHawking Zhang /** 395edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 396edc61147SHawking Zhang * 397edc61147SHawking Zhang * @adev: amdgpu_device pointer 398edc61147SHawking Zhang * 399edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 400edc61147SHawking Zhang */ 401edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 402edc61147SHawking Zhang { 4035ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 4046e7b7c7fSHawking Zhang navi10_ih_toggle_interrupts(adev, false); 405edc61147SHawking Zhang 406edc61147SHawking Zhang /* Wait and acknowledge irq */ 407edc61147SHawking Zhang mdelay(1); 408edc61147SHawking Zhang } 409edc61147SHawking Zhang 410edc61147SHawking Zhang /** 411edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 412edc61147SHawking Zhang * 413edc61147SHawking Zhang * @adev: amdgpu_device pointer 414c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 415edc61147SHawking Zhang * 416edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 417edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 418edc61147SHawking Zhang * ring buffer overflow and deal with it. 419edc61147SHawking Zhang * Returns the value of the wptr. 420edc61147SHawking Zhang */ 421edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 422edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 423edc61147SHawking Zhang { 424*2d2fbf68SHawking Zhang u32 wptr, tmp; 425*2d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 426edc61147SHawking Zhang 427edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 428*2d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 429edc61147SHawking Zhang 430edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 431edc61147SHawking Zhang goto out; 432edc61147SHawking Zhang 433*2d2fbf68SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 434edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 435edc61147SHawking Zhang goto out; 436edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 437edc61147SHawking Zhang 438edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 439edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 440edc61147SHawking Zhang * this should allow us to catch up. 441edc61147SHawking Zhang */ 442edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 443edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 444edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 445edc61147SHawking Zhang wptr, ih->rptr, tmp); 446edc61147SHawking Zhang ih->rptr = tmp; 447edc61147SHawking Zhang 448*2d2fbf68SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 449edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 450*2d2fbf68SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 451edc61147SHawking Zhang out: 452edc61147SHawking Zhang return (wptr & ih->ptr_mask); 453edc61147SHawking Zhang } 454edc61147SHawking Zhang 455edc61147SHawking Zhang /** 456edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 457edc61147SHawking Zhang * 458edc61147SHawking Zhang * @adev: amdgpu_device pointer 459c56fb081SLee Jones * @ih: IH ring buffer to decode 460c56fb081SLee Jones * @entry: IV entry to place decoded information into 461edc61147SHawking Zhang * 462edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 463edc61147SHawking Zhang * position and also advance the position. 464edc61147SHawking Zhang */ 465edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 466edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 467edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 468edc61147SHawking Zhang { 469edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 470edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 471edc61147SHawking Zhang uint32_t dw[8]; 472edc61147SHawking Zhang 473edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 474edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 475edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 476edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 477edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 478edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 479edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 480edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 481edc61147SHawking Zhang 482edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 483edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 484edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 485edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 486edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 487edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 488edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 489edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 490edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 491edc61147SHawking Zhang entry->src_data[0] = dw[4]; 492edc61147SHawking Zhang entry->src_data[1] = dw[5]; 493edc61147SHawking Zhang entry->src_data[2] = dw[6]; 494edc61147SHawking Zhang entry->src_data[3] = dw[7]; 495edc61147SHawking Zhang 496edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 497edc61147SHawking Zhang ih->rptr += 32; 498edc61147SHawking Zhang } 499edc61147SHawking Zhang 500edc61147SHawking Zhang /** 501022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 502022b6518SSamir Dhume * 503022b6518SSamir Dhume * @adev: amdgpu_device pointer 504c56fb081SLee Jones * @ih: IH ring to match 505022b6518SSamir Dhume * 506022b6518SSamir Dhume */ 507022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 508022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 509022b6518SSamir Dhume { 510022b6518SSamir Dhume uint32_t v = 0; 511022b6518SSamir Dhume uint32_t i = 0; 512*2d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 513022b6518SSamir Dhume 514*2d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 515022b6518SSamir Dhume 516022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 517022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 518*2d2fbf68SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 519022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 520022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 521022b6518SSamir Dhume else 522022b6518SSamir Dhume break; 523022b6518SSamir Dhume } 524022b6518SSamir Dhume } 525022b6518SSamir Dhume 526022b6518SSamir Dhume /** 527edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 528edc61147SHawking Zhang * 529edc61147SHawking Zhang * @adev: amdgpu_device pointer 530edc61147SHawking Zhang * 531c56fb081SLee Jones * @ih: IH ring buffer to set rptr 532edc61147SHawking Zhang * Set the IH ring buffer rptr. 533edc61147SHawking Zhang */ 534edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 535edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 536edc61147SHawking Zhang { 537*2d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 538*2d2fbf68SHawking Zhang 539edc61147SHawking Zhang if (ih->use_doorbell) { 540edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 541edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 542edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 543022b6518SSamir Dhume 544022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 545022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 546*2d2fbf68SHawking Zhang } else { 547*2d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 548*2d2fbf68SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 549ab518012SAlex Sierra } 550ab518012SAlex Sierra } 551ab518012SAlex Sierra 552ab518012SAlex Sierra /** 553ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 554ab518012SAlex Sierra * 555ab518012SAlex Sierra * @adev: amdgpu_device pointer 556ab518012SAlex Sierra * @source: irq source 557ab518012SAlex Sierra * @entry: IV with WPTR update 558ab518012SAlex Sierra * 559ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 560ab518012SAlex Sierra */ 561ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 562ab518012SAlex Sierra struct amdgpu_irq_src *source, 563ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 564ab518012SAlex Sierra { 565ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 566ab518012SAlex Sierra 567ab518012SAlex Sierra switch (entry->ring_id) { 568ab518012SAlex Sierra case 1: 569ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 570ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 571ab518012SAlex Sierra break; 572ab518012SAlex Sierra case 2: 573ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 574ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 575ab518012SAlex Sierra break; 576ab518012SAlex Sierra default: break; 577ab518012SAlex Sierra } 578ab518012SAlex Sierra return 0; 579ab518012SAlex Sierra } 580ab518012SAlex Sierra 581ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 582ab518012SAlex Sierra .process = navi10_ih_self_irq, 583ab518012SAlex Sierra }; 584ab518012SAlex Sierra 585ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 586ab518012SAlex Sierra { 587ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 588ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 589edc61147SHawking Zhang } 590edc61147SHawking Zhang 591edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 592edc61147SHawking Zhang { 593edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 594edc61147SHawking Zhang 595edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 596ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 597edc61147SHawking Zhang return 0; 598edc61147SHawking Zhang } 599edc61147SHawking Zhang 600edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 601edc61147SHawking Zhang { 602edc61147SHawking Zhang int r; 603edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604edc61147SHawking Zhang bool use_bus_addr; 605edc61147SHawking Zhang 606ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 607ab518012SAlex Sierra &adev->irq.self_irq); 608ab518012SAlex Sierra 609ab518012SAlex Sierra if (r) 610ab518012SAlex Sierra return r; 611ab518012SAlex Sierra 612edc61147SHawking Zhang /* use gpu virtual address for ih ring 613edc61147SHawking Zhang * until ih_checken is programmed to allow 614edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 615bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 616bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 617bf13cb1fSHuang Rui use_bus_addr = false; 618bf13cb1fSHuang Rui else 619bf13cb1fSHuang Rui use_bus_addr = true; 620edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 621edc61147SHawking Zhang if (r) 622edc61147SHawking Zhang return r; 623edc61147SHawking Zhang 624edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 625edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 626edc61147SHawking Zhang 627abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 628abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 629abb6fccbSAlex Sierra 630abb6fccbSAlex Sierra if (adev->asic_type < CHIP_NAVI10) { 631ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 632ab518012SAlex Sierra if (r) 633ab518012SAlex Sierra return r; 634ab518012SAlex Sierra 635ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 636abb6fccbSAlex Sierra adev->irq.ih1.doorbell_index = 637abb6fccbSAlex Sierra (adev->doorbell_index.ih + 1) << 1; 638ab518012SAlex Sierra 639ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 640ab518012SAlex Sierra if (r) 641ab518012SAlex Sierra return r; 642ab518012SAlex Sierra 643ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 644abb6fccbSAlex Sierra adev->irq.ih2.doorbell_index = 645abb6fccbSAlex Sierra (adev->doorbell_index.ih + 2) << 1; 646abb6fccbSAlex Sierra } 647ab518012SAlex Sierra 648a362976bSHawking Zhang /* initialize ih control registers offset */ 649a362976bSHawking Zhang navi10_ih_init_register_offset(adev); 650a362976bSHawking Zhang 651d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 652d4581f7dSChristian König if (r) 653d4581f7dSChristian König return r; 654d4581f7dSChristian König 655edc61147SHawking Zhang r = amdgpu_irq_init(adev); 656edc61147SHawking Zhang 657edc61147SHawking Zhang return r; 658edc61147SHawking Zhang } 659edc61147SHawking Zhang 660edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 661edc61147SHawking Zhang { 662edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 663edc61147SHawking Zhang 664edc61147SHawking Zhang amdgpu_irq_fini(adev); 665ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 666ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 667edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 668edc61147SHawking Zhang 669edc61147SHawking Zhang return 0; 670edc61147SHawking Zhang } 671edc61147SHawking Zhang 672edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 673edc61147SHawking Zhang { 674edc61147SHawking Zhang int r; 675edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676edc61147SHawking Zhang 677edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 678edc61147SHawking Zhang if (r) 679edc61147SHawking Zhang return r; 680edc61147SHawking Zhang 681edc61147SHawking Zhang return 0; 682edc61147SHawking Zhang } 683edc61147SHawking Zhang 684edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 685edc61147SHawking Zhang { 686edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687edc61147SHawking Zhang 688edc61147SHawking Zhang navi10_ih_irq_disable(adev); 689edc61147SHawking Zhang 690edc61147SHawking Zhang return 0; 691edc61147SHawking Zhang } 692edc61147SHawking Zhang 693edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 694edc61147SHawking Zhang { 695edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 696edc61147SHawking Zhang 697edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 698edc61147SHawking Zhang } 699edc61147SHawking Zhang 700edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 701edc61147SHawking Zhang { 702edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 703edc61147SHawking Zhang 704edc61147SHawking Zhang return navi10_ih_hw_init(adev); 705edc61147SHawking Zhang } 706edc61147SHawking Zhang 707edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 708edc61147SHawking Zhang { 709edc61147SHawking Zhang /* todo */ 710edc61147SHawking Zhang return true; 711edc61147SHawking Zhang } 712edc61147SHawking Zhang 713edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 714edc61147SHawking Zhang { 715edc61147SHawking Zhang /* todo */ 716edc61147SHawking Zhang return -ETIMEDOUT; 717edc61147SHawking Zhang } 718edc61147SHawking Zhang 719edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 720edc61147SHawking Zhang { 721edc61147SHawking Zhang /* todo */ 722edc61147SHawking Zhang return 0; 723edc61147SHawking Zhang } 724edc61147SHawking Zhang 725edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 726edc61147SHawking Zhang bool enable) 727edc61147SHawking Zhang { 728edc61147SHawking Zhang uint32_t data, def, field_val; 729edc61147SHawking Zhang 730edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 731edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 732edc61147SHawking Zhang field_val = enable ? 0 : 1; 733edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 734edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 735edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 736edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 737edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 738edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 739edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 740edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 741edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 742edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 743edc61147SHawking Zhang if (def != data) 744edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 745edc61147SHawking Zhang } 746edc61147SHawking Zhang 747edc61147SHawking Zhang return; 748edc61147SHawking Zhang } 749edc61147SHawking Zhang 750edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 751edc61147SHawking Zhang enum amd_clockgating_state state) 752edc61147SHawking Zhang { 753edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 754edc61147SHawking Zhang 755edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 756a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 757edc61147SHawking Zhang return 0; 758edc61147SHawking Zhang } 759edc61147SHawking Zhang 760edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 761edc61147SHawking Zhang enum amd_powergating_state state) 762edc61147SHawking Zhang { 763edc61147SHawking Zhang return 0; 764edc61147SHawking Zhang } 765edc61147SHawking Zhang 766edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 767edc61147SHawking Zhang { 768edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 769edc61147SHawking Zhang 770edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 771edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 772edc61147SHawking Zhang 773edc61147SHawking Zhang return; 774edc61147SHawking Zhang } 775edc61147SHawking Zhang 776edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 777edc61147SHawking Zhang .name = "navi10_ih", 778edc61147SHawking Zhang .early_init = navi10_ih_early_init, 779edc61147SHawking Zhang .late_init = NULL, 780edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 781edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 782edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 783edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 784edc61147SHawking Zhang .suspend = navi10_ih_suspend, 785edc61147SHawking Zhang .resume = navi10_ih_resume, 786edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 787edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 788edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 789edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 790edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 791edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 792edc61147SHawking Zhang }; 793edc61147SHawking Zhang 794edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 795edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 796edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 797edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 798edc61147SHawking Zhang }; 799edc61147SHawking Zhang 800edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 801edc61147SHawking Zhang { 802edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 803edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 804edc61147SHawking Zhang } 805edc61147SHawking Zhang 806edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 807edc61147SHawking Zhang { 808edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 809edc61147SHawking Zhang .major = 5, 810edc61147SHawking Zhang .minor = 0, 811edc61147SHawking Zhang .rev = 0, 812edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 813edc61147SHawking Zhang }; 814