1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings 445212d163SHawking Zhang * 455212d163SHawking Zhang * @adev: amdgpu_device pointer 465212d163SHawking Zhang * 475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10). 485212d163SHawking Zhang */ 495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 505212d163SHawking Zhang { 515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs; 525212d163SHawking Zhang 535212d163SHawking Zhang if (adev->irq.ih.ring_size) { 545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 645212d163SHawking Zhang } 655212d163SHawking Zhang 665212d163SHawking Zhang if (adev->irq.ih1.ring_size) { 675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 755212d163SHawking Zhang } 765212d163SHawking Zhang 775212d163SHawking Zhang if (adev->irq.ih2.ring_size) { 785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 865212d163SHawking Zhang } 875212d163SHawking Zhang } 885212d163SHawking Zhang 895212d163SHawking Zhang /** 905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 915ea6f9c2SChengming Gui * 925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 965ea6f9c2SChengming Gui * 975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 985ea6f9c2SChengming Gui * real_threshold = 2^threshold 995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 1015ea6f9c2SChengming Gui * 1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 1035ea6f9c2SChengming Gui */ 1045ea6f9c2SChengming Gui static void 1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 1075ea6f9c2SChengming Gui { 1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 1095ea6f9c2SChengming Gui 110*1d789535SAlex Deucher if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3)) 1115ea6f9c2SChengming Gui return; 1125ea6f9c2SChengming Gui 1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 1155ea6f9c2SChengming Gui 1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1225ea6f9c2SChengming Gui 1232b9ced5aSRohit Khaire if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 1242b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) 1252b9ced5aSRohit Khaire return; 1262b9ced5aSRohit Khaire } else { 1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1282b9ced5aSRohit Khaire } 1292b9ced5aSRohit Khaire 1305ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 1315ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 1325ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1332b9ced5aSRohit Khaire if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 1342b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) 1352b9ced5aSRohit Khaire return; 1362b9ced5aSRohit Khaire } else { 1375ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1382b9ced5aSRohit Khaire } 1392b9ced5aSRohit Khaire 1405ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 1415ea6f9c2SChengming Gui } 1425ea6f9c2SChengming Gui 1435ea6f9c2SChengming Gui /** 1441ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 1451ce6940eSHawking Zhang * 1461ce6940eSHawking Zhang * @adev: amdgpu_device pointer 1471ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet 1481ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 1491ce6940eSHawking Zhang * 1501ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10) 1511ce6940eSHawking Zhang */ 1521ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 1531ce6940eSHawking Zhang struct amdgpu_ih_ring *ih, 1541ce6940eSHawking Zhang bool enable) 1551ce6940eSHawking Zhang { 1561ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs; 1571ce6940eSHawking Zhang uint32_t tmp; 1581ce6940eSHawking Zhang 1591ce6940eSHawking Zhang ih_regs = &ih->ih_regs; 1601ce6940eSHawking Zhang 1611ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 1621ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1631ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */ 1641ce6940eSHawking Zhang if (ih == &adev->irq.ih) 1651ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 1664aa7e6e0SYuBiao Wang 1674aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 1682b9ced5aSRohit Khaire if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) 1694aa7e6e0SYuBiao Wang return -ETIMEDOUT; 1704aa7e6e0SYuBiao Wang } else { 1711ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 1724aa7e6e0SYuBiao Wang } 1731ce6940eSHawking Zhang 1741ce6940eSHawking Zhang if (enable) { 1751ce6940eSHawking Zhang ih->enabled = true; 1761ce6940eSHawking Zhang } else { 1771ce6940eSHawking Zhang /* set rptr, wptr to 0 */ 1781ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 1791ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 1801ce6940eSHawking Zhang ih->enabled = false; 1811ce6940eSHawking Zhang ih->rptr = 0; 1821ce6940eSHawking Zhang } 1831ce6940eSHawking Zhang 1841ce6940eSHawking Zhang return 0; 1851ce6940eSHawking Zhang } 1861ce6940eSHawking Zhang 1876e7b7c7fSHawking Zhang /** 1886e7b7c7fSHawking Zhang * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 1896e7b7c7fSHawking Zhang * 1906e7b7c7fSHawking Zhang * @adev: amdgpu_device pointer 1916e7b7c7fSHawking Zhang * @enable: enable or disable interrupt ring buffers 1926e7b7c7fSHawking Zhang * 1936e7b7c7fSHawking Zhang * Toggle all the available interrupt ring buffers (NAVI10). 1946e7b7c7fSHawking Zhang */ 1956e7b7c7fSHawking Zhang static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 1966e7b7c7fSHawking Zhang { 1976e7b7c7fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 1986e7b7c7fSHawking Zhang int i; 1996e7b7c7fSHawking Zhang int r; 2006e7b7c7fSHawking Zhang 2016e7b7c7fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 2026e7b7c7fSHawking Zhang if (ih[i]->ring_size) { 2036e7b7c7fSHawking Zhang r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 2046e7b7c7fSHawking Zhang if (r) 2056e7b7c7fSHawking Zhang return r; 2066e7b7c7fSHawking Zhang } 2076e7b7c7fSHawking Zhang } 2086e7b7c7fSHawking Zhang 2096e7b7c7fSHawking Zhang return 0; 2106e7b7c7fSHawking Zhang } 2116e7b7c7fSHawking Zhang 212edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 213edc61147SHawking Zhang { 214edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 215edc61147SHawking Zhang 216edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 217edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 218edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 219edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 220edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 221edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 222edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 223edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 224edc61147SHawking Zhang * value is written to memory 225edc61147SHawking Zhang */ 226edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 227edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 228edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 229edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 230edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 231edc61147SHawking Zhang 232edc61147SHawking Zhang return ih_rb_cntl; 233edc61147SHawking Zhang } 234edc61147SHawking Zhang 235ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 236ab518012SAlex Sierra { 237ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 238ab518012SAlex Sierra 239ab518012SAlex Sierra if (ih->use_doorbell) { 240ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 241ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 242ab518012SAlex Sierra ih->doorbell_index); 243ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 244ab518012SAlex Sierra IH_DOORBELL_RPTR, 245ab518012SAlex Sierra ENABLE, 1); 246ab518012SAlex Sierra } else { 247ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 248ab518012SAlex Sierra IH_DOORBELL_RPTR, 249ab518012SAlex Sierra ENABLE, 0); 250ab518012SAlex Sierra } 251ab518012SAlex Sierra return ih_doorbell_rtpr; 252ab518012SAlex Sierra } 253ab518012SAlex Sierra 2541514cb7dSHawking Zhang /** 2551514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer 2561514cb7dSHawking Zhang * 2571514cb7dSHawking Zhang * @adev: amdgpu_device pointer 2581514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer 2591514cb7dSHawking Zhang * 2601514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10) 2611514cb7dSHawking Zhang */ 2621514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev, 2631514cb7dSHawking Zhang struct amdgpu_ih_ring *ih) 2641514cb7dSHawking Zhang { 2651514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs; 2661514cb7dSHawking Zhang uint32_t tmp; 2671514cb7dSHawking Zhang 2681514cb7dSHawking Zhang ih_regs = &ih->ih_regs; 2691514cb7dSHawking Zhang 2701514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 2711514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 2721514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 2731514cb7dSHawking Zhang 2741514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 2751514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp); 2761514cb7dSHawking Zhang if (ih == &adev->irq.ih) 2771514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 2781514cb7dSHawking Zhang if (ih == &adev->irq.ih1) { 2791514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 2801514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 2811514cb7dSHawking Zhang } 2824aa7e6e0SYuBiao Wang 2834aa7e6e0SYuBiao Wang if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 2844aa7e6e0SYuBiao Wang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 2854aa7e6e0SYuBiao Wang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 2864aa7e6e0SYuBiao Wang return -ETIMEDOUT; 2874aa7e6e0SYuBiao Wang } 2884aa7e6e0SYuBiao Wang } else { 2891514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 2904aa7e6e0SYuBiao Wang } 2911514cb7dSHawking Zhang 2921514cb7dSHawking Zhang if (ih == &adev->irq.ih) { 2931514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 2941514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 2951514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 2961514cb7dSHawking Zhang } 2971514cb7dSHawking Zhang 2981514cb7dSHawking Zhang /* set rptr, wptr to 0 */ 2991514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 3001514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 3011514cb7dSHawking Zhang 3021514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 3031514cb7dSHawking Zhang 3041514cb7dSHawking Zhang return 0; 3051514cb7dSHawking Zhang } 3061514cb7dSHawking Zhang 307edc61147SHawking Zhang /** 308edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 309edc61147SHawking Zhang * 310edc61147SHawking Zhang * @adev: amdgpu_device pointer 311edc61147SHawking Zhang * 312edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 313edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 314edc61147SHawking Zhang * ring buffer and enable it (NAVI). 315edc61147SHawking Zhang * Called at device load and reume. 316edc61147SHawking Zhang * Returns 0 for success, errors for failure. 317edc61147SHawking Zhang */ 318edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 319edc61147SHawking Zhang { 320fc4aa19fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 321fc4aa19fSHawking Zhang u32 ih_chicken; 322edc61147SHawking Zhang u32 tmp; 3236e7b7c7fSHawking Zhang int ret; 324fc4aa19fSHawking Zhang int i; 325edc61147SHawking Zhang 326edc61147SHawking Zhang /* disable irqs */ 3276e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, false); 3286e7b7c7fSHawking Zhang if (ret) 3296e7b7c7fSHawking Zhang return ret; 330edc61147SHawking Zhang 331bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 332edc61147SHawking Zhang 333edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 334fc4aa19fSHawking Zhang if (ih[0]->use_bus_addr) { 335*1d789535SAlex Deucher switch (adev->ip_versions[OSSSYS_HWIP][0]) { 3367c69d615SAlex Deucher case IP_VERSION(5, 0, 3): 3377c69d615SAlex Deucher case IP_VERSION(5, 2, 0): 3387c69d615SAlex Deucher case IP_VERSION(5, 2, 1): 339757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 340757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 341757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 342757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 343757b3af8SLikun Gao break; 344757b3af8SLikun Gao default: 345edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 346edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 347edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 348edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 349757b3af8SLikun Gao break; 350757b3af8SLikun Gao } 351edc61147SHawking Zhang } 352edc61147SHawking Zhang } 353edc61147SHawking Zhang 354fc4aa19fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 355fc4aa19fSHawking Zhang if (ih[i]->ring_size) { 356fc4aa19fSHawking Zhang ret = navi10_ih_enable_ring(adev, ih[i]); 357fc4aa19fSHawking Zhang if (ret) 358fc4aa19fSHawking Zhang return ret; 3590ab176e6SAlex Sierra } 360ab518012SAlex Sierra } 361ab518012SAlex Sierra 362fc4aa19fSHawking Zhang /* update doorbell range for ih ring 0*/ 363fc4aa19fSHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 364fc4aa19fSHawking Zhang ih[0]->doorbell_index); 365ab518012SAlex Sierra 366edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 367edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 368edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 369edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 370edc61147SHawking Zhang 371edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 372edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 373edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 374edc61147SHawking Zhang 375edc61147SHawking Zhang pci_set_master(adev->pdev); 376edc61147SHawking Zhang 377edc61147SHawking Zhang /* enable interrupts */ 3786e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, true); 3796e7b7c7fSHawking Zhang if (ret) 3806e7b7c7fSHawking Zhang return ret; 3815ea6f9c2SChengming Gui /* enable wptr force update for self int */ 3825ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 383edc61147SHawking Zhang 3847f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size) 3857f03b148SHawking Zhang adev->irq.ih_soft.enabled = true; 3867f03b148SHawking Zhang 3877eca4006SMa Feng return 0; 388edc61147SHawking Zhang } 389edc61147SHawking Zhang 390edc61147SHawking Zhang /** 391edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 392edc61147SHawking Zhang * 393edc61147SHawking Zhang * @adev: amdgpu_device pointer 394edc61147SHawking Zhang * 395edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 396edc61147SHawking Zhang */ 397edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 398edc61147SHawking Zhang { 3995ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 4006e7b7c7fSHawking Zhang navi10_ih_toggle_interrupts(adev, false); 401edc61147SHawking Zhang 402edc61147SHawking Zhang /* Wait and acknowledge irq */ 403edc61147SHawking Zhang mdelay(1); 404edc61147SHawking Zhang } 405edc61147SHawking Zhang 406edc61147SHawking Zhang /** 407edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 408edc61147SHawking Zhang * 409edc61147SHawking Zhang * @adev: amdgpu_device pointer 410c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 411edc61147SHawking Zhang * 412edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 413edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 414edc61147SHawking Zhang * ring buffer overflow and deal with it. 415edc61147SHawking Zhang * Returns the value of the wptr. 416edc61147SHawking Zhang */ 417edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 418edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 419edc61147SHawking Zhang { 4202d2fbf68SHawking Zhang u32 wptr, tmp; 4212d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 422edc61147SHawking Zhang 423edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 4242d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 425edc61147SHawking Zhang 426edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 427edc61147SHawking Zhang goto out; 428edc61147SHawking Zhang 4292d2fbf68SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 430edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 431edc61147SHawking Zhang goto out; 432edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 433edc61147SHawking Zhang 434edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 435edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 436edc61147SHawking Zhang * this should allow us to catch up. 437edc61147SHawking Zhang */ 438edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 439edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 440edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 441edc61147SHawking Zhang wptr, ih->rptr, tmp); 442edc61147SHawking Zhang ih->rptr = tmp; 443edc61147SHawking Zhang 4442d2fbf68SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 445edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 4462d2fbf68SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 447edc61147SHawking Zhang out: 448edc61147SHawking Zhang return (wptr & ih->ptr_mask); 449edc61147SHawking Zhang } 450edc61147SHawking Zhang 451edc61147SHawking Zhang /** 452022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 453022b6518SSamir Dhume * 454022b6518SSamir Dhume * @adev: amdgpu_device pointer 455c56fb081SLee Jones * @ih: IH ring to match 456022b6518SSamir Dhume * 457022b6518SSamir Dhume */ 458022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 459022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 460022b6518SSamir Dhume { 461022b6518SSamir Dhume uint32_t v = 0; 462022b6518SSamir Dhume uint32_t i = 0; 4632d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 464022b6518SSamir Dhume 4652d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 466022b6518SSamir Dhume 467022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 468022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 4692d2fbf68SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 470022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 471022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 472022b6518SSamir Dhume else 473022b6518SSamir Dhume break; 474022b6518SSamir Dhume } 475022b6518SSamir Dhume } 476022b6518SSamir Dhume 477022b6518SSamir Dhume /** 478edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 479edc61147SHawking Zhang * 480edc61147SHawking Zhang * @adev: amdgpu_device pointer 481edc61147SHawking Zhang * 482c56fb081SLee Jones * @ih: IH ring buffer to set rptr 483edc61147SHawking Zhang * Set the IH ring buffer rptr. 484edc61147SHawking Zhang */ 485edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 486edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 487edc61147SHawking Zhang { 4882d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 4892d2fbf68SHawking Zhang 490edc61147SHawking Zhang if (ih->use_doorbell) { 491edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 492edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 493edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 494022b6518SSamir Dhume 495022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 496022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 4972d2fbf68SHawking Zhang } else { 4982d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 4992d2fbf68SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 500ab518012SAlex Sierra } 501ab518012SAlex Sierra } 502ab518012SAlex Sierra 503ab518012SAlex Sierra /** 504ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 505ab518012SAlex Sierra * 506ab518012SAlex Sierra * @adev: amdgpu_device pointer 507ab518012SAlex Sierra * @source: irq source 508ab518012SAlex Sierra * @entry: IV with WPTR update 509ab518012SAlex Sierra * 510ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 511ab518012SAlex Sierra */ 512ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 513ab518012SAlex Sierra struct amdgpu_irq_src *source, 514ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 515ab518012SAlex Sierra { 516ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 517ab518012SAlex Sierra 518ab518012SAlex Sierra switch (entry->ring_id) { 519ab518012SAlex Sierra case 1: 520ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 521ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 522ab518012SAlex Sierra break; 523ab518012SAlex Sierra case 2: 524ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 525ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 526ab518012SAlex Sierra break; 527ab518012SAlex Sierra default: break; 528ab518012SAlex Sierra } 529ab518012SAlex Sierra return 0; 530ab518012SAlex Sierra } 531ab518012SAlex Sierra 532ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 533ab518012SAlex Sierra .process = navi10_ih_self_irq, 534ab518012SAlex Sierra }; 535ab518012SAlex Sierra 536ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 537ab518012SAlex Sierra { 538ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 539ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 540edc61147SHawking Zhang } 541edc61147SHawking Zhang 542edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 543edc61147SHawking Zhang { 544edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 545edc61147SHawking Zhang 546edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 547ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 548edc61147SHawking Zhang return 0; 549edc61147SHawking Zhang } 550edc61147SHawking Zhang 551edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 552edc61147SHawking Zhang { 553edc61147SHawking Zhang int r; 554edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 555edc61147SHawking Zhang bool use_bus_addr; 556edc61147SHawking Zhang 557ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 558ab518012SAlex Sierra &adev->irq.self_irq); 559ab518012SAlex Sierra 560ab518012SAlex Sierra if (r) 561ab518012SAlex Sierra return r; 562ab518012SAlex Sierra 563edc61147SHawking Zhang /* use gpu virtual address for ih ring 564edc61147SHawking Zhang * until ih_checken is programmed to allow 565edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 566bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 567bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 568bf13cb1fSHuang Rui use_bus_addr = false; 569bf13cb1fSHuang Rui else 570bf13cb1fSHuang Rui use_bus_addr = true; 571edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 572edc61147SHawking Zhang if (r) 573edc61147SHawking Zhang return r; 574edc61147SHawking Zhang 575edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 576edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 577edc61147SHawking Zhang 578abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 579abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 580abb6fccbSAlex Sierra 581a362976bSHawking Zhang /* initialize ih control registers offset */ 582a362976bSHawking Zhang navi10_ih_init_register_offset(adev); 583a362976bSHawking Zhang 584d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 585d4581f7dSChristian König if (r) 586d4581f7dSChristian König return r; 587d4581f7dSChristian König 588edc61147SHawking Zhang r = amdgpu_irq_init(adev); 589edc61147SHawking Zhang 590edc61147SHawking Zhang return r; 591edc61147SHawking Zhang } 592edc61147SHawking Zhang 593edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 594edc61147SHawking Zhang { 595edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596edc61147SHawking Zhang 59772c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev); 598edc61147SHawking Zhang 599edc61147SHawking Zhang return 0; 600edc61147SHawking Zhang } 601edc61147SHawking Zhang 602edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 603edc61147SHawking Zhang { 604edc61147SHawking Zhang int r; 605edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606edc61147SHawking Zhang 607edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 608edc61147SHawking Zhang if (r) 609edc61147SHawking Zhang return r; 610edc61147SHawking Zhang 611edc61147SHawking Zhang return 0; 612edc61147SHawking Zhang } 613edc61147SHawking Zhang 614edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 615edc61147SHawking Zhang { 616edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 617edc61147SHawking Zhang 618edc61147SHawking Zhang navi10_ih_irq_disable(adev); 619edc61147SHawking Zhang 620edc61147SHawking Zhang return 0; 621edc61147SHawking Zhang } 622edc61147SHawking Zhang 623edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 624edc61147SHawking Zhang { 625edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626edc61147SHawking Zhang 627edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 628edc61147SHawking Zhang } 629edc61147SHawking Zhang 630edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 631edc61147SHawking Zhang { 632edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633edc61147SHawking Zhang 634edc61147SHawking Zhang return navi10_ih_hw_init(adev); 635edc61147SHawking Zhang } 636edc61147SHawking Zhang 637edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 638edc61147SHawking Zhang { 639edc61147SHawking Zhang /* todo */ 640edc61147SHawking Zhang return true; 641edc61147SHawking Zhang } 642edc61147SHawking Zhang 643edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 644edc61147SHawking Zhang { 645edc61147SHawking Zhang /* todo */ 646edc61147SHawking Zhang return -ETIMEDOUT; 647edc61147SHawking Zhang } 648edc61147SHawking Zhang 649edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 650edc61147SHawking Zhang { 651edc61147SHawking Zhang /* todo */ 652edc61147SHawking Zhang return 0; 653edc61147SHawking Zhang } 654edc61147SHawking Zhang 655edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 656edc61147SHawking Zhang bool enable) 657edc61147SHawking Zhang { 658edc61147SHawking Zhang uint32_t data, def, field_val; 659edc61147SHawking Zhang 660edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 661edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 662edc61147SHawking Zhang field_val = enable ? 0 : 1; 663edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 664edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 665edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 666edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 667edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 668edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 669edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 670edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 671edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 672edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 673edc61147SHawking Zhang if (def != data) 674edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 675edc61147SHawking Zhang } 676edc61147SHawking Zhang 677edc61147SHawking Zhang return; 678edc61147SHawking Zhang } 679edc61147SHawking Zhang 680edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 681edc61147SHawking Zhang enum amd_clockgating_state state) 682edc61147SHawking Zhang { 683edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 684edc61147SHawking Zhang 685edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 686a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 687edc61147SHawking Zhang return 0; 688edc61147SHawking Zhang } 689edc61147SHawking Zhang 690edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 691edc61147SHawking Zhang enum amd_powergating_state state) 692edc61147SHawking Zhang { 693edc61147SHawking Zhang return 0; 694edc61147SHawking Zhang } 695edc61147SHawking Zhang 696edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 697edc61147SHawking Zhang { 698edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 699edc61147SHawking Zhang 700edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 701edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 702edc61147SHawking Zhang 703edc61147SHawking Zhang return; 704edc61147SHawking Zhang } 705edc61147SHawking Zhang 706edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 707edc61147SHawking Zhang .name = "navi10_ih", 708edc61147SHawking Zhang .early_init = navi10_ih_early_init, 709edc61147SHawking Zhang .late_init = NULL, 710edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 711edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 712edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 713edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 714edc61147SHawking Zhang .suspend = navi10_ih_suspend, 715edc61147SHawking Zhang .resume = navi10_ih_resume, 716edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 717edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 718edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 719edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 720edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 721edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 722edc61147SHawking Zhang }; 723edc61147SHawking Zhang 724edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 725edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 72640838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 727edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 728edc61147SHawking Zhang }; 729edc61147SHawking Zhang 730edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 731edc61147SHawking Zhang { 732edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 733edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 734edc61147SHawking Zhang } 735edc61147SHawking Zhang 736edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 737edc61147SHawking Zhang { 738edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 739edc61147SHawking Zhang .major = 5, 740edc61147SHawking Zhang .minor = 0, 741edc61147SHawking Zhang .rev = 0, 742edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 743edc61147SHawking Zhang }; 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