1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings 445212d163SHawking Zhang * 455212d163SHawking Zhang * @adev: amdgpu_device pointer 465212d163SHawking Zhang * 475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10). 485212d163SHawking Zhang */ 495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 505212d163SHawking Zhang { 515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs; 525212d163SHawking Zhang 535212d163SHawking Zhang if (adev->irq.ih.ring_size) { 545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 645212d163SHawking Zhang } 655212d163SHawking Zhang 665212d163SHawking Zhang if (adev->irq.ih1.ring_size) { 675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 755212d163SHawking Zhang } 765212d163SHawking Zhang 775212d163SHawking Zhang if (adev->irq.ih2.ring_size) { 785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 865212d163SHawking Zhang } 875212d163SHawking Zhang } 885212d163SHawking Zhang 895212d163SHawking Zhang /** 905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 915ea6f9c2SChengming Gui * 925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 965ea6f9c2SChengming Gui * 975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 985ea6f9c2SChengming Gui * real_threshold = 2^threshold 995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 1015ea6f9c2SChengming Gui * 1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 1035ea6f9c2SChengming Gui */ 1045ea6f9c2SChengming Gui static void 1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 1075ea6f9c2SChengming Gui { 1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 1095ea6f9c2SChengming Gui 1105ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 1115ea6f9c2SChengming Gui return; 1125ea6f9c2SChengming Gui 1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 1155ea6f9c2SChengming Gui 1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1225ea6f9c2SChengming Gui 1235ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1245ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 1255ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 1265ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1285ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 1295ea6f9c2SChengming Gui } 1305ea6f9c2SChengming Gui 1315ea6f9c2SChengming Gui /** 132edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 133edc61147SHawking Zhang * 134edc61147SHawking Zhang * @adev: amdgpu_device pointer 135edc61147SHawking Zhang * 136edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 137edc61147SHawking Zhang */ 138edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 139edc61147SHawking Zhang { 140edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 141edc61147SHawking Zhang 142edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 143edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 144193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1450ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 1460ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1470ab176e6SAlex Sierra return; 1480ab176e6SAlex Sierra } 1490ab176e6SAlex Sierra } else { 150edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1510ab176e6SAlex Sierra } 1520ab176e6SAlex Sierra 153edc61147SHawking Zhang adev->irq.ih.enabled = true; 154ab518012SAlex Sierra 155ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 156ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 157ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 158ab518012SAlex Sierra RB_ENABLE, 1); 159193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1600ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1610ab176e6SAlex Sierra ih_rb_cntl)) { 1620ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1630ab176e6SAlex Sierra return; 1640ab176e6SAlex Sierra } 1650ab176e6SAlex Sierra } else { 166ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1670ab176e6SAlex Sierra } 168ab518012SAlex Sierra adev->irq.ih1.enabled = true; 169ab518012SAlex Sierra } 170ab518012SAlex Sierra 171ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 172ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 173ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 174ab518012SAlex Sierra RB_ENABLE, 1); 175193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1760ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1770ab176e6SAlex Sierra ih_rb_cntl)) { 1780ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1790ab176e6SAlex Sierra return; 1800ab176e6SAlex Sierra } 1810ab176e6SAlex Sierra } else { 182ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1830ab176e6SAlex Sierra } 184ab518012SAlex Sierra adev->irq.ih2.enabled = true; 185ab518012SAlex Sierra } 186d4581f7dSChristian König 187d4581f7dSChristian König if (adev->irq.ih_soft.ring_size) 188d4581f7dSChristian König adev->irq.ih_soft.enabled = true; 189edc61147SHawking Zhang } 190edc61147SHawking Zhang 191edc61147SHawking Zhang /** 192edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 193edc61147SHawking Zhang * 194edc61147SHawking Zhang * @adev: amdgpu_device pointer 195edc61147SHawking Zhang * 196edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 197edc61147SHawking Zhang */ 198edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 199edc61147SHawking Zhang { 200edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 201edc61147SHawking Zhang 202edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 203edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 204193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 2050ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 2060ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 2070ab176e6SAlex Sierra return; 2080ab176e6SAlex Sierra } 2090ab176e6SAlex Sierra } else { 210edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 2110ab176e6SAlex Sierra } 2120ab176e6SAlex Sierra 213edc61147SHawking Zhang /* set rptr, wptr to 0 */ 214edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 215edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 216edc61147SHawking Zhang adev->irq.ih.enabled = false; 217edc61147SHawking Zhang adev->irq.ih.rptr = 0; 218ab518012SAlex Sierra 219ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 220ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 221ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 222ab518012SAlex Sierra RB_ENABLE, 0); 223193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 2240ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 2250ab176e6SAlex Sierra ih_rb_cntl)) { 2260ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 2270ab176e6SAlex Sierra return; 2280ab176e6SAlex Sierra } 2290ab176e6SAlex Sierra } else { 230ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 2310ab176e6SAlex Sierra } 232ab518012SAlex Sierra /* set rptr, wptr to 0 */ 233ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 234ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 235ab518012SAlex Sierra adev->irq.ih1.enabled = false; 236ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 237ab518012SAlex Sierra } 238ab518012SAlex Sierra 239ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 240ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 241ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 242ab518012SAlex Sierra RB_ENABLE, 0); 243193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 2440ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 2450ab176e6SAlex Sierra ih_rb_cntl)) { 2460ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 2470ab176e6SAlex Sierra return; 2480ab176e6SAlex Sierra } 2490ab176e6SAlex Sierra } else { 250ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 2510ab176e6SAlex Sierra } 252ab518012SAlex Sierra /* set rptr, wptr to 0 */ 253ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 254ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 255ab518012SAlex Sierra adev->irq.ih2.enabled = false; 256ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 257ab518012SAlex Sierra } 258ab518012SAlex Sierra 259edc61147SHawking Zhang } 260edc61147SHawking Zhang 261*1ce6940eSHawking Zhang /** 262*1ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 263*1ce6940eSHawking Zhang * 264*1ce6940eSHawking Zhang * @adev: amdgpu_device pointer 265*1ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet 266*1ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 267*1ce6940eSHawking Zhang * 268*1ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10) 269*1ce6940eSHawking Zhang */ 270*1ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 271*1ce6940eSHawking Zhang struct amdgpu_ih_ring *ih, 272*1ce6940eSHawking Zhang bool enable) 273*1ce6940eSHawking Zhang { 274*1ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs; 275*1ce6940eSHawking Zhang uint32_t tmp; 276*1ce6940eSHawking Zhang 277*1ce6940eSHawking Zhang ih_regs = &ih->ih_regs; 278*1ce6940eSHawking Zhang 279*1ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 280*1ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 281*1ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */ 282*1ce6940eSHawking Zhang if (ih == &adev->irq.ih) 283*1ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 284*1ce6940eSHawking Zhang if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 285*1ce6940eSHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 286*1ce6940eSHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 287*1ce6940eSHawking Zhang return -ETIMEDOUT; 288*1ce6940eSHawking Zhang } 289*1ce6940eSHawking Zhang } else { 290*1ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 291*1ce6940eSHawking Zhang } 292*1ce6940eSHawking Zhang 293*1ce6940eSHawking Zhang if (enable) { 294*1ce6940eSHawking Zhang ih->enabled = true; 295*1ce6940eSHawking Zhang } else { 296*1ce6940eSHawking Zhang /* set rptr, wptr to 0 */ 297*1ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 298*1ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 299*1ce6940eSHawking Zhang ih->enabled = false; 300*1ce6940eSHawking Zhang ih->rptr = 0; 301*1ce6940eSHawking Zhang } 302*1ce6940eSHawking Zhang 303*1ce6940eSHawking Zhang return 0; 304*1ce6940eSHawking Zhang } 305*1ce6940eSHawking Zhang 306edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 307edc61147SHawking Zhang { 308edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 309edc61147SHawking Zhang 310edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 311edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 312edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 313edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 314edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 315edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 316edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 317edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 318edc61147SHawking Zhang * value is written to memory 319edc61147SHawking Zhang */ 320edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 321edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 322edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 323edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 324edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 325edc61147SHawking Zhang 326edc61147SHawking Zhang return ih_rb_cntl; 327edc61147SHawking Zhang } 328edc61147SHawking Zhang 329ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 330ab518012SAlex Sierra { 331ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 332ab518012SAlex Sierra 333ab518012SAlex Sierra if (ih->use_doorbell) { 334ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 335ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 336ab518012SAlex Sierra ih->doorbell_index); 337ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 338ab518012SAlex Sierra IH_DOORBELL_RPTR, 339ab518012SAlex Sierra ENABLE, 1); 340ab518012SAlex Sierra } else { 341ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 342ab518012SAlex Sierra IH_DOORBELL_RPTR, 343ab518012SAlex Sierra ENABLE, 0); 344ab518012SAlex Sierra } 345ab518012SAlex Sierra return ih_doorbell_rtpr; 346ab518012SAlex Sierra } 347ab518012SAlex Sierra 3481514cb7dSHawking Zhang /** 3491514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer 3501514cb7dSHawking Zhang * 3511514cb7dSHawking Zhang * @adev: amdgpu_device pointer 3521514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer 3531514cb7dSHawking Zhang * 3541514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10) 3551514cb7dSHawking Zhang */ 3561514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev, 3571514cb7dSHawking Zhang struct amdgpu_ih_ring *ih) 3581514cb7dSHawking Zhang { 3591514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs; 3601514cb7dSHawking Zhang uint32_t tmp; 3611514cb7dSHawking Zhang 3621514cb7dSHawking Zhang ih_regs = &ih->ih_regs; 3631514cb7dSHawking Zhang 3641514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 3651514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 3661514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 3671514cb7dSHawking Zhang 3681514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 3691514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp); 3701514cb7dSHawking Zhang if (ih == &adev->irq.ih) 3711514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 3721514cb7dSHawking Zhang if (ih == &adev->irq.ih1) { 3731514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 3741514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 3751514cb7dSHawking Zhang } 3761514cb7dSHawking Zhang if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3771514cb7dSHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 3781514cb7dSHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 3791514cb7dSHawking Zhang return -ETIMEDOUT; 3801514cb7dSHawking Zhang } 3811514cb7dSHawking Zhang } else { 3821514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 3831514cb7dSHawking Zhang } 3841514cb7dSHawking Zhang 3851514cb7dSHawking Zhang if (ih == &adev->irq.ih) { 3861514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 3871514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 3881514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 3891514cb7dSHawking Zhang } 3901514cb7dSHawking Zhang 3911514cb7dSHawking Zhang /* set rptr, wptr to 0 */ 3921514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 3931514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 3941514cb7dSHawking Zhang 3951514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 3961514cb7dSHawking Zhang 3971514cb7dSHawking Zhang return 0; 3981514cb7dSHawking Zhang } 3991514cb7dSHawking Zhang 4009e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 4019e94ff33SAlex Sierra { 4029e94ff33SAlex Sierra uint32_t tmp; 4039e94ff33SAlex Sierra 4049e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 4059e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 4069e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 4079e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 4089e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 4099e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 4109e94ff33SAlex Sierra 4119e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 4129e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 4139e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 4149e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 4159e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 4169e94ff33SAlex Sierra } 4179e94ff33SAlex Sierra 418edc61147SHawking Zhang /** 419edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 420edc61147SHawking Zhang * 421edc61147SHawking Zhang * @adev: amdgpu_device pointer 422edc61147SHawking Zhang * 423edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 424edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 425edc61147SHawking Zhang * ring buffer and enable it (NAVI). 426edc61147SHawking Zhang * Called at device load and reume. 427edc61147SHawking Zhang * Returns 0 for success, errors for failure. 428edc61147SHawking Zhang */ 429edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 430edc61147SHawking Zhang { 431edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 432ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 433edc61147SHawking Zhang u32 tmp; 434edc61147SHawking Zhang 435edc61147SHawking Zhang /* disable irqs */ 436edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 437edc61147SHawking Zhang 438bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 439edc61147SHawking Zhang 440edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 441edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 442edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 443edc61147SHawking Zhang 444edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 445edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 446edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 447edc61147SHawking Zhang !!adev->irq.msi_enabled); 448193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 4490ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 4500ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 4510ab176e6SAlex Sierra return -ETIMEDOUT; 4520ab176e6SAlex Sierra } 4530ab176e6SAlex Sierra } else { 4540ab176e6SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 4550ab176e6SAlex Sierra } 456abb6fccbSAlex Sierra if (adev->irq.ih1.ring_size) 4579e94ff33SAlex Sierra navi10_ih_reroute_ih(adev); 458edc61147SHawking Zhang 459edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 460edc61147SHawking Zhang if (ih->use_bus_addr) { 461757b3af8SLikun Gao switch (adev->asic_type) { 462757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 463026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 464bd4f2811SHuang Rui case CHIP_VANGOGH: 465771cc67eSTao Zhou case CHIP_DIMGREY_CAVEFISH: 466757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 467757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 468757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 469757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 470757b3af8SLikun Gao break; 471757b3af8SLikun Gao default: 472edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 473edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 474edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 475edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 476757b3af8SLikun Gao break; 477757b3af8SLikun Gao } 478edc61147SHawking Zhang } 479edc61147SHawking Zhang } 480edc61147SHawking Zhang 481edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 482edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 483edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 484edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 485edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 486edc61147SHawking Zhang 487edc61147SHawking Zhang /* set rptr, wptr to 0 */ 488edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 489edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 490edc61147SHawking Zhang 491ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 492ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 493edc61147SHawking Zhang 494bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 495edc61147SHawking Zhang ih->doorbell_index); 496edc61147SHawking Zhang 497ab518012SAlex Sierra ih = &adev->irq.ih1; 498ab518012SAlex Sierra if (ih->ring_size) { 499ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 500ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 501ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 502ab518012SAlex Sierra 503ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 504ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 505ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 506ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 507ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 508ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 509193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 5100ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 5110ab176e6SAlex Sierra ih_rb_cntl)) { 5120ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 5130ab176e6SAlex Sierra return -ETIMEDOUT; 5140ab176e6SAlex Sierra } 5150ab176e6SAlex Sierra } else { 516ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 5170ab176e6SAlex Sierra } 518ab518012SAlex Sierra /* set rptr, wptr to 0 */ 519ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 520ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 521ab518012SAlex Sierra 522ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 523ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 524ab518012SAlex Sierra } 525ab518012SAlex Sierra 526ab518012SAlex Sierra ih = &adev->irq.ih2; 527ab518012SAlex Sierra if (ih->ring_size) { 528ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 529ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 530ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 531ab518012SAlex Sierra 532ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 533ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 534ab518012SAlex Sierra 535193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 5360ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 5370ab176e6SAlex Sierra ih_rb_cntl)) { 5380ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 5390ab176e6SAlex Sierra return -ETIMEDOUT; 5400ab176e6SAlex Sierra } 5410ab176e6SAlex Sierra } else { 542ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 5430ab176e6SAlex Sierra } 544ab518012SAlex Sierra /* set rptr, wptr to 0 */ 545ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 546ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 547ab518012SAlex Sierra 548ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 549ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 550ab518012SAlex Sierra } 551ab518012SAlex Sierra 552ab518012SAlex Sierra 553edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 554edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 555edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 556edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 557edc61147SHawking Zhang 558edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 559edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 560edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 561edc61147SHawking Zhang 562edc61147SHawking Zhang pci_set_master(adev->pdev); 563edc61147SHawking Zhang 564edc61147SHawking Zhang /* enable interrupts */ 565edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 5665ea6f9c2SChengming Gui /* enable wptr force update for self int */ 5675ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 568edc61147SHawking Zhang 5697eca4006SMa Feng return 0; 570edc61147SHawking Zhang } 571edc61147SHawking Zhang 572edc61147SHawking Zhang /** 573edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 574edc61147SHawking Zhang * 575edc61147SHawking Zhang * @adev: amdgpu_device pointer 576edc61147SHawking Zhang * 577edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 578edc61147SHawking Zhang */ 579edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 580edc61147SHawking Zhang { 5815ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 582edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 583edc61147SHawking Zhang 584edc61147SHawking Zhang /* Wait and acknowledge irq */ 585edc61147SHawking Zhang mdelay(1); 586edc61147SHawking Zhang } 587edc61147SHawking Zhang 588edc61147SHawking Zhang /** 589edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 590edc61147SHawking Zhang * 591edc61147SHawking Zhang * @adev: amdgpu_device pointer 592c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 593edc61147SHawking Zhang * 594edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 595edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 596edc61147SHawking Zhang * ring buffer overflow and deal with it. 597edc61147SHawking Zhang * Returns the value of the wptr. 598edc61147SHawking Zhang */ 599edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 600edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 601edc61147SHawking Zhang { 602edc61147SHawking Zhang u32 wptr, reg, tmp; 603edc61147SHawking Zhang 604edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 605edc61147SHawking Zhang 606edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 607edc61147SHawking Zhang goto out; 608edc61147SHawking Zhang 609ab518012SAlex Sierra if (ih == &adev->irq.ih) 610edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 611ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 612ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 613ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 614ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 615ab518012SAlex Sierra else 616ab518012SAlex Sierra BUG(); 617ab518012SAlex Sierra 618edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 619edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 620edc61147SHawking Zhang goto out; 621edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 622edc61147SHawking Zhang 623edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 624edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 625edc61147SHawking Zhang * this should allow us to catch up. 626edc61147SHawking Zhang */ 627edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 628edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 629edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 630edc61147SHawking Zhang wptr, ih->rptr, tmp); 631edc61147SHawking Zhang ih->rptr = tmp; 632edc61147SHawking Zhang 633ab518012SAlex Sierra if (ih == &adev->irq.ih) 634edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 635ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 636ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 637ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 638ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 639ab518012SAlex Sierra else 640ab518012SAlex Sierra BUG(); 641ab518012SAlex Sierra 642edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 643edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 644edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 645edc61147SHawking Zhang out: 646edc61147SHawking Zhang return (wptr & ih->ptr_mask); 647edc61147SHawking Zhang } 648edc61147SHawking Zhang 649edc61147SHawking Zhang /** 650edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 651edc61147SHawking Zhang * 652edc61147SHawking Zhang * @adev: amdgpu_device pointer 653c56fb081SLee Jones * @ih: IH ring buffer to decode 654c56fb081SLee Jones * @entry: IV entry to place decoded information into 655edc61147SHawking Zhang * 656edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 657edc61147SHawking Zhang * position and also advance the position. 658edc61147SHawking Zhang */ 659edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 660edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 661edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 662edc61147SHawking Zhang { 663edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 664edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 665edc61147SHawking Zhang uint32_t dw[8]; 666edc61147SHawking Zhang 667edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 668edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 669edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 670edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 671edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 672edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 673edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 674edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 675edc61147SHawking Zhang 676edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 677edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 678edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 679edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 680edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 681edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 682edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 683edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 684edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 685edc61147SHawking Zhang entry->src_data[0] = dw[4]; 686edc61147SHawking Zhang entry->src_data[1] = dw[5]; 687edc61147SHawking Zhang entry->src_data[2] = dw[6]; 688edc61147SHawking Zhang entry->src_data[3] = dw[7]; 689edc61147SHawking Zhang 690edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 691edc61147SHawking Zhang ih->rptr += 32; 692edc61147SHawking Zhang } 693edc61147SHawking Zhang 694edc61147SHawking Zhang /** 695022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 696022b6518SSamir Dhume * 697022b6518SSamir Dhume * @adev: amdgpu_device pointer 698c56fb081SLee Jones * @ih: IH ring to match 699022b6518SSamir Dhume * 700022b6518SSamir Dhume */ 701022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 702022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 703022b6518SSamir Dhume { 704022b6518SSamir Dhume uint32_t reg_rptr = 0; 705022b6518SSamir Dhume uint32_t v = 0; 706022b6518SSamir Dhume uint32_t i = 0; 707022b6518SSamir Dhume 708022b6518SSamir Dhume if (ih == &adev->irq.ih) 709022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 710022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 711022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 712022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 713022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 714022b6518SSamir Dhume else 715022b6518SSamir Dhume return; 716022b6518SSamir Dhume 717022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 718022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 719022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 720022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 721022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 722022b6518SSamir Dhume else 723022b6518SSamir Dhume break; 724022b6518SSamir Dhume } 725022b6518SSamir Dhume } 726022b6518SSamir Dhume 727022b6518SSamir Dhume /** 728edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 729edc61147SHawking Zhang * 730edc61147SHawking Zhang * @adev: amdgpu_device pointer 731edc61147SHawking Zhang * 732c56fb081SLee Jones * @ih: IH ring buffer to set rptr 733edc61147SHawking Zhang * Set the IH ring buffer rptr. 734edc61147SHawking Zhang */ 735edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 736edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 737edc61147SHawking Zhang { 738edc61147SHawking Zhang if (ih->use_doorbell) { 739edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 740edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 741edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 742022b6518SSamir Dhume 743022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 744022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 745ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 746edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 747ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 748ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 749ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 750ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 751ab518012SAlex Sierra } 752ab518012SAlex Sierra } 753ab518012SAlex Sierra 754ab518012SAlex Sierra /** 755ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 756ab518012SAlex Sierra * 757ab518012SAlex Sierra * @adev: amdgpu_device pointer 758ab518012SAlex Sierra * @source: irq source 759ab518012SAlex Sierra * @entry: IV with WPTR update 760ab518012SAlex Sierra * 761ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 762ab518012SAlex Sierra */ 763ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 764ab518012SAlex Sierra struct amdgpu_irq_src *source, 765ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 766ab518012SAlex Sierra { 767ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 768ab518012SAlex Sierra 769ab518012SAlex Sierra switch (entry->ring_id) { 770ab518012SAlex Sierra case 1: 771ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 772ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 773ab518012SAlex Sierra break; 774ab518012SAlex Sierra case 2: 775ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 776ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 777ab518012SAlex Sierra break; 778ab518012SAlex Sierra default: break; 779ab518012SAlex Sierra } 780ab518012SAlex Sierra return 0; 781ab518012SAlex Sierra } 782ab518012SAlex Sierra 783ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 784ab518012SAlex Sierra .process = navi10_ih_self_irq, 785ab518012SAlex Sierra }; 786ab518012SAlex Sierra 787ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 788ab518012SAlex Sierra { 789ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 790ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 791edc61147SHawking Zhang } 792edc61147SHawking Zhang 793edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 794edc61147SHawking Zhang { 795edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 796edc61147SHawking Zhang 797edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 798ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 799edc61147SHawking Zhang return 0; 800edc61147SHawking Zhang } 801edc61147SHawking Zhang 802edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 803edc61147SHawking Zhang { 804edc61147SHawking Zhang int r; 805edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806edc61147SHawking Zhang bool use_bus_addr; 807edc61147SHawking Zhang 808ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 809ab518012SAlex Sierra &adev->irq.self_irq); 810ab518012SAlex Sierra 811ab518012SAlex Sierra if (r) 812ab518012SAlex Sierra return r; 813ab518012SAlex Sierra 814edc61147SHawking Zhang /* use gpu virtual address for ih ring 815edc61147SHawking Zhang * until ih_checken is programmed to allow 816edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 817bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 818bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 819bf13cb1fSHuang Rui use_bus_addr = false; 820bf13cb1fSHuang Rui else 821bf13cb1fSHuang Rui use_bus_addr = true; 822edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 823edc61147SHawking Zhang if (r) 824edc61147SHawking Zhang return r; 825edc61147SHawking Zhang 826edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 827edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 828edc61147SHawking Zhang 829abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 830abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 831abb6fccbSAlex Sierra 832abb6fccbSAlex Sierra if (adev->asic_type < CHIP_NAVI10) { 833ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 834ab518012SAlex Sierra if (r) 835ab518012SAlex Sierra return r; 836ab518012SAlex Sierra 837ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 838abb6fccbSAlex Sierra adev->irq.ih1.doorbell_index = 839abb6fccbSAlex Sierra (adev->doorbell_index.ih + 1) << 1; 840ab518012SAlex Sierra 841ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 842ab518012SAlex Sierra if (r) 843ab518012SAlex Sierra return r; 844ab518012SAlex Sierra 845ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 846abb6fccbSAlex Sierra adev->irq.ih2.doorbell_index = 847abb6fccbSAlex Sierra (adev->doorbell_index.ih + 2) << 1; 848abb6fccbSAlex Sierra } 849ab518012SAlex Sierra 850d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 851d4581f7dSChristian König if (r) 852d4581f7dSChristian König return r; 853d4581f7dSChristian König 854edc61147SHawking Zhang r = amdgpu_irq_init(adev); 855edc61147SHawking Zhang 856edc61147SHawking Zhang return r; 857edc61147SHawking Zhang } 858edc61147SHawking Zhang 859edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 860edc61147SHawking Zhang { 861edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 862edc61147SHawking Zhang 863edc61147SHawking Zhang amdgpu_irq_fini(adev); 864ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 865ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 866edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 867edc61147SHawking Zhang 868edc61147SHawking Zhang return 0; 869edc61147SHawking Zhang } 870edc61147SHawking Zhang 871edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 872edc61147SHawking Zhang { 873edc61147SHawking Zhang int r; 874edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875edc61147SHawking Zhang 876edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 877edc61147SHawking Zhang if (r) 878edc61147SHawking Zhang return r; 879edc61147SHawking Zhang 880edc61147SHawking Zhang return 0; 881edc61147SHawking Zhang } 882edc61147SHawking Zhang 883edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 884edc61147SHawking Zhang { 885edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 886edc61147SHawking Zhang 887edc61147SHawking Zhang navi10_ih_irq_disable(adev); 888edc61147SHawking Zhang 889edc61147SHawking Zhang return 0; 890edc61147SHawking Zhang } 891edc61147SHawking Zhang 892edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 893edc61147SHawking Zhang { 894edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895edc61147SHawking Zhang 896edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 897edc61147SHawking Zhang } 898edc61147SHawking Zhang 899edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 900edc61147SHawking Zhang { 901edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 902edc61147SHawking Zhang 903edc61147SHawking Zhang return navi10_ih_hw_init(adev); 904edc61147SHawking Zhang } 905edc61147SHawking Zhang 906edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 907edc61147SHawking Zhang { 908edc61147SHawking Zhang /* todo */ 909edc61147SHawking Zhang return true; 910edc61147SHawking Zhang } 911edc61147SHawking Zhang 912edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 913edc61147SHawking Zhang { 914edc61147SHawking Zhang /* todo */ 915edc61147SHawking Zhang return -ETIMEDOUT; 916edc61147SHawking Zhang } 917edc61147SHawking Zhang 918edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 919edc61147SHawking Zhang { 920edc61147SHawking Zhang /* todo */ 921edc61147SHawking Zhang return 0; 922edc61147SHawking Zhang } 923edc61147SHawking Zhang 924edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 925edc61147SHawking Zhang bool enable) 926edc61147SHawking Zhang { 927edc61147SHawking Zhang uint32_t data, def, field_val; 928edc61147SHawking Zhang 929edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 930edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 931edc61147SHawking Zhang field_val = enable ? 0 : 1; 932edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 933edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 934edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 935edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 936edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 937edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 938edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 939edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 940edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 941edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 942edc61147SHawking Zhang if (def != data) 943edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 944edc61147SHawking Zhang } 945edc61147SHawking Zhang 946edc61147SHawking Zhang return; 947edc61147SHawking Zhang } 948edc61147SHawking Zhang 949edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 950edc61147SHawking Zhang enum amd_clockgating_state state) 951edc61147SHawking Zhang { 952edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 953edc61147SHawking Zhang 954edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 955a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 956edc61147SHawking Zhang return 0; 957edc61147SHawking Zhang } 958edc61147SHawking Zhang 959edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 960edc61147SHawking Zhang enum amd_powergating_state state) 961edc61147SHawking Zhang { 962edc61147SHawking Zhang return 0; 963edc61147SHawking Zhang } 964edc61147SHawking Zhang 965edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 966edc61147SHawking Zhang { 967edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 968edc61147SHawking Zhang 969edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 970edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 971edc61147SHawking Zhang 972edc61147SHawking Zhang return; 973edc61147SHawking Zhang } 974edc61147SHawking Zhang 975edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 976edc61147SHawking Zhang .name = "navi10_ih", 977edc61147SHawking Zhang .early_init = navi10_ih_early_init, 978edc61147SHawking Zhang .late_init = NULL, 979edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 980edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 981edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 982edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 983edc61147SHawking Zhang .suspend = navi10_ih_suspend, 984edc61147SHawking Zhang .resume = navi10_ih_resume, 985edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 986edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 987edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 988edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 989edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 990edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 991edc61147SHawking Zhang }; 992edc61147SHawking Zhang 993edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 994edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 995edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 996edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 997edc61147SHawking Zhang }; 998edc61147SHawking Zhang 999edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 1000edc61147SHawking Zhang { 1001edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 1002edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 1003edc61147SHawking Zhang } 1004edc61147SHawking Zhang 1005edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 1006edc61147SHawking Zhang { 1007edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 1008edc61147SHawking Zhang .major = 5, 1009edc61147SHawking Zhang .minor = 0, 1010edc61147SHawking Zhang .rev = 0, 1011edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 1012edc61147SHawking Zhang }; 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