1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __MMSCH_V4_0_H__
25 #define __MMSCH_V4_0_H__
26 
27 #include "amdgpu_vcn.h"
28 
29 #define MMSCH_VERSION_MAJOR	4
30 #define MMSCH_VERSION_MINOR	0
31 #define MMSCH_VERSION	(MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
32 
33 #define RB_ENABLED (1 << 0)
34 #define RB4_ENABLED (1 << 1)
35 
36 #define MMSCH_VF_ENGINE_STATUS__PASS 0x1
37 
38 #define MMSCH_VF_MAILBOX_RESP__OK 0x1
39 #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
40 
41 #define MMSCH_VF_ENGINE_STATUS__PASS 0x1
42 
43 #define MMSCH_VF_MAILBOX_RESP__OK 0x1
44 #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
45 
46 enum mmsch_v4_0_command_type {
47 	MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
48 	MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
49 	MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
50 	MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
51 	MMSCH_COMMAND__END = 0xf
52 };
53 
54 struct mmsch_v4_0_table_info {
55 	uint32_t init_status;
56 	uint32_t table_offset;
57 	uint32_t table_size;
58 };
59 
60 struct mmsch_v4_0_init_header {
61 	uint32_t version;
62 	uint32_t total_size;
63 	struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
64 	struct mmsch_v4_0_table_info jpegdec;
65 };
66 
67 struct mmsch_v4_0_cmd_direct_reg_header {
68 	uint32_t reg_offset   : 28;
69 	uint32_t command_type : 4;
70 };
71 
72 struct mmsch_v4_0_cmd_indirect_reg_header {
73 	uint32_t reg_offset    : 20;
74 	uint32_t reg_idx_space : 8;
75 	uint32_t command_type  : 4;
76 };
77 
78 struct mmsch_v4_0_cmd_direct_write {
79 	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
80 	uint32_t reg_value;
81 };
82 
83 struct mmsch_v4_0_cmd_direct_read_modify_write {
84 	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
85 	uint32_t write_data;
86 	uint32_t mask_value;
87 };
88 
89 struct mmsch_v4_0_cmd_direct_polling {
90 	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
91 	uint32_t mask_value;
92 	uint32_t wait_value;
93 };
94 
95 struct mmsch_v4_0_cmd_end {
96 	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
97 };
98 
99 struct mmsch_v4_0_cmd_indirect_write {
100 	struct mmsch_v4_0_cmd_indirect_reg_header cmd_header;
101 	uint32_t reg_value;
102 };
103 
104 #define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
105 	size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \
106 	size_dw = size / 4; \
107 	direct_rd_mod_wt.cmd_header.reg_offset = reg; \
108 	direct_rd_mod_wt.mask_value = mask; \
109 	direct_rd_mod_wt.write_data = data; \
110 	memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
111 	table_loc += size_dw; \
112 	table_size += size_dw; \
113 }
114 
115 #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \
116 	size = sizeof(struct mmsch_v4_0_cmd_direct_write); \
117 	size_dw = size / 4; \
118 	direct_wt.cmd_header.reg_offset = reg; \
119 	direct_wt.reg_value = value; \
120 	memcpy((void *)table_loc, &direct_wt, size); \
121 	table_loc += size_dw; \
122 	table_size += size_dw; \
123 }
124 
125 #define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
126 	size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \
127 	size_dw = size / 4; \
128 	direct_poll.cmd_header.reg_offset = reg; \
129 	direct_poll.mask_value = mask; \
130 	direct_poll.wait_value = wait; \
131 	memcpy((void *)table_loc, &direct_poll, size); \
132 	table_loc += size_dw; \
133 	table_size += size_dw; \
134 }
135 
136 #define MMSCH_V4_0_INSERT_END() { \
137 	size = sizeof(struct mmsch_v4_0_cmd_end); \
138 	size_dw = size / 4; \
139 	memcpy((void *)table_loc, &end, size); \
140 	table_loc += size_dw; \
141 	table_size += size_dw; \
142 }
143 
144 #endif
145