1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MMSCH_V4_0_H__ 25 #define __MMSCH_V4_0_H__ 26 27 #include "amdgpu_vcn.h" 28 29 #define MMSCH_VERSION_MAJOR 4 30 #define MMSCH_VERSION_MINOR 0 31 #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR) 32 33 #define RB_ENABLED (1 << 0) 34 #define RB4_ENABLED (1 << 1) 35 #define MMSCH_DOORBELL_OFFSET 0x8 36 37 #define MMSCH_VF_ENGINE_STATUS__PASS 0x1 38 39 #define MMSCH_VF_MAILBOX_RESP__OK 0x1 40 #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2 41 42 enum mmsch_v4_0_command_type { 43 MMSCH_COMMAND__DIRECT_REG_WRITE = 0, 44 MMSCH_COMMAND__DIRECT_REG_POLLING = 2, 45 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3, 46 MMSCH_COMMAND__INDIRECT_REG_WRITE = 8, 47 MMSCH_COMMAND__END = 0xf 48 }; 49 50 struct mmsch_v4_0_table_info { 51 uint32_t init_status; 52 uint32_t table_offset; 53 uint32_t table_size; 54 }; 55 56 struct mmsch_v4_0_init_header { 57 uint32_t version; 58 uint32_t total_size; 59 struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES]; 60 struct mmsch_v4_0_table_info jpegdec; 61 }; 62 63 struct mmsch_v4_0_cmd_direct_reg_header { 64 uint32_t reg_offset : 28; 65 uint32_t command_type : 4; 66 }; 67 68 struct mmsch_v4_0_cmd_indirect_reg_header { 69 uint32_t reg_offset : 20; 70 uint32_t reg_idx_space : 8; 71 uint32_t command_type : 4; 72 }; 73 74 struct mmsch_v4_0_cmd_direct_write { 75 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 76 uint32_t reg_value; 77 }; 78 79 struct mmsch_v4_0_cmd_direct_read_modify_write { 80 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 81 uint32_t write_data; 82 uint32_t mask_value; 83 }; 84 85 struct mmsch_v4_0_cmd_direct_polling { 86 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 87 uint32_t mask_value; 88 uint32_t wait_value; 89 }; 90 91 struct mmsch_v4_0_cmd_end { 92 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 93 }; 94 95 struct mmsch_v4_0_cmd_indirect_write { 96 struct mmsch_v4_0_cmd_indirect_reg_header cmd_header; 97 uint32_t reg_value; 98 }; 99 100 #define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 101 size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \ 102 size_dw = size / 4; \ 103 direct_rd_mod_wt.cmd_header.reg_offset = reg; \ 104 direct_rd_mod_wt.mask_value = mask; \ 105 direct_rd_mod_wt.write_data = data; \ 106 memcpy((void *)table_loc, &direct_rd_mod_wt, size); \ 107 table_loc += size_dw; \ 108 table_size += size_dw; \ 109 } 110 111 #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ 112 size = sizeof(struct mmsch_v4_0_cmd_direct_write); \ 113 size_dw = size / 4; \ 114 direct_wt.cmd_header.reg_offset = reg; \ 115 direct_wt.reg_value = value; \ 116 memcpy((void *)table_loc, &direct_wt, size); \ 117 table_loc += size_dw; \ 118 table_size += size_dw; \ 119 } 120 121 #define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ 122 size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \ 123 size_dw = size / 4; \ 124 direct_poll.cmd_header.reg_offset = reg; \ 125 direct_poll.mask_value = mask; \ 126 direct_poll.wait_value = wait; \ 127 memcpy((void *)table_loc, &direct_poll, size); \ 128 table_loc += size_dw; \ 129 table_size += size_dw; \ 130 } 131 132 #define MMSCH_V4_0_INSERT_END() { \ 133 size = sizeof(struct mmsch_v4_0_cmd_end); \ 134 size_dw = size / 4; \ 135 memcpy((void *)table_loc, &end, size); \ 136 table_loc += size_dw; \ 137 table_size += size_dw; \ 138 } 139 140 #endif 141