1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "amdgpu.h"
24 #include "amdgpu_ras.h"
25 #include "mmhub_v9_4.h"
26 
27 #include "mmhub/mmhub_9_4_1_offset.h"
28 #include "mmhub/mmhub_9_4_1_sh_mask.h"
29 #include "mmhub/mmhub_9_4_1_default.h"
30 #include "athub/athub_1_0_offset.h"
31 #include "athub/athub_1_0_sh_mask.h"
32 #include "vega10_enum.h"
33 #include "soc15.h"
34 #include "soc15_common.h"
35 
36 #define MMHUB_NUM_INSTANCES			2
37 #define MMHUB_INSTANCE_REGISTER_OFFSET		0x3000
38 
39 static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
40 {
41 	/* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
42 	u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
43 	u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
44 
45 	base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
46 	base <<= 24;
47 
48 	top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
49 	top <<= 24;
50 
51 	adev->gmc.fb_start = base;
52 	adev->gmc.fb_end = top;
53 
54 	return base;
55 }
56 
57 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
58 				uint32_t vmid, uint64_t value)
59 {
60 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
61 
62 	WREG32_SOC15_OFFSET(MMHUB, 0,
63 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
64 			    hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
65 			    lower_32_bits(value));
66 
67 	WREG32_SOC15_OFFSET(MMHUB, 0,
68 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
69 			    hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
70 			    upper_32_bits(value));
71 
72 }
73 
74 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
75 					       int hubid)
76 {
77 	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
78 
79 	mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
80 
81 	WREG32_SOC15_OFFSET(MMHUB, 0,
82 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
83 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
84 			    (u32)(adev->gmc.gart_start >> 12));
85 	WREG32_SOC15_OFFSET(MMHUB, 0,
86 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
87 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
88 			    (u32)(adev->gmc.gart_start >> 44));
89 
90 	WREG32_SOC15_OFFSET(MMHUB, 0,
91 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
92 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
93 			    (u32)(adev->gmc.gart_end >> 12));
94 	WREG32_SOC15_OFFSET(MMHUB, 0,
95 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
96 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
97 			    (u32)(adev->gmc.gart_end >> 44));
98 }
99 
100 static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
101 				uint64_t page_table_base)
102 {
103 	int i;
104 
105 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
106 		mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
107 				page_table_base);
108 }
109 
110 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
111 					         int hubid)
112 {
113 	uint64_t value;
114 	uint32_t tmp;
115 
116 	/* Program the AGP BAR */
117 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
118 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
119 			    0);
120 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
121 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
122 			    adev->gmc.agp_end >> 24);
123 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
124 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
125 			    adev->gmc.agp_start >> 24);
126 
127 	if (!amdgpu_sriov_vf(adev)) {
128 		/* Program the system aperture low logical page number. */
129 		WREG32_SOC15_OFFSET(
130 			MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
131 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
132 			min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
133 		WREG32_SOC15_OFFSET(
134 			MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
135 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
136 			max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
137 
138 		/* Set default page address. */
139 		value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
140 		WREG32_SOC15_OFFSET(
141 			MMHUB, 0,
142 			mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
143 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
144 			(u32)(value >> 12));
145 		WREG32_SOC15_OFFSET(
146 			MMHUB, 0,
147 			mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
148 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
149 			(u32)(value >> 44));
150 
151 		/* Program "protection fault". */
152 		WREG32_SOC15_OFFSET(
153 			MMHUB, 0,
154 			mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
155 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
156 			(u32)(adev->dummy_page_addr >> 12));
157 		WREG32_SOC15_OFFSET(
158 			MMHUB, 0,
159 			mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
160 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
161 			(u32)((u64)adev->dummy_page_addr >> 44));
162 
163 		tmp = RREG32_SOC15_OFFSET(
164 			MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
165 			hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
166 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
167 				    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
168 		WREG32_SOC15_OFFSET(MMHUB, 0,
169 				    mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
170 				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
171 				    tmp);
172 	}
173 }
174 
175 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
176 {
177 	uint32_t tmp;
178 
179 	/* Setup TLB control */
180 	tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
181 			   mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
182 			   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
183 
184 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
185 			    ENABLE_L1_TLB, 1);
186 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
187 			    SYSTEM_ACCESS_MODE, 3);
188 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
189 			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
190 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
191 			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
192 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
193 			    MTYPE, MTYPE_UC);/* XXX for emulation. */
194 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
195 			    ATC_EN, 1);
196 
197 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
198 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
199 }
200 
201 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
202 {
203 	uint32_t tmp;
204 
205 	/* Setup L2 cache */
206 	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
207 				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
208 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
209 			    ENABLE_L2_CACHE, 1);
210 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
211 			    ENABLE_L2_FRAGMENT_PROCESSING, 1);
212 	/* XXX for emulation, Refer to closed source code.*/
213 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
214 			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
215 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
216 			    PDE_FAULT_CLASSIFICATION, 0);
217 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
218 			    CONTEXT1_IDENTITY_ACCESS_MODE, 1);
219 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
220 			    IDENTITY_MODE_FRAGMENT_SIZE, 0);
221 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
222 		     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
223 
224 	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
225 				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
226 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
227 			    INVALIDATE_ALL_L1_TLBS, 1);
228 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
229 			    INVALIDATE_L2_CACHE, 1);
230 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
231 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
232 
233 	tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
234 	if (adev->gmc.translate_further) {
235 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
236 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
237 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
238 	} else {
239 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
240 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
241 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
242 	}
243 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
244 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
245 
246 	tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
247 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
248 			    VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
249 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
250 			    VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
251 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
252 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
253 }
254 
255 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
256 					    int hubid)
257 {
258 	uint32_t tmp;
259 
260 	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
261 				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
262 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
263 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
264 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
265 			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
266 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
267 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
268 }
269 
270 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
271 						 int hubid)
272 {
273 	WREG32_SOC15_OFFSET(MMHUB, 0,
274 		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
275 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
276 	WREG32_SOC15_OFFSET(MMHUB, 0,
277 		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
278 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
279 
280 	WREG32_SOC15_OFFSET(MMHUB, 0,
281 		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
282 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
283 	WREG32_SOC15_OFFSET(MMHUB, 0,
284 		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
285 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
286 
287 	WREG32_SOC15_OFFSET(MMHUB, 0,
288 		    mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
289 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
290 	WREG32_SOC15_OFFSET(MMHUB, 0,
291 		    mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
292 		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
293 }
294 
295 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
296 {
297 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
298 	uint32_t tmp;
299 	int i;
300 
301 	for (i = 0; i <= 14; i++) {
302 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
303 				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
304 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
305 				    ENABLE_CONTEXT, 1);
306 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
307 				    PAGE_TABLE_DEPTH,
308 				    adev->vm_manager.num_level);
309 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
310 				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
311 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
312 				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
313 				    1);
314 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
315 				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
316 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
317 				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
318 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
319 				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
320 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
321 				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
322 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
323 				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
324 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
325 				    PAGE_TABLE_BLOCK_SIZE,
326 				    adev->vm_manager.block_size - 9);
327 		/* Send no-retry XNACK on fault to suppress VM fault storm. */
328 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
329 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
330 				    !adev->gmc.noretry);
331 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
332 				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
333 				    i * hub->ctx_distance, tmp);
334 		WREG32_SOC15_OFFSET(MMHUB, 0,
335 			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
336 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
337 			    i * hub->ctx_addr_distance, 0);
338 		WREG32_SOC15_OFFSET(MMHUB, 0,
339 			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
340 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
341 			    i * hub->ctx_addr_distance, 0);
342 		WREG32_SOC15_OFFSET(MMHUB, 0,
343 				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
344 				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
345 				i * hub->ctx_addr_distance,
346 				lower_32_bits(adev->vm_manager.max_pfn - 1));
347 		WREG32_SOC15_OFFSET(MMHUB, 0,
348 				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
349 				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
350 				i * hub->ctx_addr_distance,
351 				upper_32_bits(adev->vm_manager.max_pfn - 1));
352 	}
353 }
354 
355 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
356 					    int hubid)
357 {
358 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
359 	unsigned i;
360 
361 	for (i = 0; i < 18; ++i) {
362 		WREG32_SOC15_OFFSET(MMHUB, 0,
363 				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
364 				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
365 				i * hub->eng_addr_distance,
366 				0xffffffff);
367 		WREG32_SOC15_OFFSET(MMHUB, 0,
368 				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
369 				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
370 				i * hub->eng_addr_distance,
371 				0x1f);
372 	}
373 }
374 
375 static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
376 {
377 	int i;
378 
379 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
380 		/* GART Enable. */
381 		mmhub_v9_4_init_gart_aperture_regs(adev, i);
382 		mmhub_v9_4_init_system_aperture_regs(adev, i);
383 		mmhub_v9_4_init_tlb_regs(adev, i);
384 		if (!amdgpu_sriov_vf(adev))
385 			mmhub_v9_4_init_cache_regs(adev, i);
386 
387 		mmhub_v9_4_enable_system_domain(adev, i);
388 		if (!amdgpu_sriov_vf(adev))
389 			mmhub_v9_4_disable_identity_aperture(adev, i);
390 		mmhub_v9_4_setup_vmid_config(adev, i);
391 		mmhub_v9_4_program_invalidation(adev, i);
392 	}
393 
394 	return 0;
395 }
396 
397 static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
398 {
399 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
400 	u32 tmp;
401 	u32 i, j;
402 
403 	for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
404 		/* Disable all tables */
405 		for (i = 0; i < AMDGPU_NUM_VMID; i++)
406 			WREG32_SOC15_OFFSET(MMHUB, 0,
407 					    mmVML2VC0_VM_CONTEXT0_CNTL,
408 					    j * MMHUB_INSTANCE_REGISTER_OFFSET +
409 					    i * hub->ctx_distance, 0);
410 
411 		/* Setup TLB control */
412 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
413 				   mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
414 				   j * MMHUB_INSTANCE_REGISTER_OFFSET);
415 		tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
416 				    ENABLE_L1_TLB, 0);
417 		tmp = REG_SET_FIELD(tmp,
418 				    VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
419 				    ENABLE_ADVANCED_DRIVER_MODEL, 0);
420 		WREG32_SOC15_OFFSET(MMHUB, 0,
421 				    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
422 				    j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
423 
424 		/* Setup L2 cache */
425 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
426 					  j * MMHUB_INSTANCE_REGISTER_OFFSET);
427 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
428 				    ENABLE_L2_CACHE, 0);
429 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
430 				    j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
431 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
432 				    j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
433 	}
434 }
435 
436 /**
437  * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling
438  *
439  * @adev: amdgpu_device pointer
440  * @value: true redirects VM faults to the default page
441  */
442 static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
443 {
444 	u32 tmp;
445 	int i;
446 
447 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
448 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
449 					  mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
450 					  i * MMHUB_INSTANCE_REGISTER_OFFSET);
451 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
452 				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
453 				    value);
454 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
455 				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
456 				    value);
457 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
458 				    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
459 				    value);
460 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
461 				    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
462 				    value);
463 		tmp = REG_SET_FIELD(tmp,
464 			    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
465 			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
466 			    value);
467 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
468 				    NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
469 				    value);
470 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
471 				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
472 				    value);
473 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
474 				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
475 				    value);
476 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
477 				    READ_PROTECTION_FAULT_ENABLE_DEFAULT,
478 				    value);
479 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
480 				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
481 				    value);
482 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
483 				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
484 				    value);
485 		if (!value) {
486 			tmp = REG_SET_FIELD(tmp,
487 					    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
488 					    CRASH_ON_NO_RETRY_FAULT, 1);
489 			tmp = REG_SET_FIELD(tmp,
490 					    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
491 					    CRASH_ON_RETRY_FAULT, 1);
492 		}
493 
494 		WREG32_SOC15_OFFSET(MMHUB, 0,
495 				    mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
496 				    i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
497 	}
498 }
499 
500 static void mmhub_v9_4_init(struct amdgpu_device *adev)
501 {
502 	struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
503 		{&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
504 	int i;
505 
506 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
507 		hub[i]->ctx0_ptb_addr_lo32 =
508 			SOC15_REG_OFFSET(MMHUB, 0,
509 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
510 			    i * MMHUB_INSTANCE_REGISTER_OFFSET;
511 		hub[i]->ctx0_ptb_addr_hi32 =
512 			SOC15_REG_OFFSET(MMHUB, 0,
513 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
514 			    i * MMHUB_INSTANCE_REGISTER_OFFSET;
515 		hub[i]->vm_inv_eng0_sem =
516 			SOC15_REG_OFFSET(MMHUB, 0,
517 					 mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
518 					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
519 		hub[i]->vm_inv_eng0_req =
520 			SOC15_REG_OFFSET(MMHUB, 0,
521 					 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
522 					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
523 		hub[i]->vm_inv_eng0_ack =
524 			SOC15_REG_OFFSET(MMHUB, 0,
525 					 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
526 					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
527 		hub[i]->vm_context0_cntl =
528 			SOC15_REG_OFFSET(MMHUB, 0,
529 					 mmVML2VC0_VM_CONTEXT0_CNTL) +
530 					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
531 		hub[i]->vm_l2_pro_fault_status =
532 			SOC15_REG_OFFSET(MMHUB, 0,
533 				    mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
534 				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
535 		hub[i]->vm_l2_pro_fault_cntl =
536 			SOC15_REG_OFFSET(MMHUB, 0,
537 				    mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
538 				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
539 
540 		hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL -
541 			mmVML2VC0_VM_CONTEXT0_CNTL;
542 		hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
543 			mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
544 		hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ -
545 			mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
546 		hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
547 			mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
548 	}
549 }
550 
551 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
552 							bool enable)
553 {
554 	uint32_t def, data, def1, data1;
555 	int i, j;
556 	int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
557 
558 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
559 		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
560 					mmATCL2_0_ATC_L2_MISC_CG,
561 					i * MMHUB_INSTANCE_REGISTER_OFFSET);
562 
563 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
564 			data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
565 		else
566 			data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
567 
568 		if (def != data)
569 			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
570 				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
571 
572 		for (j = 0; j < 5; j++) {
573 			def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
574 					mmDAGB0_CNTL_MISC2,
575 					i * MMHUB_INSTANCE_REGISTER_OFFSET +
576 					j * dist);
577 			if (enable &&
578 			    (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
579 				data1 &=
580 				    ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
581 				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
582 				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
583 				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
584 				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
585 				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
586 			} else {
587 				data1 |=
588 				    (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
589 				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
590 				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
591 				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
592 				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
593 				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
594 			}
595 
596 			if (def1 != data1)
597 				WREG32_SOC15_OFFSET(MMHUB, 0,
598 					mmDAGB0_CNTL_MISC2,
599 					i * MMHUB_INSTANCE_REGISTER_OFFSET +
600 					j * dist, data1);
601 
602 			if (i == 1 && j == 3)
603 				break;
604 		}
605 	}
606 }
607 
608 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
609 						       bool enable)
610 {
611 	uint32_t def, data;
612 	int i;
613 
614 	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
615 		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
616 					mmATCL2_0_ATC_L2_MISC_CG,
617 					i * MMHUB_INSTANCE_REGISTER_OFFSET);
618 
619 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
620 			data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
621 		else
622 			data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
623 
624 		if (def != data)
625 			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
626 				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
627 	}
628 }
629 
630 static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
631 			       enum amd_clockgating_state state)
632 {
633 	if (amdgpu_sriov_vf(adev))
634 		return 0;
635 
636 	switch (adev->asic_type) {
637 	case CHIP_ARCTURUS:
638 		mmhub_v9_4_update_medium_grain_clock_gating(adev,
639 				state == AMD_CG_STATE_GATE);
640 		mmhub_v9_4_update_medium_grain_light_sleep(adev,
641 				state == AMD_CG_STATE_GATE);
642 		break;
643 	default:
644 		break;
645 	}
646 
647 	return 0;
648 }
649 
650 static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags)
651 {
652 	int data, data1;
653 
654 	if (amdgpu_sriov_vf(adev))
655 		*flags = 0;
656 
657 	/* AMD_CG_SUPPORT_MC_MGCG */
658 	data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
659 
660 	data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
661 
662 	if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
663 	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
664 		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
665 		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
666 		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
667 		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
668 		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
669 		*flags |= AMD_CG_SUPPORT_MC_MGCG;
670 
671 	/* AMD_CG_SUPPORT_MC_LS */
672 	if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
673 		*flags |= AMD_CG_SUPPORT_MC_LS;
674 }
675 
676 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
677 	/* MMHUB Range 0 */
678 	{ "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
679 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
680 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
681 	},
682 	{ "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
683 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
684 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
685 	},
686 	{ "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
687 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
688 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
689 	},
690 	{ "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
691 	SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
692 	SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
693 	},
694 	{ "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
695 	SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
696 	SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
697 	},
698 	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
699 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
700 	0, 0,
701 	},
702 	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
703 	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
704 	0, 0,
705 	},
706 	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
707 	SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
708 	0, 0,
709 	},
710 	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
711 	SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
712 	0, 0,
713 	},
714 	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
715 	SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
716 	0, 0,
717 	},
718 	{ "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
719 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
720 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
721 	},
722 	{ "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
723 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
724 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
725 	},
726 	{ "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
727 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
728 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
729 	},
730 	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
731 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
732 	0, 0,
733 	},
734 	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
735 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
736 	0, 0,
737 	},
738 	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
739 	0, 0,
740 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
741 	},
742 	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
743 	0, 0,
744 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
745 	},
746 	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
747 	0, 0,
748 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
749 	},
750 	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
751 	0, 0,
752 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
753 	},
754 	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
755 	0, 0,
756 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
757 	},
758 	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
759 	0, 0,
760 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
761 	},
762 	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
763 	0, 0,
764 	SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
765 	},
766 	{ "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
767 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
768 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
769 	},
770 	{ "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
771 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
772 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
773 	},
774 	{ "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
775 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
776 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
777 	},
778 	{ "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
779 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
780 	SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
781 	},
782 
783 	/* MMHUB Range 1 */
784 	{ "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
785 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
786 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
787 	},
788 	{ "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
789 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
790 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
791 	},
792 	{ "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
793 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
794 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
795 	},
796 	{ "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
797 	SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
798 	SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
799 	},
800 	{ "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
801 	SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
802 	SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
803 	},
804 	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
805 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
806 	0, 0,
807 	},
808 	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
809 	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
810 	0, 0,
811 	},
812 	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
813 	SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
814 	0, 0,
815 	},
816 	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
817 	SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
818 	0, 0,
819 	},
820 	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
821 	SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
822 	0, 0,
823 	},
824 	{ "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
825 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
826 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
827 	},
828 	{ "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
829 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
830 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
831 	},
832 	{ "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
833 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
834 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
835 	},
836 	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
837 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
838 	0, 0,
839 	},
840 	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
841 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
842 	0, 0,
843 	},
844 	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
845 	0, 0,
846 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
847 	},
848 	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
849 	0, 0,
850 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
851 	},
852 	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
853 	0, 0,
854 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
855 	},
856 	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
857 	0, 0,
858 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
859 	},
860 	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
861 	0, 0,
862 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
863 	},
864 	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
865 	0, 0,
866 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
867 	},
868 	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
869 	0, 0,
870 	SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
871 	},
872 	{ "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
873 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
874 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
875 	},
876 	{ "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
877 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
878 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
879 	},
880 	{ "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
881 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
882 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
883 	},
884 	{ "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
885 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
886 	SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
887 	},
888 
889 	/* MMHAB Range 2*/
890 	{ "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
891 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
892 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
893 	},
894 	{ "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
895 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
896 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
897 	},
898 	{ "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
899 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
900 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
901 	},
902 	{ "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
903 	SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
904 	SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
905 	},
906 	{ "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
907 	SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
908 	SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
909 	},
910 	{ "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
911 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
912 	0, 0,
913 	},
914 	{ "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
915 	SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
916 	0, 0,
917 	},
918 	{ "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
919 	SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
920 	0, 0,
921 	},
922 	{ "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
923 	SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
924 	0, 0,
925 	},
926 	{ "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
927 	SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
928 	0, 0,
929 	},
930 	{ "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
931 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
932 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
933 	},
934 	{ "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
935 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
936 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
937 	},
938 	{ "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
939 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
940 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
941 	},
942 	{ "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
943 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
944 	0, 0,
945 	},
946 	{ "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
947 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
948 	0, 0,
949 	},
950 	{ "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
951 	0, 0,
952 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
953 	},
954 	{ "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
955 	0, 0,
956 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
957 	},
958 	{ "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
959 	0, 0,
960 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
961 	},
962 	{ "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
963 	0, 0,
964 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
965 	},
966 	{ "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
967 	0, 0,
968 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
969 	},
970 	{ "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
971 	0, 0,
972 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
973 	},
974 	{ "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
975 	0, 0,
976 	SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
977 	},
978 	{ "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
979 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
980 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
981 	},
982 	{ "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
983 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
984 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
985 	},
986 	{ "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
987 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
988 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
989 	},
990 	{ "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
991 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
992 	SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
993 	},
994 
995 	/* MMHUB Rang 3 */
996 	{ "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
997 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
998 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
999 	},
1000 	{ "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1001 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1002 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1003 	},
1004 	{ "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1005 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1006 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1007 	},
1008 	{ "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1009 	SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1010 	SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1011 	},
1012 	{ "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1013 	SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1014 	SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1015 	},
1016 	{ "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1017 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1018 	0, 0,
1019 	},
1020 	{ "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1021 	SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1022 	0, 0,
1023 	},
1024 	{ "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1025 	SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1026 	0, 0,
1027 	},
1028 	{ "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1029 	SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1030 	0, 0,
1031 	},
1032 	{ "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1033 	SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1034 	0, 0,
1035 	},
1036 	{ "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1037 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1038 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1039 	},
1040 	{ "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1041 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1042 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1043 	},
1044 	{ "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1045 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1046 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1047 	},
1048 	{ "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1049 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1050 	0, 0,
1051 	},
1052 	{ "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1053 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1054 	0, 0,
1055 	},
1056 	{ "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1057 	0, 0,
1058 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1059 	},
1060 	{ "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1061 	0, 0,
1062 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1063 	},
1064 	{ "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1065 	0, 0,
1066 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1067 	},
1068 	{ "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1069 	0, 0,
1070 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1071 	},
1072 	{ "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1073 	0, 0,
1074 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1075 	},
1076 	{ "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1077 	0, 0,
1078 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1079 	},
1080 	{ "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1081 	0, 0,
1082 	SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1083 	},
1084 	{ "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1085 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1086 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1087 	},
1088 	{ "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1089 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1090 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1091 	},
1092 	{ "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1093 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1094 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1095 	},
1096 	{ "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1097 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1098 	SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1099 	},
1100 
1101 	/* MMHUB Range 4 */
1102 	{ "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1103 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1104 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1105 	},
1106 	{ "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1107 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1108 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1109 	},
1110 	{ "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1111 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1112 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1113 	},
1114 	{ "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1115 	SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1116 	SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1117 	},
1118 	{ "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1119 	SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1120 	SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1121 	},
1122 	{ "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1123 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1124 	0, 0,
1125 	},
1126 	{ "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1127 	SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1128 	0, 0,
1129 	},
1130 	{ "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1131 	SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1132 	0, 0,
1133 	},
1134 	{ "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1135 	SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1136 	0, 0,
1137 	},
1138 	{ "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1139 	SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1140 	0, 0,
1141 	},
1142 	{ "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1143 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1144 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1145 	},
1146 	{ "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1147 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1148 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1149 	},
1150 	{ "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1151 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1152 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1153 	},
1154 	{ "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1155 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1156 	0, 0,
1157 	},
1158 	{ "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1159 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1160 	0, 0,
1161 	},
1162 	{ "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1163 	0, 0,
1164 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1165 	},
1166 	{ "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1167 	0, 0,
1168 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1169 	},
1170 	{ "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1171 	0, 0,
1172 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1173 	},
1174 	{ "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1175 	0, 0,
1176 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1177 	},
1178 	{ "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1179 	0, 0,
1180 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1181 	},
1182 	{ "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1183 	0, 0,
1184 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1185 	},
1186 	{ "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1187 	0, 0,
1188 	SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1189 	},
1190 	{ "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1191 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1192 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1193 	},
1194 	{ "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1195 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1196 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1197 	},
1198 	{ "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1199 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1200 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1201 	},
1202 	{ "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1203 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1204 	SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1205 	},
1206 
1207 	/* MMHUAB Range 5 */
1208 	{ "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1209 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1210 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1211 	},
1212 	{ "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1213 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1214 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1215 	},
1216 	{ "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1217 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1218 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1219 	},
1220 	{ "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1221 	SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1222 	SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1223 	},
1224 	{ "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1225 	SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1226 	SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1227 	},
1228 	{ "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1229 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1230 	0, 0,
1231 	},
1232 	{ "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1233 	SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1234 	0, 0,
1235 	},
1236 	{ "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1237 	SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1238 	0, 0,
1239 	},
1240 	{ "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1241 	SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1242 	0, 0,
1243 	},
1244 	{ "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1245 	SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1246 	0, 0,
1247 	},
1248 	{ "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1249 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1250 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1251 	},
1252 	{ "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1253 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1254 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1255 	},
1256 	{ "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1257 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1258 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1259 	},
1260 	{ "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1261 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1262 	0, 0,
1263 	},
1264 	{ "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1265 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1266 	0, 0,
1267 	},
1268 	{ "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1269 	0, 0,
1270 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1271 	},
1272 	{ "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1273 	0, 0,
1274 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1275 	},
1276 	{ "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1277 	0, 0,
1278 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1279 	},
1280 	{ "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1281 	0, 0,
1282 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1283 	},
1284 	{ "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1285 	0, 0,
1286 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1287 	},
1288 	{ "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1289 	0, 0,
1290 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1291 	},
1292 	{ "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1293 	0, 0,
1294 	SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1295 	},
1296 	{ "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1297 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1298 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1299 	},
1300 	{ "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1301 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1302 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1303 	},
1304 	{ "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1305 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1306 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1307 	},
1308 	{ "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1309 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1310 	SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1311 	},
1312 
1313 	/* MMHUB Range 6 */
1314 	{ "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1315 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1316 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1317 	},
1318 	{ "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1319 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1320 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1321 	},
1322 	{ "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1323 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1324 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1325 	},
1326 	{ "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1327 	SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1328 	SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1329 	},
1330 	{ "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1331 	SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1332 	SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1333 	},
1334 	{ "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1335 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1336 	0, 0,
1337 	},
1338 	{ "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1339 	SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1340 	0, 0,
1341 	},
1342 	{ "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1343 	SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1344 	0, 0,
1345 	},
1346 	{ "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1347 	SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1348 	0, 0,
1349 	},
1350 	{ "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1351 	SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1352 	0, 0,
1353 	},
1354 	{ "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1355 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1356 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1357 	},
1358 	{ "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1359 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1360 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1361 	},
1362 	{ "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1363 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1364 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1365 	},
1366 	{ "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1367 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1368 	0, 0,
1369 	},
1370 	{ "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1371 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1372 	0, 0,
1373 	},
1374 	{ "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1375 	0, 0,
1376 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1377 	},
1378 	{ "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1379 	0, 0,
1380 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1381 	},
1382 	{ "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1383 	0, 0,
1384 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1385 	},
1386 	{ "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1387 	0, 0,
1388 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1389 	},
1390 	{ "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1391 	0, 0,
1392 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1393 	},
1394 	{ "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1395 	0, 0,
1396 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1397 	},
1398 	{ "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1399 	0, 0,
1400 	SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1401 	},
1402 	{ "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1403 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1404 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1405 	},
1406 	{ "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1407 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1408 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1409 	},
1410 	{ "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1411 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1412 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1413 	},
1414 	{ "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1415 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1416 	SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1417 	},
1418 
1419 	/* MMHUB Range 7*/
1420 	{ "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1421 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1422 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1423 	},
1424 	{ "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1425 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1426 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1427 	},
1428 	{ "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1429 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1430 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1431 	},
1432 	{ "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1433 	SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1434 	SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1435 	},
1436 	{ "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1437 	SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1438 	SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1439 	},
1440 	{ "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1441 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1442 	0, 0,
1443 	},
1444 	{ "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1445 	SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1446 	0, 0,
1447 	},
1448 	{ "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1449 	SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1450 	0, 0,
1451 	},
1452 	{ "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1453 	SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1454 	0, 0,
1455 	},
1456 	{ "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1457 	SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1458 	0, 0,
1459 	},
1460 	{ "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1461 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1462 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1463 	},
1464 	{ "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1465 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1466 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1467 	},
1468 	{ "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1469 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1470 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1471 	},
1472 	{ "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1473 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1474 	0, 0,
1475 	},
1476 	{ "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1477 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1478 	0, 0,
1479 	},
1480 	{ "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1481 	0, 0,
1482 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1483 	},
1484 	{ "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1485 	0, 0,
1486 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1487 	},
1488 	{ "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1489 	0, 0,
1490 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1491 	},
1492 	{ "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1493 	0, 0,
1494 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1495 	},
1496 	{ "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1497 	0, 0,
1498 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1499 	},
1500 	{ "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1501 	0, 0,
1502 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1503 	},
1504 	{ "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1505 	0, 0,
1506 	SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1507 	},
1508 	{ "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1509 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1510 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1511 	},
1512 	{ "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1513 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1514 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1515 	},
1516 	{ "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1517 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1518 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1519 	},
1520 	{ "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1521 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1522 	SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1523 	}
1524 };
1525 
1526 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1527 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1528 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1529 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1530 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1531 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1532 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1533 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1534 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1535 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1536 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1537 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1538 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1539 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1540 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1541 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1542 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1543 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1544 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1545 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1546 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1547 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1548 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1549 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1550 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1551 };
1552 
1553 static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1554 					  const struct soc15_reg_entry *reg,
1555 					  uint32_t value,
1556 					  uint32_t *sec_count,
1557 					  uint32_t *ded_count)
1558 {
1559 	uint32_t i;
1560 	uint32_t sec_cnt, ded_cnt;
1561 
1562 	for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1563 		if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1564 			continue;
1565 
1566 		sec_cnt = (value &
1567 				mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1568 				mmhub_v9_4_ras_fields[i].sec_count_shift;
1569 		if (sec_cnt) {
1570 			dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1571 				mmhub_v9_4_ras_fields[i].name,
1572 				sec_cnt);
1573 			*sec_count += sec_cnt;
1574 		}
1575 
1576 		ded_cnt = (value &
1577 				mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1578 				mmhub_v9_4_ras_fields[i].ded_count_shift;
1579 		if (ded_cnt) {
1580 			dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1581 				mmhub_v9_4_ras_fields[i].name,
1582 				ded_cnt);
1583 			*ded_count += ded_cnt;
1584 		}
1585 	}
1586 
1587 	return 0;
1588 }
1589 
1590 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1591 					   void *ras_error_status)
1592 {
1593 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1594 	uint32_t sec_count = 0, ded_count = 0;
1595 	uint32_t i;
1596 	uint32_t reg_value;
1597 
1598 	err_data->ue_count = 0;
1599 	err_data->ce_count = 0;
1600 
1601 	for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1602 		reg_value =
1603 			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1604 		if (reg_value)
1605 			mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1606 				reg_value, &sec_count, &ded_count);
1607 	}
1608 
1609 	err_data->ce_count += sec_count;
1610 	err_data->ue_count += ded_count;
1611 }
1612 
1613 static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1614 {
1615 	uint32_t i;
1616 
1617 	/* read back edc counter registers to reset the counters to 0 */
1618 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1619 		for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1620 			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1621 	}
1622 }
1623 
1624 static const struct soc15_reg_entry mmhub_v9_4_err_status_regs[] = {
1625 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_ERR_STATUS), 0, 0, 0 },
1626 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_ERR_STATUS), 0, 0, 0 },
1627 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_ERR_STATUS), 0, 0, 0 },
1628 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_ERR_STATUS), 0, 0, 0 },
1629 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_ERR_STATUS), 0, 0, 0 },
1630 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_ERR_STATUS), 0, 0, 0 },
1631 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_ERR_STATUS), 0, 0, 0 },
1632 	{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_ERR_STATUS), 0, 0, 0 },
1633 };
1634 
1635 static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev)
1636 {
1637 	int i;
1638 	uint32_t reg_value;
1639 
1640 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1641 		return;
1642 
1643 	for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) {
1644 		reg_value =
1645 			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));
1646 		if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1647 		    REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1648 		    REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1649 			/* SDP read/write error/parity error in FUE_IS_FATAL mode
1650 			 * can cause system fatal error in arcturas. Harvest the error
1651 			 * status before GPU reset */
1652 			dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1653 					i, reg_value);
1654 		}
1655 	}
1656 }
1657 
1658 const struct amdgpu_ras_block_hw_ops mmhub_v9_4_ras_hw_ops = {
1659 	.query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1660 	.reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1661 	.query_ras_error_status = mmhub_v9_4_query_ras_error_status,
1662 };
1663 
1664 struct amdgpu_mmhub_ras mmhub_v9_4_ras = {
1665 	.ras_block = {
1666 		.hw_ops = &mmhub_v9_4_ras_hw_ops,
1667 	},
1668 };
1669 
1670 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1671 	.get_fb_location = mmhub_v9_4_get_fb_location,
1672 	.init = mmhub_v9_4_init,
1673 	.gart_enable = mmhub_v9_4_gart_enable,
1674 	.set_fault_enable_default = mmhub_v9_4_set_fault_enable_default,
1675 	.gart_disable = mmhub_v9_4_gart_disable,
1676 	.set_clockgating = mmhub_v9_4_set_clockgating,
1677 	.get_clockgating = mmhub_v9_4_get_clockgating,
1678 	.setup_vm_pt_regs = mmhub_v9_4_setup_vm_pt_regs,
1679 };
1680