1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v9_4.h" 25 26 #include "mmhub/mmhub_9_4_1_offset.h" 27 #include "mmhub/mmhub_9_4_1_sh_mask.h" 28 #include "mmhub/mmhub_9_4_1_default.h" 29 #include "athub/athub_1_0_offset.h" 30 #include "athub/athub_1_0_sh_mask.h" 31 #include "vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #define MMHUB_NUM_INSTANCES 2 36 #define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000 37 38 u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev) 39 { 40 /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */ 41 u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); 42 u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP); 43 44 base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 45 base <<= 24; 46 47 top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 48 top <<= 24; 49 50 adev->gmc.fb_start = base; 51 adev->gmc.fb_end = top; 52 53 return base; 54 } 55 56 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid, 57 uint32_t vmid, uint64_t value) 58 { 59 /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to 60 * mmVML2VC0_VM_CONTEXT1_* 61 */ 62 int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 63 - mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 64 65 WREG32_SOC15_OFFSET(MMHUB, 0, 66 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 67 dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 68 lower_32_bits(value)); 69 70 WREG32_SOC15_OFFSET(MMHUB, 0, 71 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 72 dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 73 upper_32_bits(value)); 74 75 } 76 77 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev, 78 int hubid) 79 { 80 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 81 82 mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base); 83 84 WREG32_SOC15_OFFSET(MMHUB, 0, 85 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 86 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 87 (u32)(adev->gmc.gart_start >> 12)); 88 WREG32_SOC15_OFFSET(MMHUB, 0, 89 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 90 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 91 (u32)(adev->gmc.gart_start >> 44)); 92 93 WREG32_SOC15_OFFSET(MMHUB, 0, 94 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 95 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 96 (u32)(adev->gmc.gart_end >> 12)); 97 WREG32_SOC15_OFFSET(MMHUB, 0, 98 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 99 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 100 (u32)(adev->gmc.gart_end >> 44)); 101 } 102 103 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev, 104 int hubid) 105 { 106 uint64_t value; 107 uint32_t tmp; 108 109 /* Program the AGP BAR */ 110 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE, 111 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 112 0); 113 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP, 114 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 115 adev->gmc.agp_end >> 24); 116 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT, 117 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 118 adev->gmc.agp_start >> 24); 119 120 /* Program the system aperture low logical page number. */ 121 WREG32_SOC15_OFFSET(MMHUB, 0, 122 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR, 123 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 124 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 125 WREG32_SOC15_OFFSET(MMHUB, 0, 126 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 127 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 128 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 129 130 /* Set default page address. */ 131 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 132 adev->vm_manager.vram_base_offset; 133 WREG32_SOC15_OFFSET(MMHUB, 0, 134 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 135 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 136 (u32)(value >> 12)); 137 WREG32_SOC15_OFFSET(MMHUB, 0, 138 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 139 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 140 (u32)(value >> 44)); 141 142 /* Program "protection fault". */ 143 WREG32_SOC15_OFFSET(MMHUB, 0, 144 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 145 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 146 (u32)(adev->dummy_page_addr >> 12)); 147 WREG32_SOC15_OFFSET(MMHUB, 0, 148 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 149 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 150 (u32)((u64)adev->dummy_page_addr >> 44)); 151 152 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 153 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 154 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 155 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 156 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 157 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 158 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 159 } 160 161 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid) 162 { 163 uint32_t tmp; 164 165 /* Setup TLB control */ 166 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 167 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 168 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 169 170 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 171 ENABLE_L1_TLB, 1); 172 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 173 SYSTEM_ACCESS_MODE, 3); 174 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 175 ENABLE_ADVANCED_DRIVER_MODEL, 1); 176 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 177 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 178 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 179 ECO_BITS, 0); 180 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 181 MTYPE, MTYPE_UC);/* XXX for emulation. */ 182 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 183 ATC_EN, 1); 184 185 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 186 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 187 } 188 189 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid) 190 { 191 uint32_t tmp; 192 193 /* Setup L2 cache */ 194 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 195 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 196 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 197 ENABLE_L2_CACHE, 1); 198 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 199 ENABLE_L2_FRAGMENT_PROCESSING, 1); 200 /* XXX for emulation, Refer to closed source code.*/ 201 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 202 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 203 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 204 PDE_FAULT_CLASSIFICATION, 0); 205 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 206 CONTEXT1_IDENTITY_ACCESS_MODE, 1); 207 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 208 IDENTITY_MODE_FRAGMENT_SIZE, 0); 209 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 210 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 211 212 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 213 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 214 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 215 INVALIDATE_ALL_L1_TLBS, 1); 216 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 217 INVALIDATE_L2_CACHE, 1); 218 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 219 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 220 221 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT; 222 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 223 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 224 225 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT; 226 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 227 VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 228 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 229 VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 230 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4, 231 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 232 } 233 234 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev, 235 int hubid) 236 { 237 uint32_t tmp; 238 239 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 240 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 241 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 242 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 243 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, 244 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 245 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 246 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 247 } 248 249 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev, 250 int hubid) 251 { 252 WREG32_SOC15_OFFSET(MMHUB, 0, 253 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 254 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF); 255 WREG32_SOC15_OFFSET(MMHUB, 0, 256 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 257 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F); 258 259 WREG32_SOC15_OFFSET(MMHUB, 0, 260 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 261 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 262 WREG32_SOC15_OFFSET(MMHUB, 0, 263 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 264 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 265 266 WREG32_SOC15_OFFSET(MMHUB, 0, 267 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 268 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 269 WREG32_SOC15_OFFSET(MMHUB, 0, 270 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 271 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 272 } 273 274 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid) 275 { 276 uint32_t tmp; 277 int i; 278 279 for (i = 0; i <= 14; i++) { 280 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 281 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i); 282 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 283 ENABLE_CONTEXT, 1); 284 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 285 PAGE_TABLE_DEPTH, 286 adev->vm_manager.num_level); 287 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 288 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 289 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 290 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 291 1); 292 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 293 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 294 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 295 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 296 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 297 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 298 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 299 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 300 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 301 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 302 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 303 PAGE_TABLE_BLOCK_SIZE, 304 adev->vm_manager.block_size - 9); 305 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 306 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 307 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 308 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 309 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i, 310 tmp); 311 WREG32_SOC15_OFFSET(MMHUB, 0, 312 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 313 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); 314 WREG32_SOC15_OFFSET(MMHUB, 0, 315 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 316 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); 317 WREG32_SOC15_OFFSET(MMHUB, 0, 318 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 319 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 320 lower_32_bits(adev->vm_manager.max_pfn - 1)); 321 WREG32_SOC15_OFFSET(MMHUB, 0, 322 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 323 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 324 upper_32_bits(adev->vm_manager.max_pfn - 1)); 325 } 326 } 327 328 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev, 329 int hubid) 330 { 331 unsigned i; 332 333 for (i = 0; i < 18; ++i) { 334 WREG32_SOC15_OFFSET(MMHUB, 0, 335 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 336 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, 337 0xffffffff); 338 WREG32_SOC15_OFFSET(MMHUB, 0, 339 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 340 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, 341 0x1f); 342 } 343 } 344 345 int mmhub_v9_4_gart_enable(struct amdgpu_device *adev) 346 { 347 int i; 348 349 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 350 if (amdgpu_sriov_vf(adev)) { 351 /* 352 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase 353 * they are VF copy registers so vbios post doesn't 354 * program them, for SRIOV driver need to program them 355 */ 356 WREG32_SOC15_OFFSET(MMHUB, 0, 357 mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE, 358 i * MMHUB_INSTANCE_REGISTER_OFFSET, 359 adev->gmc.vram_start >> 24); 360 WREG32_SOC15_OFFSET(MMHUB, 0, 361 mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP, 362 i * MMHUB_INSTANCE_REGISTER_OFFSET, 363 adev->gmc.vram_end >> 24); 364 } 365 366 /* GART Enable. */ 367 mmhub_v9_4_init_gart_aperture_regs(adev, i); 368 mmhub_v9_4_init_system_aperture_regs(adev, i); 369 mmhub_v9_4_init_tlb_regs(adev, i); 370 mmhub_v9_4_init_cache_regs(adev, i); 371 372 mmhub_v9_4_enable_system_domain(adev, i); 373 mmhub_v9_4_disable_identity_aperture(adev, i); 374 mmhub_v9_4_setup_vmid_config(adev, i); 375 mmhub_v9_4_program_invalidation(adev, i); 376 } 377 378 return 0; 379 } 380 381 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev) 382 { 383 u32 tmp; 384 u32 i, j; 385 386 for (j = 0; j < MMHUB_NUM_INSTANCES; j++) { 387 /* Disable all tables */ 388 for (i = 0; i < 16; i++) 389 WREG32_SOC15_OFFSET(MMHUB, 0, 390 mmVML2VC0_VM_CONTEXT0_CNTL, 391 j * MMHUB_INSTANCE_REGISTER_OFFSET + 392 i, 0); 393 394 /* Setup TLB control */ 395 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 396 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 397 j * MMHUB_INSTANCE_REGISTER_OFFSET); 398 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 399 ENABLE_L1_TLB, 0); 400 tmp = REG_SET_FIELD(tmp, 401 VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 402 ENABLE_ADVANCED_DRIVER_MODEL, 0); 403 WREG32_SOC15_OFFSET(MMHUB, 0, 404 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 405 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 406 407 /* Setup L2 cache */ 408 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 409 j * MMHUB_INSTANCE_REGISTER_OFFSET); 410 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 411 ENABLE_L2_CACHE, 0); 412 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 413 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 414 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 415 j * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 416 } 417 } 418 419 /** 420 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 421 * 422 * @adev: amdgpu_device pointer 423 * @value: true redirects VM faults to the default page 424 */ 425 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value) 426 { 427 u32 tmp; 428 int i; 429 430 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 431 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 432 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 433 i * MMHUB_INSTANCE_REGISTER_OFFSET); 434 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 435 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 436 value); 437 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 438 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 439 value); 440 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 441 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, 442 value); 443 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 444 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, 445 value); 446 tmp = REG_SET_FIELD(tmp, 447 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 448 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 449 value); 450 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 451 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, 452 value); 453 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 454 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 455 value); 456 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 457 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 458 value); 459 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 460 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 461 value); 462 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 463 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 464 value); 465 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 466 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 467 value); 468 if (!value) { 469 tmp = REG_SET_FIELD(tmp, 470 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 471 CRASH_ON_NO_RETRY_FAULT, 1); 472 tmp = REG_SET_FIELD(tmp, 473 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 474 CRASH_ON_RETRY_FAULT, 1); 475 } 476 477 WREG32_SOC15_OFFSET(MMHUB, 0, 478 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 479 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 480 } 481 } 482 483 void mmhub_v9_4_init(struct amdgpu_device *adev) 484 { 485 struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = 486 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]}; 487 int i; 488 489 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 490 hub[i]->ctx0_ptb_addr_lo32 = 491 SOC15_REG_OFFSET(MMHUB, 0, 492 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + 493 i * MMHUB_INSTANCE_REGISTER_OFFSET; 494 hub[i]->ctx0_ptb_addr_hi32 = 495 SOC15_REG_OFFSET(MMHUB, 0, 496 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + 497 i * MMHUB_INSTANCE_REGISTER_OFFSET; 498 hub[i]->vm_inv_eng0_req = 499 SOC15_REG_OFFSET(MMHUB, 0, 500 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) + 501 i * MMHUB_INSTANCE_REGISTER_OFFSET; 502 hub[i]->vm_inv_eng0_ack = 503 SOC15_REG_OFFSET(MMHUB, 0, 504 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) + 505 i * MMHUB_INSTANCE_REGISTER_OFFSET; 506 hub[i]->vm_context0_cntl = 507 SOC15_REG_OFFSET(MMHUB, 0, 508 mmVML2VC0_VM_CONTEXT0_CNTL) + 509 i * MMHUB_INSTANCE_REGISTER_OFFSET; 510 hub[i]->vm_l2_pro_fault_status = 511 SOC15_REG_OFFSET(MMHUB, 0, 512 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) + 513 i * MMHUB_INSTANCE_REGISTER_OFFSET; 514 hub[i]->vm_l2_pro_fault_cntl = 515 SOC15_REG_OFFSET(MMHUB, 0, 516 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) + 517 i * MMHUB_INSTANCE_REGISTER_OFFSET; 518 } 519 } 520 521 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 522 bool enable) 523 { 524 uint32_t def, data, def1, data1; 525 int i, j; 526 int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2; 527 528 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 529 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 530 mmATCL2_0_ATC_L2_MISC_CG, 531 i * MMHUB_INSTANCE_REGISTER_OFFSET); 532 533 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 534 data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 535 else 536 data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 537 538 if (def != data) 539 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 540 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 541 542 for (j = 0; j < 5; j++) { 543 def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0, 544 mmDAGB0_CNTL_MISC2, 545 i * MMHUB_INSTANCE_REGISTER_OFFSET + 546 j * dist); 547 if (enable && 548 (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 549 data1 &= 550 ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 551 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 552 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 553 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 554 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 555 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 556 } else { 557 data1 |= 558 (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 559 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 560 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 561 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 562 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 563 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 564 } 565 566 if (def1 != data1) 567 WREG32_SOC15_OFFSET(MMHUB, 0, 568 mmDAGB0_CNTL_MISC2, 569 i * MMHUB_INSTANCE_REGISTER_OFFSET + 570 j * dist, data1); 571 572 if (i == 1 && j == 3) 573 break; 574 } 575 } 576 } 577 578 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 579 bool enable) 580 { 581 uint32_t def, data; 582 int i; 583 584 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 585 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 586 mmATCL2_0_ATC_L2_MISC_CG, 587 i * MMHUB_INSTANCE_REGISTER_OFFSET); 588 589 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 590 data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 591 else 592 data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 593 594 if (def != data) 595 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 596 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 597 } 598 } 599 600 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev, 601 enum amd_clockgating_state state) 602 { 603 if (amdgpu_sriov_vf(adev)) 604 return 0; 605 606 switch (adev->asic_type) { 607 case CHIP_ARCTURUS: 608 mmhub_v9_4_update_medium_grain_clock_gating(adev, 609 state == AMD_CG_STATE_GATE ? true : false); 610 mmhub_v9_4_update_medium_grain_light_sleep(adev, 611 state == AMD_CG_STATE_GATE ? true : false); 612 break; 613 default: 614 break; 615 } 616 617 return 0; 618 } 619 620 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags) 621 { 622 int data, data1; 623 624 if (amdgpu_sriov_vf(adev)) 625 *flags = 0; 626 627 /* AMD_CG_SUPPORT_MC_MGCG */ 628 data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 629 630 data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 631 632 if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) && 633 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 634 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 635 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 636 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 637 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 638 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 639 *flags |= AMD_CG_SUPPORT_MC_MGCG; 640 641 /* AMD_CG_SUPPORT_MC_LS */ 642 if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 643 *flags |= AMD_CG_SUPPORT_MC_LS; 644 } 645