19fa57397SHawking Zhang /* 29fa57397SHawking Zhang * Copyright 2022 Advanced Micro Devices, Inc. 39fa57397SHawking Zhang * 49fa57397SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 59fa57397SHawking Zhang * copy of this software and associated documentation files (the "Software"), 69fa57397SHawking Zhang * to deal in the Software without restriction, including without limitation 79fa57397SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 89fa57397SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 99fa57397SHawking Zhang * Software is furnished to do so, subject to the following conditions: 109fa57397SHawking Zhang * 119fa57397SHawking Zhang * The above copyright notice and this permission notice shall be included in 129fa57397SHawking Zhang * all copies or substantial portions of the Software. 139fa57397SHawking Zhang * 149fa57397SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 159fa57397SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 169fa57397SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 179fa57397SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 189fa57397SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 199fa57397SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 209fa57397SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 219fa57397SHawking Zhang * 229fa57397SHawking Zhang */ 239fa57397SHawking Zhang 249fa57397SHawking Zhang #include "amdgpu.h" 259fa57397SHawking Zhang #include "mmhub_v3_0_2.h" 269fa57397SHawking Zhang 279fa57397SHawking Zhang #include "mmhub/mmhub_3_0_2_offset.h" 289fa57397SHawking Zhang #include "mmhub/mmhub_3_0_2_sh_mask.h" 299fa57397SHawking Zhang #include "navi10_enum.h" 309fa57397SHawking Zhang 319fa57397SHawking Zhang #include "soc15_common.h" 329fa57397SHawking Zhang 339fa57397SHawking Zhang #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 349fa57397SHawking Zhang #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 359fa57397SHawking Zhang #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 369fa57397SHawking Zhang 379fa57397SHawking Zhang static const char *mmhub_client_ids_v3_0_2[][2] = { 389fa57397SHawking Zhang [0][0] = "VMC", 399fa57397SHawking Zhang [4][0] = "DCEDMC", 409fa57397SHawking Zhang [5][0] = "DCEVGA", 419fa57397SHawking Zhang [6][0] = "MP0", 429fa57397SHawking Zhang [7][0] = "MP1", 439fa57397SHawking Zhang [8][0] = "MPIO", 449fa57397SHawking Zhang [16][0] = "HDP", 459fa57397SHawking Zhang [17][0] = "LSDMA", 469fa57397SHawking Zhang [18][0] = "JPEG", 479fa57397SHawking Zhang [19][0] = "VCNU0", 489fa57397SHawking Zhang [21][0] = "VSCH", 499fa57397SHawking Zhang [22][0] = "VCNU1", 509fa57397SHawking Zhang [23][0] = "VCN1", 519fa57397SHawking Zhang [32+20][0] = "VCN0", 529fa57397SHawking Zhang [2][1] = "DBGUNBIO", 539fa57397SHawking Zhang [3][1] = "DCEDWB", 549fa57397SHawking Zhang [4][1] = "DCEDMC", 559fa57397SHawking Zhang [5][1] = "DCEVGA", 569fa57397SHawking Zhang [6][1] = "MP0", 579fa57397SHawking Zhang [7][1] = "MP1", 589fa57397SHawking Zhang [8][1] = "MPIO", 599fa57397SHawking Zhang [10][1] = "DBGU0", 609fa57397SHawking Zhang [11][1] = "DBGU1", 619fa57397SHawking Zhang [12][1] = "DBGU2", 629fa57397SHawking Zhang [13][1] = "DBGU3", 639fa57397SHawking Zhang [14][1] = "XDP", 649fa57397SHawking Zhang [15][1] = "OSSSYS", 659fa57397SHawking Zhang [16][1] = "HDP", 669fa57397SHawking Zhang [17][1] = "LSDMA", 679fa57397SHawking Zhang [18][1] = "JPEG", 689fa57397SHawking Zhang [19][1] = "VCNU0", 699fa57397SHawking Zhang [20][1] = "VCN0", 709fa57397SHawking Zhang [21][1] = "VSCH", 719fa57397SHawking Zhang [22][1] = "VCNU1", 729fa57397SHawking Zhang [23][1] = "VCN1", 739fa57397SHawking Zhang }; 749fa57397SHawking Zhang 759fa57397SHawking Zhang static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid, 769fa57397SHawking Zhang uint32_t flush_type) 779fa57397SHawking Zhang { 789fa57397SHawking Zhang u32 req = 0; 799fa57397SHawking Zhang 809fa57397SHawking Zhang /* invalidate using legacy mode on vmid*/ 819fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 829fa57397SHawking Zhang PER_VMID_INVALIDATE_REQ, 1 << vmid); 839fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 849fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 859fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 869fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 879fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 889fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 899fa57397SHawking Zhang req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 909fa57397SHawking Zhang CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 919fa57397SHawking Zhang 929fa57397SHawking Zhang return req; 939fa57397SHawking Zhang } 949fa57397SHawking Zhang 959fa57397SHawking Zhang static void 969fa57397SHawking Zhang mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, 979fa57397SHawking Zhang uint32_t status) 989fa57397SHawking Zhang { 999fa57397SHawking Zhang uint32_t cid, rw; 1009fa57397SHawking Zhang const char *mmhub_cid = NULL; 1019fa57397SHawking Zhang 1029fa57397SHawking Zhang cid = REG_GET_FIELD(status, 1039fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, CID); 1049fa57397SHawking Zhang rw = REG_GET_FIELD(status, 1059fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, RW); 1069fa57397SHawking Zhang 1079fa57397SHawking Zhang dev_err(adev->dev, 1089fa57397SHawking Zhang "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 1099fa57397SHawking Zhang status); 1109fa57397SHawking Zhang 1119fa57397SHawking Zhang mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw]; 1129fa57397SHawking Zhang dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 1139fa57397SHawking Zhang mmhub_cid ? mmhub_cid : "unknown", cid); 1149fa57397SHawking Zhang dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 1159fa57397SHawking Zhang REG_GET_FIELD(status, 1169fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 1179fa57397SHawking Zhang dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 1189fa57397SHawking Zhang REG_GET_FIELD(status, 1199fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 1209fa57397SHawking Zhang dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 1219fa57397SHawking Zhang REG_GET_FIELD(status, 1229fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 1239fa57397SHawking Zhang dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 1249fa57397SHawking Zhang REG_GET_FIELD(status, 1259fa57397SHawking Zhang MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 1269fa57397SHawking Zhang dev_err(adev->dev, "\t RW: 0x%x\n", rw); 1279fa57397SHawking Zhang } 1289fa57397SHawking Zhang 1299fa57397SHawking Zhang static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 1309fa57397SHawking Zhang uint64_t page_table_base) 1319fa57397SHawking Zhang { 1329fa57397SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 1339fa57397SHawking Zhang 1349fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 1359fa57397SHawking Zhang hub->ctx_addr_distance * vmid, 1369fa57397SHawking Zhang lower_32_bits(page_table_base)); 1379fa57397SHawking Zhang 1389fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 1399fa57397SHawking Zhang hub->ctx_addr_distance * vmid, 1409fa57397SHawking Zhang upper_32_bits(page_table_base)); 1419fa57397SHawking Zhang } 1429fa57397SHawking Zhang 1439fa57397SHawking Zhang static void mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device *adev) 1449fa57397SHawking Zhang { 1459fa57397SHawking Zhang uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1469fa57397SHawking Zhang 1479fa57397SHawking Zhang mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base); 1489fa57397SHawking Zhang 1499fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 1509fa57397SHawking Zhang (u32)(adev->gmc.gart_start >> 12)); 1519fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 1529fa57397SHawking Zhang (u32)(adev->gmc.gart_start >> 44)); 1539fa57397SHawking Zhang 1549fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 1559fa57397SHawking Zhang (u32)(adev->gmc.gart_end >> 12)); 1569fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 1579fa57397SHawking Zhang (u32)(adev->gmc.gart_end >> 44)); 1589fa57397SHawking Zhang } 1599fa57397SHawking Zhang 1609fa57397SHawking Zhang static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev) 1619fa57397SHawking Zhang { 1629fa57397SHawking Zhang uint64_t value; 1639fa57397SHawking Zhang uint32_t tmp; 1649fa57397SHawking Zhang 1659fa57397SHawking Zhang /* Disable AGP. */ 1669fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 1679fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); 1689fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); 1699fa57397SHawking Zhang 1709fa57397SHawking Zhang if (!amdgpu_sriov_vf(adev)) { 1719fa57397SHawking Zhang /* 1729fa57397SHawking Zhang * the new L1 policy will block SRIOV guest from writing 1739fa57397SHawking Zhang * these regs, and they will be programed at host. 1749fa57397SHawking Zhang * so skip programing these regs. 1759fa57397SHawking Zhang */ 1769fa57397SHawking Zhang /* Program the system aperture low logical page number. */ 1779fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 1789fa57397SHawking Zhang adev->gmc.vram_start >> 18); 1799fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1809fa57397SHawking Zhang adev->gmc.vram_end >> 18); 1819fa57397SHawking Zhang } 1829fa57397SHawking Zhang 1839fa57397SHawking Zhang /* Set default page address. */ 184*7ccfd79fSChristian König value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + 1859fa57397SHawking Zhang adev->vm_manager.vram_base_offset; 1869fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 1879fa57397SHawking Zhang (u32)(value >> 12)); 1889fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 1899fa57397SHawking Zhang (u32)(value >> 44)); 1909fa57397SHawking Zhang 1919fa57397SHawking Zhang /* Program "protection fault". */ 1929fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 1939fa57397SHawking Zhang (u32)(adev->dummy_page_addr >> 12)); 1949fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 1959fa57397SHawking Zhang (u32)((u64)adev->dummy_page_addr >> 44)); 1969fa57397SHawking Zhang 1979fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 1989fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 1999fa57397SHawking Zhang ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 2009fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 2019fa57397SHawking Zhang } 2029fa57397SHawking Zhang 2039fa57397SHawking Zhang static void mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device *adev) 2049fa57397SHawking Zhang { 2059fa57397SHawking Zhang uint32_t tmp; 2069fa57397SHawking Zhang 2079fa57397SHawking Zhang /* Setup TLB control */ 2089fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 2099fa57397SHawking Zhang 2109fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 2119fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 2129fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 2139fa57397SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 1); 2149fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 2159fa57397SHawking Zhang SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 2169fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 2179fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 2189fa57397SHawking Zhang MTYPE, MTYPE_UC); /* UC, uncached */ 2199fa57397SHawking Zhang 2209fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 2219fa57397SHawking Zhang } 2229fa57397SHawking Zhang 2239fa57397SHawking Zhang static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev) 2249fa57397SHawking Zhang { 2259fa57397SHawking Zhang uint32_t tmp; 2269fa57397SHawking Zhang 2279fa57397SHawking Zhang /* These registers are not accessible to VF-SRIOV. 2289fa57397SHawking Zhang * The PF will program them instead. 2299fa57397SHawking Zhang */ 2309fa57397SHawking Zhang if (amdgpu_sriov_vf(adev)) 2319fa57397SHawking Zhang return; 2329fa57397SHawking Zhang 2339fa57397SHawking Zhang /* Setup L2 cache */ 2349fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 2359fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 2369fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 2379fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 2389fa57397SHawking Zhang ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 2399fa57397SHawking Zhang /* XXX for emulation, Refer to closed source code.*/ 2409fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 2419fa57397SHawking Zhang 0); 2429fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 2439fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 2449fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 2459fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 2469fa57397SHawking Zhang 2479fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 2489fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 2499fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 2509fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 2519fa57397SHawking Zhang 2529fa57397SHawking Zhang tmp = regMMVM_L2_CNTL3_DEFAULT; 2539fa57397SHawking Zhang if (adev->gmc.translate_further) { 2549fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 2559fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 2569fa57397SHawking Zhang L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 2579fa57397SHawking Zhang } else { 2589fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 2599fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 2609fa57397SHawking Zhang L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 2619fa57397SHawking Zhang } 2629fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 2639fa57397SHawking Zhang 2649fa57397SHawking Zhang tmp = regMMVM_L2_CNTL4_DEFAULT; 2659fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 2669fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 2679fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 2689fa57397SHawking Zhang 2699fa57397SHawking Zhang tmp = regMMVM_L2_CNTL5_DEFAULT; 2709fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 271347fafe0SYang Wang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 2729fa57397SHawking Zhang } 2739fa57397SHawking Zhang 2749fa57397SHawking Zhang static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev) 2759fa57397SHawking Zhang { 2769fa57397SHawking Zhang uint32_t tmp; 2779fa57397SHawking Zhang 2789fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 2799fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 2809fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 2819fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 2829fa57397SHawking Zhang RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 2839fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 2849fa57397SHawking Zhang } 2859fa57397SHawking Zhang 2869fa57397SHawking Zhang static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev) 2879fa57397SHawking Zhang { 2889fa57397SHawking Zhang /* These registers are not accessible to VF-SRIOV. 2899fa57397SHawking Zhang * The PF will program them instead. 2909fa57397SHawking Zhang */ 2919fa57397SHawking Zhang if (amdgpu_sriov_vf(adev)) 2929fa57397SHawking Zhang return; 2939fa57397SHawking Zhang 2949fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, 2959fa57397SHawking Zhang regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 2969fa57397SHawking Zhang 0xFFFFFFFF); 2979fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, 2989fa57397SHawking Zhang regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 2999fa57397SHawking Zhang 0x0000000F); 3009fa57397SHawking Zhang 3019fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, 3029fa57397SHawking Zhang regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 3039fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, 3049fa57397SHawking Zhang regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 3059fa57397SHawking Zhang 3069fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 3079fa57397SHawking Zhang 0); 3089fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 3099fa57397SHawking Zhang 0); 3109fa57397SHawking Zhang } 3119fa57397SHawking Zhang 3129fa57397SHawking Zhang static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev) 3139fa57397SHawking Zhang { 3149fa57397SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 3159fa57397SHawking Zhang int i; 3169fa57397SHawking Zhang uint32_t tmp; 3179fa57397SHawking Zhang 3189fa57397SHawking Zhang for (i = 0; i <= 14; i++) { 3199fa57397SHawking Zhang tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); 3209fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 3219fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 3229fa57397SHawking Zhang adev->vm_manager.num_level); 3239fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3249fa57397SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3259fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3269fa57397SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 3279fa57397SHawking Zhang 1); 3289fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3299fa57397SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3309fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3319fa57397SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3329fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3339fa57397SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3349fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3359fa57397SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3369fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3379fa57397SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 3389fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3399fa57397SHawking Zhang PAGE_TABLE_BLOCK_SIZE, 3409fa57397SHawking Zhang adev->vm_manager.block_size - 9); 3419fa57397SHawking Zhang /* Send no-retry XNACK on fault to suppress VM fault storm. */ 3429fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 3439fa57397SHawking Zhang RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 3449fa57397SHawking Zhang !amdgpu_noretry); 3459fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 3469fa57397SHawking Zhang i * hub->ctx_distance, tmp); 3479fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 3489fa57397SHawking Zhang i * hub->ctx_addr_distance, 0); 3499fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 3509fa57397SHawking Zhang i * hub->ctx_addr_distance, 0); 3519fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 3529fa57397SHawking Zhang i * hub->ctx_addr_distance, 3539fa57397SHawking Zhang lower_32_bits(adev->vm_manager.max_pfn - 1)); 3549fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 3559fa57397SHawking Zhang i * hub->ctx_addr_distance, 3569fa57397SHawking Zhang upper_32_bits(adev->vm_manager.max_pfn - 1)); 3579fa57397SHawking Zhang } 3589fa57397SHawking Zhang 3599fa57397SHawking Zhang hub->vm_cntx_cntl = tmp; 3609fa57397SHawking Zhang } 3619fa57397SHawking Zhang 3629fa57397SHawking Zhang static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev) 3639fa57397SHawking Zhang { 3649fa57397SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 3659fa57397SHawking Zhang unsigned i; 3669fa57397SHawking Zhang 3679fa57397SHawking Zhang for (i = 0; i < 18; ++i) { 3689fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 3699fa57397SHawking Zhang i * hub->eng_addr_distance, 0xffffffff); 3709fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 3719fa57397SHawking Zhang i * hub->eng_addr_distance, 0x1f); 3729fa57397SHawking Zhang } 3739fa57397SHawking Zhang } 3749fa57397SHawking Zhang 3759fa57397SHawking Zhang static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev) 3769fa57397SHawking Zhang { 3779fa57397SHawking Zhang /* GART Enable. */ 3789fa57397SHawking Zhang mmhub_v3_0_2_init_gart_aperture_regs(adev); 3799fa57397SHawking Zhang mmhub_v3_0_2_init_system_aperture_regs(adev); 3809fa57397SHawking Zhang mmhub_v3_0_2_init_tlb_regs(adev); 3819fa57397SHawking Zhang mmhub_v3_0_2_init_cache_regs(adev); 3829fa57397SHawking Zhang 3839fa57397SHawking Zhang mmhub_v3_0_2_enable_system_domain(adev); 3849fa57397SHawking Zhang mmhub_v3_0_2_disable_identity_aperture(adev); 3859fa57397SHawking Zhang mmhub_v3_0_2_setup_vmid_config(adev); 3869fa57397SHawking Zhang mmhub_v3_0_2_program_invalidation(adev); 3879fa57397SHawking Zhang 3889fa57397SHawking Zhang return 0; 3899fa57397SHawking Zhang } 3909fa57397SHawking Zhang 3919fa57397SHawking Zhang static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev) 3929fa57397SHawking Zhang { 3939fa57397SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 3949fa57397SHawking Zhang u32 tmp; 3959fa57397SHawking Zhang u32 i; 3969fa57397SHawking Zhang 3979fa57397SHawking Zhang /* Disable all tables */ 3989fa57397SHawking Zhang for (i = 0; i < 16; i++) 3999fa57397SHawking Zhang WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 4009fa57397SHawking Zhang i * hub->ctx_distance, 0); 4019fa57397SHawking Zhang 4029fa57397SHawking Zhang /* Setup TLB control */ 4039fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 4049fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 4059fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 4069fa57397SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 0); 4079fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 4089fa57397SHawking Zhang 4099fa57397SHawking Zhang /* Setup L2 cache */ 4109fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 4119fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 4129fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 4139fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 4149fa57397SHawking Zhang } 4159fa57397SHawking Zhang 4169fa57397SHawking Zhang /** 4179fa57397SHawking Zhang * mmhub_v3_0_2_set_fault_enable_default - update GART/VM fault handling 4189fa57397SHawking Zhang * 4199fa57397SHawking Zhang * @adev: amdgpu_device pointer 4209fa57397SHawking Zhang * @value: true redirects VM faults to the default page 4219fa57397SHawking Zhang */ 4229fa57397SHawking Zhang static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value) 4239fa57397SHawking Zhang { 4249fa57397SHawking Zhang u32 tmp; 4259fa57397SHawking Zhang 4269fa57397SHawking Zhang /* These registers are not accessible to VF-SRIOV. 4279fa57397SHawking Zhang * The PF will program them instead. 4289fa57397SHawking Zhang */ 4299fa57397SHawking Zhang if (amdgpu_sriov_vf(adev)) 4309fa57397SHawking Zhang return; 4319fa57397SHawking Zhang 4329fa57397SHawking Zhang tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 4339fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4349fa57397SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4359fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4369fa57397SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4379fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4389fa57397SHawking Zhang PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4399fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4409fa57397SHawking Zhang PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4419fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4429fa57397SHawking Zhang TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 4439fa57397SHawking Zhang value); 4449fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4459fa57397SHawking Zhang NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4469fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4479fa57397SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4489fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4499fa57397SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4509fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4519fa57397SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4529fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4539fa57397SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4549fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4559fa57397SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 4569fa57397SHawking Zhang if (!value) { 4579fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4589fa57397SHawking Zhang CRASH_ON_NO_RETRY_FAULT, 1); 4599fa57397SHawking Zhang tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 4609fa57397SHawking Zhang CRASH_ON_RETRY_FAULT, 1); 4619fa57397SHawking Zhang } 4629fa57397SHawking Zhang WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 4639fa57397SHawking Zhang } 4649fa57397SHawking Zhang 4659fa57397SHawking Zhang static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = { 4669fa57397SHawking Zhang .print_l2_protection_fault_status = mmhub_v3_0_2_print_l2_protection_fault_status, 4679fa57397SHawking Zhang .get_invalidate_req = mmhub_v3_0_2_get_invalidate_req, 4689fa57397SHawking Zhang }; 4699fa57397SHawking Zhang 4709fa57397SHawking Zhang static void mmhub_v3_0_2_init(struct amdgpu_device *adev) 4719fa57397SHawking Zhang { 4729fa57397SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 4739fa57397SHawking Zhang 4749fa57397SHawking Zhang hub->ctx0_ptb_addr_lo32 = 4759fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, 4769fa57397SHawking Zhang regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 4779fa57397SHawking Zhang hub->ctx0_ptb_addr_hi32 = 4789fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, 4799fa57397SHawking Zhang regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 4809fa57397SHawking Zhang hub->vm_inv_eng0_sem = 4819fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 4829fa57397SHawking Zhang hub->vm_inv_eng0_req = 4839fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 4849fa57397SHawking Zhang hub->vm_inv_eng0_ack = 4859fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 4869fa57397SHawking Zhang hub->vm_context0_cntl = 4879fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 4889fa57397SHawking Zhang hub->vm_l2_pro_fault_status = 4899fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 4909fa57397SHawking Zhang hub->vm_l2_pro_fault_cntl = 4919fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 4929fa57397SHawking Zhang 4939fa57397SHawking Zhang hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 4949fa57397SHawking Zhang hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 4959fa57397SHawking Zhang regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 4969fa57397SHawking Zhang hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 4979fa57397SHawking Zhang regMMVM_INVALIDATE_ENG0_REQ; 4989fa57397SHawking Zhang hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 4999fa57397SHawking Zhang regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 5009fa57397SHawking Zhang 5019fa57397SHawking Zhang hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5029fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5039fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5049fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5059fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5069fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 5079fa57397SHawking Zhang MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 5089fa57397SHawking Zhang 5099fa57397SHawking Zhang hub->vm_l2_bank_select_reserved_cid2 = 5109fa57397SHawking Zhang SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); 5119fa57397SHawking Zhang 5129fa57397SHawking Zhang hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs; 5139fa57397SHawking Zhang } 5149fa57397SHawking Zhang 5159fa57397SHawking Zhang static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev) 5169fa57397SHawking Zhang { 5179fa57397SHawking Zhang u64 base; 5189fa57397SHawking Zhang 5199fa57397SHawking Zhang base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 5209fa57397SHawking Zhang base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 5219fa57397SHawking Zhang base <<= 24; 5229fa57397SHawking Zhang 5239fa57397SHawking Zhang return base; 5249fa57397SHawking Zhang } 5259fa57397SHawking Zhang 5269fa57397SHawking Zhang static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev) 5279fa57397SHawking Zhang { 5289fa57397SHawking Zhang return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 5299fa57397SHawking Zhang } 5309fa57397SHawking Zhang 5319fa57397SHawking Zhang static void mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5329fa57397SHawking Zhang bool enable) 5339fa57397SHawking Zhang { 5349fa57397SHawking Zhang //TODO 5359fa57397SHawking Zhang } 5369fa57397SHawking Zhang 5379fa57397SHawking Zhang static void mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 5389fa57397SHawking Zhang bool enable) 5399fa57397SHawking Zhang { 5409fa57397SHawking Zhang //TODO 5419fa57397SHawking Zhang } 5429fa57397SHawking Zhang 5439fa57397SHawking Zhang static int mmhub_v3_0_2_set_clockgating(struct amdgpu_device *adev, 5449fa57397SHawking Zhang enum amd_clockgating_state state) 5459fa57397SHawking Zhang { 5469fa57397SHawking Zhang if (amdgpu_sriov_vf(adev)) 5479fa57397SHawking Zhang return 0; 5489fa57397SHawking Zhang 5499fa57397SHawking Zhang mmhub_v3_0_2_update_medium_grain_clock_gating(adev, 5509fa57397SHawking Zhang state == AMD_CG_STATE_GATE); 5519fa57397SHawking Zhang mmhub_v3_0_2_update_medium_grain_light_sleep(adev, 5529fa57397SHawking Zhang state == AMD_CG_STATE_GATE); 5539fa57397SHawking Zhang return 0; 5549fa57397SHawking Zhang } 5559fa57397SHawking Zhang 5569fa57397SHawking Zhang static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags) 5579fa57397SHawking Zhang { 5589fa57397SHawking Zhang //TODO 5599fa57397SHawking Zhang } 5609fa57397SHawking Zhang 5619fa57397SHawking Zhang const struct amdgpu_mmhub_funcs mmhub_v3_0_2_funcs = { 5629fa57397SHawking Zhang .init = mmhub_v3_0_2_init, 5639fa57397SHawking Zhang .get_fb_location = mmhub_v3_0_2_get_fb_location, 5649fa57397SHawking Zhang .get_mc_fb_offset = mmhub_v3_0_2_get_mc_fb_offset, 5659fa57397SHawking Zhang .gart_enable = mmhub_v3_0_2_gart_enable, 5669fa57397SHawking Zhang .set_fault_enable_default = mmhub_v3_0_2_set_fault_enable_default, 5679fa57397SHawking Zhang .gart_disable = mmhub_v3_0_2_gart_disable, 5689fa57397SHawking Zhang .set_clockgating = mmhub_v3_0_2_set_clockgating, 5699fa57397SHawking Zhang .get_clockgating = mmhub_v3_0_2_get_clockgating, 5709fa57397SHawking Zhang .setup_vm_pt_regs = mmhub_v3_0_2_setup_vm_pt_regs, 5719fa57397SHawking Zhang }; 572