1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_0.h" 26 27 #include "mmhub/mmhub_3_0_0_offset.h" 28 #include "mmhub/mmhub_3_0_0_sh_mask.h" 29 #include "navi10_enum.h" 30 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37 static const char *mmhub_client_ids_v3_0_0[][2] = { 38 [0][0] = "VMC", 39 [4][0] = "DCEDMC", 40 [5][0] = "DCEVGA", 41 [6][0] = "MP0", 42 [7][0] = "MP1", 43 [8][0] = "MPIO", 44 [16][0] = "HDP", 45 [17][0] = "LSDMA", 46 [18][0] = "JPEG", 47 [19][0] = "VCNU0", 48 [21][0] = "VSCH", 49 [22][0] = "VCNU1", 50 [23][0] = "VCN1", 51 [32+20][0] = "VCN0", 52 [2][1] = "DBGUNBIO", 53 [3][1] = "DCEDWB", 54 [4][1] = "DCEDMC", 55 [5][1] = "DCEVGA", 56 [6][1] = "MP0", 57 [7][1] = "MP1", 58 [8][1] = "MPIO", 59 [10][1] = "DBGU0", 60 [11][1] = "DBGU1", 61 [12][1] = "DBGU2", 62 [13][1] = "DBGU3", 63 [14][1] = "XDP", 64 [15][1] = "OSSSYS", 65 [16][1] = "HDP", 66 [17][1] = "LSDMA", 67 [18][1] = "JPEG", 68 [19][1] = "VCNU0", 69 [20][1] = "VCN0", 70 [21][1] = "VSCH", 71 [22][1] = "VCNU1", 72 [23][1] = "VCN1", 73 }; 74 75 static uint32_t mmhub_v3_0_get_invalidate_req(unsigned int vmid, 76 uint32_t flush_type) 77 { 78 u32 req = 0; 79 80 /* invalidate using legacy mode on vmid*/ 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 82 PER_VMID_INVALIDATE_REQ, 1 << vmid); 83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 90 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 91 92 return req; 93 } 94 95 static void 96 mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 97 uint32_t status) 98 { 99 uint32_t cid, rw; 100 const char *mmhub_cid = NULL; 101 102 cid = REG_GET_FIELD(status, 103 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 104 rw = REG_GET_FIELD(status, 105 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 106 107 dev_err(adev->dev, 108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 109 status); 110 switch (adev->ip_versions[MMHUB_HWIP][0]) { 111 case IP_VERSION(3, 0, 0): 112 mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw]; 113 break; 114 default: 115 mmhub_cid = NULL; 116 break; 117 } 118 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 119 mmhub_cid ? mmhub_cid : "unknown", cid); 120 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 121 REG_GET_FIELD(status, 122 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 123 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 124 REG_GET_FIELD(status, 125 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 126 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 127 REG_GET_FIELD(status, 128 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 129 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 130 REG_GET_FIELD(status, 131 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 132 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 133 } 134 135 static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 136 uint64_t page_table_base) 137 { 138 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 139 140 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 141 hub->ctx_addr_distance * vmid, 142 lower_32_bits(page_table_base)); 143 144 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 145 hub->ctx_addr_distance * vmid, 146 upper_32_bits(page_table_base)); 147 } 148 149 static void mmhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev) 150 { 151 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 152 153 mmhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base); 154 155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 156 (u32)(adev->gmc.gart_start >> 12)); 157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 158 (u32)(adev->gmc.gart_start >> 44)); 159 160 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 161 (u32)(adev->gmc.gart_end >> 12)); 162 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 163 (u32)(adev->gmc.gart_end >> 44)); 164 } 165 166 static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) 167 { 168 uint64_t value; 169 uint32_t tmp; 170 171 /* Disable AGP. */ 172 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0); 174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF); 175 176 if (!amdgpu_sriov_vf(adev)) { 177 /* 178 * the new L1 policy will block SRIOV guest from writing 179 * these regs, and they will be programed at host. 180 * so skip programing these regs. 181 */ 182 /* Program the system aperture low logical page number. */ 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 184 adev->gmc.vram_start >> 18); 185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 186 adev->gmc.vram_end >> 18); 187 } 188 189 /* Set default page address. */ 190 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 191 adev->vm_manager.vram_base_offset; 192 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 193 (u32)(value >> 12)); 194 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 195 (u32)(value >> 44)); 196 197 /* Program "protection fault". */ 198 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 199 (u32)(adev->dummy_page_addr >> 12)); 200 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 201 (u32)((u64)adev->dummy_page_addr >> 44)); 202 203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 204 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 205 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 206 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 207 } 208 209 static void mmhub_v3_0_init_tlb_regs(struct amdgpu_device *adev) 210 { 211 uint32_t tmp; 212 213 /* Setup TLB control */ 214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 215 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 219 ENABLE_ADVANCED_DRIVER_MODEL, 1); 220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 221 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 222 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 223 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 224 MTYPE, MTYPE_UC); /* UC, uncached */ 225 226 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 227 } 228 229 static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev) 230 { 231 uint32_t tmp; 232 233 /* These registers are not accessible to VF-SRIOV. 234 * The PF will program them instead. 235 */ 236 if (amdgpu_sriov_vf(adev)) 237 return; 238 239 /* Setup L2 cache */ 240 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 244 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 245 /* XXX for emulation, Refer to closed source code.*/ 246 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 247 0); 248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 251 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 252 253 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 256 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 257 258 tmp = regMMVM_L2_CNTL3_DEFAULT; 259 if (adev->gmc.translate_further) { 260 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 261 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 262 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 263 } else { 264 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 266 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 267 } 268 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 269 270 tmp = regMMVM_L2_CNTL4_DEFAULT; 271 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 272 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 273 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 274 275 tmp = regMMVM_L2_CNTL5_DEFAULT; 276 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 277 WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp); 278 } 279 280 static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev) 281 { 282 uint32_t tmp; 283 284 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 285 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 286 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 287 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 288 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 289 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 290 } 291 292 static void mmhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev) 293 { 294 /* These registers are not accessible to VF-SRIOV. 295 * The PF will program them instead. 296 */ 297 if (amdgpu_sriov_vf(adev)) 298 return; 299 300 WREG32_SOC15(MMHUB, 0, 301 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 302 0xFFFFFFFF); 303 WREG32_SOC15(MMHUB, 0, 304 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 305 0x0000000F); 306 307 WREG32_SOC15(MMHUB, 0, 308 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 309 WREG32_SOC15(MMHUB, 0, 310 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 311 312 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 313 0); 314 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 315 0); 316 } 317 318 static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev) 319 { 320 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 321 int i; 322 uint32_t tmp; 323 324 for (i = 0; i <= 14; i++) { 325 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 328 adev->vm_manager.num_level); 329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 330 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 332 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 333 1); 334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 335 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 337 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 338 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 339 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 340 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 341 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 342 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 343 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 344 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 345 PAGE_TABLE_BLOCK_SIZE, 346 adev->vm_manager.block_size - 9); 347 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 348 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 349 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 350 !amdgpu_noretry); 351 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 352 i * hub->ctx_distance, tmp); 353 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 354 i * hub->ctx_addr_distance, 0); 355 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 356 i * hub->ctx_addr_distance, 0); 357 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 358 i * hub->ctx_addr_distance, 359 lower_32_bits(adev->vm_manager.max_pfn - 1)); 360 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 361 i * hub->ctx_addr_distance, 362 upper_32_bits(adev->vm_manager.max_pfn - 1)); 363 } 364 } 365 366 static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev) 367 { 368 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 369 unsigned i; 370 371 for (i = 0; i < 18; ++i) { 372 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 373 i * hub->eng_addr_distance, 0xffffffff); 374 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 375 i * hub->eng_addr_distance, 0x1f); 376 } 377 } 378 379 static int mmhub_v3_0_gart_enable(struct amdgpu_device *adev) 380 { 381 /* GART Enable. */ 382 mmhub_v3_0_init_gart_aperture_regs(adev); 383 mmhub_v3_0_init_system_aperture_regs(adev); 384 mmhub_v3_0_init_tlb_regs(adev); 385 mmhub_v3_0_init_cache_regs(adev); 386 387 mmhub_v3_0_enable_system_domain(adev); 388 mmhub_v3_0_disable_identity_aperture(adev); 389 mmhub_v3_0_setup_vmid_config(adev); 390 mmhub_v3_0_program_invalidation(adev); 391 392 return 0; 393 } 394 395 static void mmhub_v3_0_gart_disable(struct amdgpu_device *adev) 396 { 397 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 398 u32 tmp; 399 u32 i; 400 401 /* Disable all tables */ 402 for (i = 0; i < 16; i++) 403 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 404 i * hub->ctx_distance, 0); 405 406 /* Setup TLB control */ 407 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 408 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 409 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 410 ENABLE_ADVANCED_DRIVER_MODEL, 0); 411 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 412 413 /* Setup L2 cache */ 414 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 415 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 416 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 417 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 418 } 419 420 /** 421 * mmhub_v3_0_set_fault_enable_default - update GART/VM fault handling 422 * 423 * @adev: amdgpu_device pointer 424 * @value: true redirects VM faults to the default page 425 */ 426 static void mmhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 427 { 428 u32 tmp; 429 430 /* These registers are not accessible to VF-SRIOV. 431 * The PF will program them instead. 432 */ 433 if (amdgpu_sriov_vf(adev)) 434 return; 435 436 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 438 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 440 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 442 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 444 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 446 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 447 value); 448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 449 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 450 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 451 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 452 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 453 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 454 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 455 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 456 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 457 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 458 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 459 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 460 if (!value) { 461 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 462 CRASH_ON_NO_RETRY_FAULT, 1); 463 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 464 CRASH_ON_RETRY_FAULT, 1); 465 } 466 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 467 } 468 469 static const struct amdgpu_vmhub_funcs mmhub_v3_0_vmhub_funcs = { 470 .print_l2_protection_fault_status = mmhub_v3_0_print_l2_protection_fault_status, 471 .get_invalidate_req = mmhub_v3_0_get_invalidate_req, 472 }; 473 474 static void mmhub_v3_0_init(struct amdgpu_device *adev) 475 { 476 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 477 478 hub->ctx0_ptb_addr_lo32 = 479 SOC15_REG_OFFSET(MMHUB, 0, 480 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 481 hub->ctx0_ptb_addr_hi32 = 482 SOC15_REG_OFFSET(MMHUB, 0, 483 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 484 hub->vm_inv_eng0_sem = 485 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 486 hub->vm_inv_eng0_req = 487 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 488 hub->vm_inv_eng0_ack = 489 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 490 hub->vm_context0_cntl = 491 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 492 hub->vm_l2_pro_fault_status = 493 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 494 hub->vm_l2_pro_fault_cntl = 495 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 496 497 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 498 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 499 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 500 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 501 regMMVM_INVALIDATE_ENG0_REQ; 502 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 503 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 504 505 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 506 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 507 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 508 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 509 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 510 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 511 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 512 513 hub->vm_l2_bank_select_reserved_cid2 = 514 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); 515 516 hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs; 517 } 518 519 static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev) 520 { 521 u64 base; 522 523 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 524 525 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 526 base <<= 24; 527 528 return base; 529 } 530 531 static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev) 532 { 533 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 534 } 535 536 static void mmhub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 537 bool enable) 538 { 539 //TODO 540 } 541 542 static void mmhub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 543 bool enable) 544 { 545 //TODO 546 } 547 548 static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev, 549 enum amd_clockgating_state state) 550 { 551 if (amdgpu_sriov_vf(adev)) 552 return 0; 553 554 mmhub_v3_0_update_medium_grain_clock_gating(adev, 555 state == AMD_CG_STATE_GATE); 556 mmhub_v3_0_update_medium_grain_light_sleep(adev, 557 state == AMD_CG_STATE_GATE); 558 return 0; 559 } 560 561 static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 562 { 563 //TODO 564 } 565 566 const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs = { 567 .init = mmhub_v3_0_init, 568 .get_fb_location = mmhub_v3_0_get_fb_location, 569 .get_mc_fb_offset = mmhub_v3_0_get_mc_fb_offset, 570 .gart_enable = mmhub_v3_0_gart_enable, 571 .set_fault_enable_default = mmhub_v3_0_set_fault_enable_default, 572 .gart_disable = mmhub_v3_0_gart_disable, 573 .set_clockgating = mmhub_v3_0_set_clockgating, 574 .get_clockgating = mmhub_v3_0_get_clockgating, 575 .setup_vm_pt_regs = mmhub_v3_0_setup_vm_pt_regs, 576 }; 577