1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_3.h" 26 27 #include "mmhub/mmhub_2_3_0_offset.h" 28 #include "mmhub/mmhub_2_3_0_sh_mask.h" 29 #include "mmhub/mmhub_2_3_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid, 35 uint32_t flush_type) 36 { 37 u32 req = 0; 38 39 /* invalidate using legacy mode on vmid*/ 40 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 41 PER_VMID_INVALIDATE_REQ, 1 << vmid); 42 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 43 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 44 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 45 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 46 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 47 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 48 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 49 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 50 51 return req; 52 } 53 54 static void 55 mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 56 uint32_t status) 57 { 58 dev_err(adev->dev, 59 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 60 status); 61 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 62 REG_GET_FIELD(status, 63 MMVM_L2_PROTECTION_FAULT_STATUS, CID)); 64 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 65 REG_GET_FIELD(status, 66 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 67 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 68 REG_GET_FIELD(status, 69 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 70 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 71 REG_GET_FIELD(status, 72 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 73 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 74 REG_GET_FIELD(status, 75 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 76 dev_err(adev->dev, "\t RW: 0x%lx\n", 77 REG_GET_FIELD(status, 78 MMVM_L2_PROTECTION_FAULT_STATUS, RW)); 79 } 80 81 static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev, 82 uint32_t vmid, 83 uint64_t page_table_base) 84 { 85 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 86 87 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 88 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); 89 90 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 91 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); 92 } 93 94 static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev) 95 { 96 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 97 98 mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base); 99 100 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 101 (u32)(adev->gmc.gart_start >> 12)); 102 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 103 (u32)(adev->gmc.gart_start >> 44)); 104 105 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 106 (u32)(adev->gmc.gart_end >> 12)); 107 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 108 (u32)(adev->gmc.gart_end >> 44)); 109 } 110 111 static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev) 112 { 113 uint64_t value; 114 uint32_t tmp; 115 116 /* Disable AGP. */ 117 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 118 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 119 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 120 121 /* Program the system aperture low logical page number. */ 122 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 123 adev->gmc.vram_start >> 18); 124 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 125 adev->gmc.vram_end >> 18); 126 127 /* Set default page address. */ 128 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 129 adev->vm_manager.vram_base_offset; 130 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 131 (u32)(value >> 12)); 132 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 133 (u32)(value >> 44)); 134 135 /* Program "protection fault". */ 136 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 137 (u32)(adev->dummy_page_addr >> 12)); 138 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 139 (u32)((u64)adev->dummy_page_addr >> 44)); 140 141 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 142 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 143 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 144 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 145 } 146 147 static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev) 148 { 149 uint32_t tmp; 150 151 /* Setup TLB control */ 152 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 153 154 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 155 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 156 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 157 ENABLE_ADVANCED_DRIVER_MODEL, 1); 158 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 159 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 160 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 161 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 162 MTYPE, MTYPE_UC); /* UC, uncached */ 163 164 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 165 } 166 167 static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev) 168 { 169 uint32_t tmp; 170 171 /* Setup L2 cache */ 172 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 173 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 174 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 175 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 176 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 177 /* XXX for emulation, Refer to closed source code.*/ 178 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 179 0); 180 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 181 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 182 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 183 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 184 185 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 186 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 187 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 188 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 189 190 tmp = mmMMVM_L2_CNTL3_DEFAULT; 191 if (adev->gmc.translate_further) { 192 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 193 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 194 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 195 } else { 196 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 197 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 198 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 199 } 200 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 201 202 tmp = mmMMVM_L2_CNTL4_DEFAULT; 203 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 204 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 205 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 206 207 tmp = mmMMVM_L2_CNTL5_DEFAULT; 208 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 209 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 210 } 211 212 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev) 213 { 214 uint32_t tmp; 215 216 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 217 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 218 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 219 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 220 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 221 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 222 } 223 224 static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev) 225 { 226 WREG32_SOC15(MMHUB, 0, 227 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 228 0xFFFFFFFF); 229 WREG32_SOC15(MMHUB, 0, 230 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 231 0x0000000F); 232 233 WREG32_SOC15(MMHUB, 0, 234 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 235 WREG32_SOC15(MMHUB, 0, 236 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 237 238 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 239 0); 240 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 241 0); 242 } 243 244 static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev) 245 { 246 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 247 int i; 248 uint32_t tmp; 249 250 for (i = 0; i <= 14; i++) { 251 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 252 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 253 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 254 adev->vm_manager.num_level); 255 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 256 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 257 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 258 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 259 1); 260 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 261 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 262 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 263 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 264 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 265 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 266 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 267 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 268 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 269 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 270 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 271 PAGE_TABLE_BLOCK_SIZE, 272 adev->vm_manager.block_size - 9); 273 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 274 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 275 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 276 !amdgpu_noretry); 277 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, 278 i * hub->ctx_distance, tmp); 279 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 280 i * hub->ctx_addr_distance, 0); 281 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 282 i * hub->ctx_addr_distance, 0); 283 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 284 i * hub->ctx_addr_distance, 285 lower_32_bits(adev->vm_manager.max_pfn - 1)); 286 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 287 i * hub->ctx_addr_distance, 288 upper_32_bits(adev->vm_manager.max_pfn - 1)); 289 } 290 } 291 292 static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev) 293 { 294 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 295 unsigned i; 296 297 for (i = 0; i < 18; ++i) { 298 WREG32_SOC15_OFFSET(MMHUB, 0, 299 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 300 i * hub->eng_addr_distance, 0xffffffff); 301 WREG32_SOC15_OFFSET(MMHUB, 0, 302 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 303 i * hub->eng_addr_distance, 0x1f); 304 } 305 } 306 307 static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev) 308 { 309 if (amdgpu_sriov_vf(adev)) { 310 /* 311 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 312 * VF copy registers so vbios post doesn't program them, for 313 * SRIOV driver need to program them 314 */ 315 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, 316 adev->gmc.vram_start >> 24); 317 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, 318 adev->gmc.vram_end >> 24); 319 } 320 321 /* GART Enable. */ 322 mmhub_v2_3_init_gart_aperture_regs(adev); 323 mmhub_v2_3_init_system_aperture_regs(adev); 324 mmhub_v2_3_init_tlb_regs(adev); 325 mmhub_v2_3_init_cache_regs(adev); 326 327 mmhub_v2_3_enable_system_domain(adev); 328 mmhub_v2_3_disable_identity_aperture(adev); 329 mmhub_v2_3_setup_vmid_config(adev); 330 mmhub_v2_3_program_invalidation(adev); 331 332 return 0; 333 } 334 335 static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev) 336 { 337 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 338 u32 tmp; 339 u32 i; 340 341 /* Disable all tables */ 342 for (i = 0; i < 16; i++) 343 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, 344 i * hub->ctx_distance, 0); 345 346 /* Setup TLB control */ 347 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 348 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 349 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 350 ENABLE_ADVANCED_DRIVER_MODEL, 0); 351 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 352 353 /* Setup L2 cache */ 354 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 355 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 356 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 357 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 358 } 359 360 /** 361 * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling 362 * 363 * @adev: amdgpu_device pointer 364 * @value: true redirects VM faults to the default page 365 */ 366 static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev, 367 bool value) 368 { 369 u32 tmp; 370 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 371 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 372 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 373 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 374 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 375 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 376 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 377 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 378 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 380 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 381 value); 382 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 383 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 384 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 385 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 387 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 389 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 391 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 393 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 if (!value) { 395 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 396 CRASH_ON_NO_RETRY_FAULT, 1); 397 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 398 CRASH_ON_RETRY_FAULT, 1); 399 } 400 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 401 } 402 403 static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = { 404 .print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status, 405 .get_invalidate_req = mmhub_v2_3_get_invalidate_req, 406 }; 407 408 static void mmhub_v2_3_init(struct amdgpu_device *adev) 409 { 410 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 411 412 hub->ctx0_ptb_addr_lo32 = 413 SOC15_REG_OFFSET(MMHUB, 0, 414 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 415 hub->ctx0_ptb_addr_hi32 = 416 SOC15_REG_OFFSET(MMHUB, 0, 417 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 418 hub->vm_inv_eng0_sem = 419 SOC15_REG_OFFSET(MMHUB, 0, 420 mmMMVM_INVALIDATE_ENG0_SEM); 421 hub->vm_inv_eng0_req = 422 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 423 hub->vm_inv_eng0_ack = 424 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 425 hub->vm_context0_cntl = 426 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 427 hub->vm_l2_pro_fault_status = 428 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 429 hub->vm_l2_pro_fault_cntl = 430 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 431 432 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL; 433 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 434 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 435 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ - 436 mmMMVM_INVALIDATE_ENG0_REQ; 437 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 438 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 439 440 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 441 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 442 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 443 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 444 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 445 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 446 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 447 448 hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs; 449 } 450 451 static void 452 mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 453 bool enable) 454 { 455 uint32_t def, data, def1, data1; 456 457 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 458 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 459 460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 461 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 462 463 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 464 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 465 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 466 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 467 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 468 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 469 470 } else { 471 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 472 473 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 474 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 475 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 476 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 477 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 478 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 479 } 480 481 if (def != data) 482 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 483 if (def1 != data1) 484 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 485 } 486 487 static void 488 mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 489 bool enable) 490 { 491 uint32_t def, data; 492 493 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 494 495 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 496 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 497 else 498 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 499 500 if (def != data) 501 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 502 } 503 504 static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev, 505 enum amd_clockgating_state state) 506 { 507 if (amdgpu_sriov_vf(adev)) 508 return 0; 509 510 mmhub_v2_3_update_medium_grain_clock_gating(adev, 511 state == AMD_CG_STATE_GATE ? true : false); 512 mmhub_v2_3_update_medium_grain_light_sleep(adev, 513 state == AMD_CG_STATE_GATE ? true : false); 514 515 return 0; 516 } 517 518 static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags) 519 { 520 int data, data1; 521 522 if (amdgpu_sriov_vf(adev)) 523 *flags = 0; 524 525 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 526 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 527 528 /* AMD_CG_SUPPORT_MC_MGCG */ 529 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 530 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 531 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 532 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 533 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 534 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 535 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 536 *flags |= AMD_CG_SUPPORT_MC_MGCG; 537 538 /* AMD_CG_SUPPORT_MC_LS */ 539 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 540 *flags |= AMD_CG_SUPPORT_MC_LS; 541 } 542 543 const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = { 544 .ras_late_init = amdgpu_mmhub_ras_late_init, 545 .init = mmhub_v2_3_init, 546 .gart_enable = mmhub_v2_3_gart_enable, 547 .set_fault_enable_default = mmhub_v2_3_set_fault_enable_default, 548 .gart_disable = mmhub_v2_3_gart_disable, 549 .set_clockgating = mmhub_v2_3_set_clockgating, 550 .get_clockgating = mmhub_v2_3_get_clockgating, 551 .setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs, 552 }; 553