1*4d8d75a4SHuang Rui /* 2*4d8d75a4SHuang Rui * Copyright 2019 Advanced Micro Devices, Inc. 3*4d8d75a4SHuang Rui * 4*4d8d75a4SHuang Rui * Permission is hereby granted, free of charge, to any person obtaining a 5*4d8d75a4SHuang Rui * copy of this software and associated documentation files (the "Software"), 6*4d8d75a4SHuang Rui * to deal in the Software without restriction, including without limitation 7*4d8d75a4SHuang Rui * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4d8d75a4SHuang Rui * and/or sell copies of the Software, and to permit persons to whom the 9*4d8d75a4SHuang Rui * Software is furnished to do so, subject to the following conditions: 10*4d8d75a4SHuang Rui * 11*4d8d75a4SHuang Rui * The above copyright notice and this permission notice shall be included in 12*4d8d75a4SHuang Rui * all copies or substantial portions of the Software. 13*4d8d75a4SHuang Rui * 14*4d8d75a4SHuang Rui * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4d8d75a4SHuang Rui * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4d8d75a4SHuang Rui * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4d8d75a4SHuang Rui * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4d8d75a4SHuang Rui * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4d8d75a4SHuang Rui * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4d8d75a4SHuang Rui * OTHER DEALINGS IN THE SOFTWARE. 21*4d8d75a4SHuang Rui * 22*4d8d75a4SHuang Rui */ 23*4d8d75a4SHuang Rui 24*4d8d75a4SHuang Rui #include "amdgpu.h" 25*4d8d75a4SHuang Rui #include "mmhub_v2_3.h" 26*4d8d75a4SHuang Rui 27*4d8d75a4SHuang Rui #include "mmhub/mmhub_2_3_0_offset.h" 28*4d8d75a4SHuang Rui #include "mmhub/mmhub_2_3_0_sh_mask.h" 29*4d8d75a4SHuang Rui #include "mmhub/mmhub_2_3_0_default.h" 30*4d8d75a4SHuang Rui #include "navi10_enum.h" 31*4d8d75a4SHuang Rui 32*4d8d75a4SHuang Rui #include "soc15_common.h" 33*4d8d75a4SHuang Rui 34*4d8d75a4SHuang Rui static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid, 35*4d8d75a4SHuang Rui uint32_t flush_type) 36*4d8d75a4SHuang Rui { 37*4d8d75a4SHuang Rui u32 req = 0; 38*4d8d75a4SHuang Rui 39*4d8d75a4SHuang Rui /* invalidate using legacy mode on vmid*/ 40*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 41*4d8d75a4SHuang Rui PER_VMID_INVALIDATE_REQ, 1 << vmid); 42*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 43*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 44*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 45*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 46*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 47*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 48*4d8d75a4SHuang Rui req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 49*4d8d75a4SHuang Rui CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 50*4d8d75a4SHuang Rui 51*4d8d75a4SHuang Rui return req; 52*4d8d75a4SHuang Rui } 53*4d8d75a4SHuang Rui 54*4d8d75a4SHuang Rui static void 55*4d8d75a4SHuang Rui mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 56*4d8d75a4SHuang Rui uint32_t status) 57*4d8d75a4SHuang Rui { 58*4d8d75a4SHuang Rui dev_err(adev->dev, 59*4d8d75a4SHuang Rui "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 60*4d8d75a4SHuang Rui status); 61*4d8d75a4SHuang Rui dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 62*4d8d75a4SHuang Rui REG_GET_FIELD(status, 63*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, CID)); 64*4d8d75a4SHuang Rui dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 65*4d8d75a4SHuang Rui REG_GET_FIELD(status, 66*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 67*4d8d75a4SHuang Rui dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 68*4d8d75a4SHuang Rui REG_GET_FIELD(status, 69*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 70*4d8d75a4SHuang Rui dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 71*4d8d75a4SHuang Rui REG_GET_FIELD(status, 72*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 73*4d8d75a4SHuang Rui dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 74*4d8d75a4SHuang Rui REG_GET_FIELD(status, 75*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 76*4d8d75a4SHuang Rui dev_err(adev->dev, "\t RW: 0x%lx\n", 77*4d8d75a4SHuang Rui REG_GET_FIELD(status, 78*4d8d75a4SHuang Rui MMVM_L2_PROTECTION_FAULT_STATUS, RW)); 79*4d8d75a4SHuang Rui } 80*4d8d75a4SHuang Rui 81*4d8d75a4SHuang Rui static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev, 82*4d8d75a4SHuang Rui uint32_t vmid, 83*4d8d75a4SHuang Rui uint64_t page_table_base) 84*4d8d75a4SHuang Rui { 85*4d8d75a4SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 86*4d8d75a4SHuang Rui 87*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 88*4d8d75a4SHuang Rui hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); 89*4d8d75a4SHuang Rui 90*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 91*4d8d75a4SHuang Rui hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); 92*4d8d75a4SHuang Rui } 93*4d8d75a4SHuang Rui 94*4d8d75a4SHuang Rui static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev) 95*4d8d75a4SHuang Rui { 96*4d8d75a4SHuang Rui uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 97*4d8d75a4SHuang Rui 98*4d8d75a4SHuang Rui mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base); 99*4d8d75a4SHuang Rui 100*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 101*4d8d75a4SHuang Rui (u32)(adev->gmc.gart_start >> 12)); 102*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 103*4d8d75a4SHuang Rui (u32)(adev->gmc.gart_start >> 44)); 104*4d8d75a4SHuang Rui 105*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 106*4d8d75a4SHuang Rui (u32)(adev->gmc.gart_end >> 12)); 107*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 108*4d8d75a4SHuang Rui (u32)(adev->gmc.gart_end >> 44)); 109*4d8d75a4SHuang Rui } 110*4d8d75a4SHuang Rui 111*4d8d75a4SHuang Rui static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev) 112*4d8d75a4SHuang Rui { 113*4d8d75a4SHuang Rui uint64_t value; 114*4d8d75a4SHuang Rui uint32_t tmp; 115*4d8d75a4SHuang Rui 116*4d8d75a4SHuang Rui /* Disable AGP. */ 117*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 118*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 119*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 120*4d8d75a4SHuang Rui 121*4d8d75a4SHuang Rui /* Program the system aperture low logical page number. */ 122*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 123*4d8d75a4SHuang Rui adev->gmc.vram_start >> 18); 124*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 125*4d8d75a4SHuang Rui adev->gmc.vram_end >> 18); 126*4d8d75a4SHuang Rui 127*4d8d75a4SHuang Rui /* Set default page address. */ 128*4d8d75a4SHuang Rui value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 129*4d8d75a4SHuang Rui adev->vm_manager.vram_base_offset; 130*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 131*4d8d75a4SHuang Rui (u32)(value >> 12)); 132*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 133*4d8d75a4SHuang Rui (u32)(value >> 44)); 134*4d8d75a4SHuang Rui 135*4d8d75a4SHuang Rui /* Program "protection fault". */ 136*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 137*4d8d75a4SHuang Rui (u32)(adev->dummy_page_addr >> 12)); 138*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 139*4d8d75a4SHuang Rui (u32)((u64)adev->dummy_page_addr >> 44)); 140*4d8d75a4SHuang Rui 141*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 142*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 143*4d8d75a4SHuang Rui ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 144*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 145*4d8d75a4SHuang Rui } 146*4d8d75a4SHuang Rui 147*4d8d75a4SHuang Rui static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev) 148*4d8d75a4SHuang Rui { 149*4d8d75a4SHuang Rui uint32_t tmp; 150*4d8d75a4SHuang Rui 151*4d8d75a4SHuang Rui /* Setup TLB control */ 152*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 153*4d8d75a4SHuang Rui 154*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 155*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 156*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 157*4d8d75a4SHuang Rui ENABLE_ADVANCED_DRIVER_MODEL, 1); 158*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 159*4d8d75a4SHuang Rui SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 160*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 161*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 162*4d8d75a4SHuang Rui MTYPE, MTYPE_UC); /* UC, uncached */ 163*4d8d75a4SHuang Rui 164*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 165*4d8d75a4SHuang Rui } 166*4d8d75a4SHuang Rui 167*4d8d75a4SHuang Rui static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev) 168*4d8d75a4SHuang Rui { 169*4d8d75a4SHuang Rui uint32_t tmp; 170*4d8d75a4SHuang Rui 171*4d8d75a4SHuang Rui /* Setup L2 cache */ 172*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 173*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 174*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 175*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 176*4d8d75a4SHuang Rui ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 177*4d8d75a4SHuang Rui /* XXX for emulation, Refer to closed source code.*/ 178*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 179*4d8d75a4SHuang Rui 0); 180*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 181*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 182*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 183*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 184*4d8d75a4SHuang Rui 185*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 186*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 187*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 188*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 189*4d8d75a4SHuang Rui 190*4d8d75a4SHuang Rui tmp = mmMMVM_L2_CNTL3_DEFAULT; 191*4d8d75a4SHuang Rui if (adev->gmc.translate_further) { 192*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 193*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 194*4d8d75a4SHuang Rui L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 195*4d8d75a4SHuang Rui } else { 196*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 197*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 198*4d8d75a4SHuang Rui L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 199*4d8d75a4SHuang Rui } 200*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 201*4d8d75a4SHuang Rui 202*4d8d75a4SHuang Rui tmp = mmMMVM_L2_CNTL4_DEFAULT; 203*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 204*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 205*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 206*4d8d75a4SHuang Rui 207*4d8d75a4SHuang Rui tmp = mmMMVM_L2_CNTL5_DEFAULT; 208*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 209*4d8d75a4SHuang Rui WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 210*4d8d75a4SHuang Rui } 211*4d8d75a4SHuang Rui 212*4d8d75a4SHuang Rui static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev) 213*4d8d75a4SHuang Rui { 214*4d8d75a4SHuang Rui uint32_t tmp; 215*4d8d75a4SHuang Rui 216*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 217*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 218*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 219*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 220*4d8d75a4SHuang Rui RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 221*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 222*4d8d75a4SHuang Rui } 223*4d8d75a4SHuang Rui 224*4d8d75a4SHuang Rui static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev) 225*4d8d75a4SHuang Rui { 226*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, 227*4d8d75a4SHuang Rui mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 228*4d8d75a4SHuang Rui 0xFFFFFFFF); 229*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, 230*4d8d75a4SHuang Rui mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 231*4d8d75a4SHuang Rui 0x0000000F); 232*4d8d75a4SHuang Rui 233*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, 234*4d8d75a4SHuang Rui mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 235*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, 236*4d8d75a4SHuang Rui mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 237*4d8d75a4SHuang Rui 238*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 239*4d8d75a4SHuang Rui 0); 240*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 241*4d8d75a4SHuang Rui 0); 242*4d8d75a4SHuang Rui } 243*4d8d75a4SHuang Rui 244*4d8d75a4SHuang Rui static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev) 245*4d8d75a4SHuang Rui { 246*4d8d75a4SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 247*4d8d75a4SHuang Rui int i; 248*4d8d75a4SHuang Rui uint32_t tmp; 249*4d8d75a4SHuang Rui 250*4d8d75a4SHuang Rui for (i = 0; i <= 14; i++) { 251*4d8d75a4SHuang Rui tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 252*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 253*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 254*4d8d75a4SHuang Rui adev->vm_manager.num_level); 255*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 256*4d8d75a4SHuang Rui RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 257*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 258*4d8d75a4SHuang Rui DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 259*4d8d75a4SHuang Rui 1); 260*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 261*4d8d75a4SHuang Rui PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 262*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 263*4d8d75a4SHuang Rui VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 264*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 265*4d8d75a4SHuang Rui READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 266*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 267*4d8d75a4SHuang Rui WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 268*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 269*4d8d75a4SHuang Rui EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 270*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 271*4d8d75a4SHuang Rui PAGE_TABLE_BLOCK_SIZE, 272*4d8d75a4SHuang Rui adev->vm_manager.block_size - 9); 273*4d8d75a4SHuang Rui /* Send no-retry XNACK on fault to suppress VM fault storm. */ 274*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 275*4d8d75a4SHuang Rui RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 276*4d8d75a4SHuang Rui !amdgpu_noretry); 277*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, 278*4d8d75a4SHuang Rui i * hub->ctx_distance, tmp); 279*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 280*4d8d75a4SHuang Rui i * hub->ctx_addr_distance, 0); 281*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 282*4d8d75a4SHuang Rui i * hub->ctx_addr_distance, 0); 283*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 284*4d8d75a4SHuang Rui i * hub->ctx_addr_distance, 285*4d8d75a4SHuang Rui lower_32_bits(adev->vm_manager.max_pfn - 1)); 286*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 287*4d8d75a4SHuang Rui i * hub->ctx_addr_distance, 288*4d8d75a4SHuang Rui upper_32_bits(adev->vm_manager.max_pfn - 1)); 289*4d8d75a4SHuang Rui } 290*4d8d75a4SHuang Rui } 291*4d8d75a4SHuang Rui 292*4d8d75a4SHuang Rui static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev) 293*4d8d75a4SHuang Rui { 294*4d8d75a4SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 295*4d8d75a4SHuang Rui unsigned i; 296*4d8d75a4SHuang Rui 297*4d8d75a4SHuang Rui for (i = 0; i < 18; ++i) { 298*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, 299*4d8d75a4SHuang Rui mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 300*4d8d75a4SHuang Rui i * hub->eng_addr_distance, 0xffffffff); 301*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, 302*4d8d75a4SHuang Rui mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 303*4d8d75a4SHuang Rui i * hub->eng_addr_distance, 0x1f); 304*4d8d75a4SHuang Rui } 305*4d8d75a4SHuang Rui } 306*4d8d75a4SHuang Rui 307*4d8d75a4SHuang Rui static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev) 308*4d8d75a4SHuang Rui { 309*4d8d75a4SHuang Rui if (amdgpu_sriov_vf(adev)) { 310*4d8d75a4SHuang Rui /* 311*4d8d75a4SHuang Rui * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 312*4d8d75a4SHuang Rui * VF copy registers so vbios post doesn't program them, for 313*4d8d75a4SHuang Rui * SRIOV driver need to program them 314*4d8d75a4SHuang Rui */ 315*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, 316*4d8d75a4SHuang Rui adev->gmc.vram_start >> 24); 317*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, 318*4d8d75a4SHuang Rui adev->gmc.vram_end >> 24); 319*4d8d75a4SHuang Rui } 320*4d8d75a4SHuang Rui 321*4d8d75a4SHuang Rui /* GART Enable. */ 322*4d8d75a4SHuang Rui mmhub_v2_3_init_gart_aperture_regs(adev); 323*4d8d75a4SHuang Rui mmhub_v2_3_init_system_aperture_regs(adev); 324*4d8d75a4SHuang Rui mmhub_v2_3_init_tlb_regs(adev); 325*4d8d75a4SHuang Rui mmhub_v2_3_init_cache_regs(adev); 326*4d8d75a4SHuang Rui 327*4d8d75a4SHuang Rui mmhub_v2_3_enable_system_domain(adev); 328*4d8d75a4SHuang Rui mmhub_v2_3_disable_identity_aperture(adev); 329*4d8d75a4SHuang Rui mmhub_v2_3_setup_vmid_config(adev); 330*4d8d75a4SHuang Rui mmhub_v2_3_program_invalidation(adev); 331*4d8d75a4SHuang Rui 332*4d8d75a4SHuang Rui return 0; 333*4d8d75a4SHuang Rui } 334*4d8d75a4SHuang Rui 335*4d8d75a4SHuang Rui static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev) 336*4d8d75a4SHuang Rui { 337*4d8d75a4SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 338*4d8d75a4SHuang Rui u32 tmp; 339*4d8d75a4SHuang Rui u32 i; 340*4d8d75a4SHuang Rui 341*4d8d75a4SHuang Rui /* Disable all tables */ 342*4d8d75a4SHuang Rui for (i = 0; i < 16; i++) 343*4d8d75a4SHuang Rui WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, 344*4d8d75a4SHuang Rui i * hub->ctx_distance, 0); 345*4d8d75a4SHuang Rui 346*4d8d75a4SHuang Rui /* Setup TLB control */ 347*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 348*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 349*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 350*4d8d75a4SHuang Rui ENABLE_ADVANCED_DRIVER_MODEL, 0); 351*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 352*4d8d75a4SHuang Rui 353*4d8d75a4SHuang Rui /* Setup L2 cache */ 354*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 355*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 356*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 357*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 358*4d8d75a4SHuang Rui } 359*4d8d75a4SHuang Rui 360*4d8d75a4SHuang Rui /** 361*4d8d75a4SHuang Rui * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling 362*4d8d75a4SHuang Rui * 363*4d8d75a4SHuang Rui * @adev: amdgpu_device pointer 364*4d8d75a4SHuang Rui * @value: true redirects VM faults to the default page 365*4d8d75a4SHuang Rui */ 366*4d8d75a4SHuang Rui static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev, 367*4d8d75a4SHuang Rui bool value) 368*4d8d75a4SHuang Rui { 369*4d8d75a4SHuang Rui u32 tmp; 370*4d8d75a4SHuang Rui tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 371*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 372*4d8d75a4SHuang Rui RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 373*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 374*4d8d75a4SHuang Rui PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 375*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 376*4d8d75a4SHuang Rui PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 377*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 378*4d8d75a4SHuang Rui PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 380*4d8d75a4SHuang Rui TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 381*4d8d75a4SHuang Rui value); 382*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 383*4d8d75a4SHuang Rui NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 384*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 385*4d8d75a4SHuang Rui DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 387*4d8d75a4SHuang Rui VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 389*4d8d75a4SHuang Rui READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 391*4d8d75a4SHuang Rui WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 393*4d8d75a4SHuang Rui EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394*4d8d75a4SHuang Rui if (!value) { 395*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 396*4d8d75a4SHuang Rui CRASH_ON_NO_RETRY_FAULT, 1); 397*4d8d75a4SHuang Rui tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 398*4d8d75a4SHuang Rui CRASH_ON_RETRY_FAULT, 1); 399*4d8d75a4SHuang Rui } 400*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 401*4d8d75a4SHuang Rui } 402*4d8d75a4SHuang Rui 403*4d8d75a4SHuang Rui static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = { 404*4d8d75a4SHuang Rui .print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status, 405*4d8d75a4SHuang Rui .get_invalidate_req = mmhub_v2_3_get_invalidate_req, 406*4d8d75a4SHuang Rui }; 407*4d8d75a4SHuang Rui 408*4d8d75a4SHuang Rui static void mmhub_v2_3_init(struct amdgpu_device *adev) 409*4d8d75a4SHuang Rui { 410*4d8d75a4SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 411*4d8d75a4SHuang Rui 412*4d8d75a4SHuang Rui hub->ctx0_ptb_addr_lo32 = 413*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, 414*4d8d75a4SHuang Rui mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 415*4d8d75a4SHuang Rui hub->ctx0_ptb_addr_hi32 = 416*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, 417*4d8d75a4SHuang Rui mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 418*4d8d75a4SHuang Rui hub->vm_inv_eng0_sem = 419*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, 420*4d8d75a4SHuang Rui mmMMVM_INVALIDATE_ENG0_SEM); 421*4d8d75a4SHuang Rui hub->vm_inv_eng0_req = 422*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 423*4d8d75a4SHuang Rui hub->vm_inv_eng0_ack = 424*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 425*4d8d75a4SHuang Rui hub->vm_context0_cntl = 426*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 427*4d8d75a4SHuang Rui hub->vm_l2_pro_fault_status = 428*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 429*4d8d75a4SHuang Rui hub->vm_l2_pro_fault_cntl = 430*4d8d75a4SHuang Rui SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 431*4d8d75a4SHuang Rui 432*4d8d75a4SHuang Rui hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL; 433*4d8d75a4SHuang Rui hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 434*4d8d75a4SHuang Rui mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 435*4d8d75a4SHuang Rui hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ - 436*4d8d75a4SHuang Rui mmMMVM_INVALIDATE_ENG0_REQ; 437*4d8d75a4SHuang Rui hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 438*4d8d75a4SHuang Rui mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 439*4d8d75a4SHuang Rui 440*4d8d75a4SHuang Rui hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 441*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 442*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 443*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 444*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 445*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 446*4d8d75a4SHuang Rui MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 447*4d8d75a4SHuang Rui 448*4d8d75a4SHuang Rui hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs; 449*4d8d75a4SHuang Rui } 450*4d8d75a4SHuang Rui 451*4d8d75a4SHuang Rui static void 452*4d8d75a4SHuang Rui mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 453*4d8d75a4SHuang Rui bool enable) 454*4d8d75a4SHuang Rui { 455*4d8d75a4SHuang Rui uint32_t def, data, def1, data1; 456*4d8d75a4SHuang Rui 457*4d8d75a4SHuang Rui def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 458*4d8d75a4SHuang Rui def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 459*4d8d75a4SHuang Rui 460*4d8d75a4SHuang Rui if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 461*4d8d75a4SHuang Rui data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 462*4d8d75a4SHuang Rui 463*4d8d75a4SHuang Rui data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 464*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 465*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 466*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 467*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 468*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 469*4d8d75a4SHuang Rui 470*4d8d75a4SHuang Rui } else { 471*4d8d75a4SHuang Rui data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 472*4d8d75a4SHuang Rui 473*4d8d75a4SHuang Rui data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 474*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 475*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 476*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 477*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 478*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 479*4d8d75a4SHuang Rui } 480*4d8d75a4SHuang Rui 481*4d8d75a4SHuang Rui if (def != data) 482*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 483*4d8d75a4SHuang Rui if (def1 != data1) 484*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 485*4d8d75a4SHuang Rui } 486*4d8d75a4SHuang Rui 487*4d8d75a4SHuang Rui static void 488*4d8d75a4SHuang Rui mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 489*4d8d75a4SHuang Rui bool enable) 490*4d8d75a4SHuang Rui { 491*4d8d75a4SHuang Rui uint32_t def, data; 492*4d8d75a4SHuang Rui 493*4d8d75a4SHuang Rui def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 494*4d8d75a4SHuang Rui 495*4d8d75a4SHuang Rui if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 496*4d8d75a4SHuang Rui data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 497*4d8d75a4SHuang Rui else 498*4d8d75a4SHuang Rui data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 499*4d8d75a4SHuang Rui 500*4d8d75a4SHuang Rui if (def != data) 501*4d8d75a4SHuang Rui WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 502*4d8d75a4SHuang Rui } 503*4d8d75a4SHuang Rui 504*4d8d75a4SHuang Rui static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev, 505*4d8d75a4SHuang Rui enum amd_clockgating_state state) 506*4d8d75a4SHuang Rui { 507*4d8d75a4SHuang Rui if (amdgpu_sriov_vf(adev)) 508*4d8d75a4SHuang Rui return 0; 509*4d8d75a4SHuang Rui 510*4d8d75a4SHuang Rui mmhub_v2_3_update_medium_grain_clock_gating(adev, 511*4d8d75a4SHuang Rui state == AMD_CG_STATE_GATE ? true : false); 512*4d8d75a4SHuang Rui mmhub_v2_3_update_medium_grain_light_sleep(adev, 513*4d8d75a4SHuang Rui state == AMD_CG_STATE_GATE ? true : false); 514*4d8d75a4SHuang Rui 515*4d8d75a4SHuang Rui return 0; 516*4d8d75a4SHuang Rui } 517*4d8d75a4SHuang Rui 518*4d8d75a4SHuang Rui static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags) 519*4d8d75a4SHuang Rui { 520*4d8d75a4SHuang Rui int data, data1; 521*4d8d75a4SHuang Rui 522*4d8d75a4SHuang Rui if (amdgpu_sriov_vf(adev)) 523*4d8d75a4SHuang Rui *flags = 0; 524*4d8d75a4SHuang Rui 525*4d8d75a4SHuang Rui data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 526*4d8d75a4SHuang Rui data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 527*4d8d75a4SHuang Rui 528*4d8d75a4SHuang Rui /* AMD_CG_SUPPORT_MC_MGCG */ 529*4d8d75a4SHuang Rui if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 530*4d8d75a4SHuang Rui !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 531*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 532*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 533*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 534*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 535*4d8d75a4SHuang Rui DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 536*4d8d75a4SHuang Rui *flags |= AMD_CG_SUPPORT_MC_MGCG; 537*4d8d75a4SHuang Rui 538*4d8d75a4SHuang Rui /* AMD_CG_SUPPORT_MC_LS */ 539*4d8d75a4SHuang Rui if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 540*4d8d75a4SHuang Rui *flags |= AMD_CG_SUPPORT_MC_LS; 541*4d8d75a4SHuang Rui } 542*4d8d75a4SHuang Rui 543*4d8d75a4SHuang Rui const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = { 544*4d8d75a4SHuang Rui .ras_late_init = amdgpu_mmhub_ras_late_init, 545*4d8d75a4SHuang Rui .init = mmhub_v2_3_init, 546*4d8d75a4SHuang Rui .gart_enable = mmhub_v2_3_gart_enable, 547*4d8d75a4SHuang Rui .set_fault_enable_default = mmhub_v2_3_set_fault_enable_default, 548*4d8d75a4SHuang Rui .gart_disable = mmhub_v2_3_gart_disable, 549*4d8d75a4SHuang Rui .set_clockgating = mmhub_v2_3_set_clockgating, 550*4d8d75a4SHuang Rui .get_clockgating = mmhub_v2_3_get_clockgating, 551*4d8d75a4SHuang Rui .setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs, 552*4d8d75a4SHuang Rui }; 553