1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev) 35 { 36 uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); 37 38 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 39 lower_32_bits(value)); 40 41 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 42 upper_32_bits(value)); 43 } 44 45 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 46 { 47 mmhub_v2_0_init_gart_pt_regs(adev); 48 49 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 50 (u32)(adev->gmc.gart_start >> 12)); 51 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 52 (u32)(adev->gmc.gart_start >> 44)); 53 54 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 55 (u32)(adev->gmc.gart_end >> 12)); 56 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 57 (u32)(adev->gmc.gart_end >> 44)); 58 } 59 60 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 61 { 62 uint64_t value; 63 uint32_t tmp; 64 65 /* Disable AGP. */ 66 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 67 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 68 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 69 70 /* Program the system aperture low logical page number. */ 71 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 72 adev->gmc.vram_start >> 18); 73 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 74 adev->gmc.vram_end >> 18); 75 76 /* Set default page address. */ 77 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 78 adev->vm_manager.vram_base_offset; 79 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 80 (u32)(value >> 12)); 81 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 82 (u32)(value >> 44)); 83 84 /* Program "protection fault". */ 85 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 86 (u32)(adev->dummy_page_addr >> 12)); 87 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 88 (u32)((u64)adev->dummy_page_addr >> 44)); 89 90 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 91 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 92 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 93 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 94 } 95 96 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 97 { 98 uint32_t tmp; 99 100 /* Setup TLB control */ 101 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 102 103 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 104 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 105 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 106 ENABLE_ADVANCED_DRIVER_MODEL, 1); 107 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 108 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 109 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 110 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 111 MTYPE, MTYPE_UC); /* UC, uncached */ 112 113 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 114 } 115 116 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 117 { 118 uint32_t tmp; 119 120 /* Setup L2 cache */ 121 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 122 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 123 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 124 /* XXX for emulation, Refer to closed source code.*/ 125 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 126 0); 127 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 128 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 129 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 130 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 131 132 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 133 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 134 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 135 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 136 137 tmp = mmMMVM_L2_CNTL3_DEFAULT; 138 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 139 140 tmp = mmMMVM_L2_CNTL4_DEFAULT; 141 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 142 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 143 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 144 } 145 146 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 147 { 148 uint32_t tmp; 149 150 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 151 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 152 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 153 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 154 } 155 156 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 157 { 158 WREG32_SOC15(MMHUB, 0, 159 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 160 0xFFFFFFFF); 161 WREG32_SOC15(MMHUB, 0, 162 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 163 0x0000000F); 164 165 WREG32_SOC15(MMHUB, 0, 166 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 167 WREG32_SOC15(MMHUB, 0, 168 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 169 170 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 171 0); 172 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 173 0); 174 } 175 176 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 177 { 178 int i; 179 uint32_t tmp; 180 181 for (i = 0; i <= 14; i++) { 182 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 183 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 184 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 185 adev->vm_manager.num_level); 186 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 187 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 188 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 189 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 190 1); 191 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 192 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 193 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 194 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 195 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 196 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 197 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 198 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 199 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 200 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 201 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 202 PAGE_TABLE_BLOCK_SIZE, 203 adev->vm_manager.block_size - 9); 204 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 205 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 206 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 207 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); 208 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 209 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 210 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 211 lower_32_bits(adev->vm_manager.max_pfn - 1)); 212 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 213 upper_32_bits(adev->vm_manager.max_pfn - 1)); 214 } 215 } 216 217 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 218 { 219 unsigned i; 220 221 for (i = 0; i < 18; ++i) { 222 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 223 2 * i, 0xffffffff); 224 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 225 2 * i, 0x1f); 226 } 227 } 228 229 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 230 { 231 if (amdgpu_sriov_vf(adev)) { 232 /* 233 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 234 * VF copy registers so vbios post doesn't program them, for 235 * SRIOV driver need to program them 236 */ 237 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, 238 adev->gmc.vram_start >> 24); 239 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, 240 adev->gmc.vram_end >> 24); 241 } 242 243 /* GART Enable. */ 244 mmhub_v2_0_init_gart_aperture_regs(adev); 245 mmhub_v2_0_init_system_aperture_regs(adev); 246 mmhub_v2_0_init_tlb_regs(adev); 247 mmhub_v2_0_init_cache_regs(adev); 248 249 mmhub_v2_0_enable_system_domain(adev); 250 mmhub_v2_0_disable_identity_aperture(adev); 251 mmhub_v2_0_setup_vmid_config(adev); 252 mmhub_v2_0_program_invalidation(adev); 253 254 return 0; 255 } 256 257 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 258 { 259 u32 tmp; 260 u32 i; 261 262 /* Disable all tables */ 263 for (i = 0; i < 16; i++) 264 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0); 265 266 /* Setup TLB control */ 267 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 268 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 269 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 270 ENABLE_ADVANCED_DRIVER_MODEL, 0); 271 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 272 273 /* Setup L2 cache */ 274 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 275 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 276 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 277 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 278 } 279 280 /** 281 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 282 * 283 * @adev: amdgpu_device pointer 284 * @value: true redirects VM faults to the default page 285 */ 286 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 287 { 288 u32 tmp; 289 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 290 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 291 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 292 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 293 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 294 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 295 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 296 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 297 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 298 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 299 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 300 value); 301 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 302 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 303 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 304 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 305 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 306 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 307 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 308 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 309 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 310 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 311 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 312 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313 if (!value) { 314 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 315 CRASH_ON_NO_RETRY_FAULT, 1); 316 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 317 CRASH_ON_RETRY_FAULT, 1); 318 } 319 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 320 } 321 322 void mmhub_v2_0_init(struct amdgpu_device *adev) 323 { 324 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 325 326 hub->ctx0_ptb_addr_lo32 = 327 SOC15_REG_OFFSET(MMHUB, 0, 328 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 329 hub->ctx0_ptb_addr_hi32 = 330 SOC15_REG_OFFSET(MMHUB, 0, 331 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 332 hub->vm_inv_eng0_req = 333 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 334 hub->vm_inv_eng0_ack = 335 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 336 hub->vm_context0_cntl = 337 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 338 hub->vm_l2_pro_fault_status = 339 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 340 hub->vm_l2_pro_fault_cntl = 341 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 342 343 } 344 345 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 346 bool enable) 347 { 348 uint32_t def, data, def1, data1; 349 350 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 351 352 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 353 354 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 355 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 356 357 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 358 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 359 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 360 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 361 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 362 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 363 364 } else { 365 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 366 367 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 368 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 369 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 370 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 371 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 372 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 373 } 374 375 if (def != data) 376 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 377 378 if (def1 != data1) 379 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 380 } 381 382 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 383 bool enable) 384 { 385 uint32_t def, data; 386 387 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 388 389 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 390 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 391 else 392 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 393 394 if (def != data) 395 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 396 } 397 398 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 399 enum amd_clockgating_state state) 400 { 401 if (amdgpu_sriov_vf(adev)) 402 return 0; 403 404 switch (adev->asic_type) { 405 case CHIP_NAVI10: 406 mmhub_v2_0_update_medium_grain_clock_gating(adev, 407 state == AMD_CG_STATE_GATE ? true : false); 408 mmhub_v2_0_update_medium_grain_light_sleep(adev, 409 state == AMD_CG_STATE_GATE ? true : false); 410 break; 411 default: 412 break; 413 } 414 415 return 0; 416 } 417 418 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 419 { 420 int data, data1; 421 422 if (amdgpu_sriov_vf(adev)) 423 *flags = 0; 424 425 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 426 427 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 428 429 /* AMD_CG_SUPPORT_MC_MGCG */ 430 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 431 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 432 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 433 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 434 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 435 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 436 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 437 *flags |= AMD_CG_SUPPORT_MC_MGCG; 438 439 /* AMD_CG_SUPPORT_MC_LS */ 440 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 441 *flags |= AMD_CG_SUPPORT_MC_LS; 442 } 443