1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu.h"
25 #include "mmhub_v2_0.h"
26 
27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
30 #include "navi10_enum.h"
31 
32 #include "gc/gc_10_1_0_offset.h"
33 #include "soc15_common.h"
34 
35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
36 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX             0
37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid                       0x0070
38 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX              0
39 
40 static const char *mmhub_client_ids_navi1x[][2] = {
41 	[3][0] = "DCEDMC",
42 	[4][0] = "DCEVGA",
43 	[5][0] = "MP0",
44 	[6][0] = "MP1",
45 	[13][0] = "VMC",
46 	[14][0] = "HDP",
47 	[15][0] = "OSS",
48 	[16][0] = "VCNU",
49 	[17][0] = "JPEG",
50 	[18][0] = "VCN",
51 	[3][1] = "DCEDMC",
52 	[4][1] = "DCEXFC",
53 	[5][1] = "DCEVGA",
54 	[6][1] = "DCEDWB",
55 	[7][1] = "MP0",
56 	[8][1] = "MP1",
57 	[9][1] = "DBGU1",
58 	[10][1] = "DBGU0",
59 	[11][1] = "XDP",
60 	[14][1] = "HDP",
61 	[15][1] = "OSS",
62 	[16][1] = "VCNU",
63 	[17][1] = "JPEG",
64 	[18][1] = "VCN",
65 };
66 
67 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
68 	[3][0] = "DCEDMC",
69 	[4][0] = "DCEVGA",
70 	[5][0] = "MP0",
71 	[6][0] = "MP1",
72 	[8][0] = "VMC",
73 	[9][0] = "VCNU0",
74 	[10][0] = "JPEG",
75 	[12][0] = "VCNU1",
76 	[13][0] = "VCN1",
77 	[14][0] = "HDP",
78 	[15][0] = "OSS",
79 	[32+11][0] = "VCN0",
80 	[0][1] = "DBGU0",
81 	[1][1] = "DBGU1",
82 	[2][1] = "DCEDWB",
83 	[3][1] = "DCEDMC",
84 	[4][1] = "DCEVGA",
85 	[5][1] = "MP0",
86 	[6][1] = "MP1",
87 	[7][1] = "XDP",
88 	[9][1] = "VCNU0",
89 	[10][1] = "JPEG",
90 	[11][1] = "VCN0",
91 	[12][1] = "VCNU1",
92 	[13][1] = "VCN1",
93 	[14][1] = "HDP",
94 	[15][1] = "OSS",
95 };
96 
97 static const char *mmhub_client_ids_beige_goby[][2] = {
98 	[3][0] = "DCEDMC",
99 	[4][0] = "DCEVGA",
100 	[5][0] = "MP0",
101 	[6][0] = "MP1",
102 	[8][0] = "VMC",
103 	[9][0] = "VCNU0",
104 	[11][0] = "VCN0",
105 	[14][0] = "HDP",
106 	[15][0] = "OSS",
107 	[0][1] = "DBGU0",
108 	[1][1] = "DBGU1",
109 	[2][1] = "DCEDWB",
110 	[3][1] = "DCEDMC",
111 	[4][1] = "DCEVGA",
112 	[5][1] = "MP0",
113 	[6][1] = "MP1",
114 	[7][1] = "XDP",
115 	[9][1] = "VCNU0",
116 	[11][1] = "VCN0",
117 	[14][1] = "HDP",
118 	[15][1] = "OSS",
119 };
120 
121 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
122 					      uint32_t flush_type)
123 {
124 	u32 req = 0;
125 
126 	/* invalidate using legacy mode on vmid*/
127 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
128 			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
129 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
130 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
131 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
132 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
133 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
134 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
135 	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
136 			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
137 
138 	return req;
139 }
140 
141 static void
142 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
143 					     uint32_t status)
144 {
145 	uint32_t cid, rw;
146 	const char *mmhub_cid = NULL;
147 
148 	cid = REG_GET_FIELD(status,
149 			    MMVM_L2_PROTECTION_FAULT_STATUS, CID);
150 	rw = REG_GET_FIELD(status,
151 			   MMVM_L2_PROTECTION_FAULT_STATUS, RW);
152 
153 	dev_err(adev->dev,
154 		"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
155 		status);
156 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
157 	case IP_VERSION(2, 0, 0):
158 	case IP_VERSION(2, 0, 2):
159 		mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
160 		break;
161 	case IP_VERSION(2, 1, 0):
162 	case IP_VERSION(2, 1, 1):
163 		mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
164 		break;
165 	case IP_VERSION(2, 1, 2):
166 		mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
167 		break;
168 	default:
169 		mmhub_cid = NULL;
170 		break;
171 	}
172 	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
173 		mmhub_cid ? mmhub_cid : "unknown", cid);
174 	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
175 		REG_GET_FIELD(status,
176 		MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
177 	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
178 		REG_GET_FIELD(status,
179 		MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
180 	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
181 		REG_GET_FIELD(status,
182 		MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
183 	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
184 		REG_GET_FIELD(status,
185 		MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
186 	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
187 }
188 
189 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
190 				uint64_t page_table_base)
191 {
192 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
193 
194 	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
195 			    hub->ctx_addr_distance * vmid,
196 			    lower_32_bits(page_table_base));
197 
198 	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
199 			    hub->ctx_addr_distance * vmid,
200 			    upper_32_bits(page_table_base));
201 }
202 
203 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
204 {
205 	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
206 
207 	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
208 
209 	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
210 		     (u32)(adev->gmc.gart_start >> 12));
211 	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
212 		     (u32)(adev->gmc.gart_start >> 44));
213 
214 	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
215 		     (u32)(adev->gmc.gart_end >> 12));
216 	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
217 		     (u32)(adev->gmc.gart_end >> 44));
218 }
219 
220 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
221 {
222 	uint64_t value;
223 	uint32_t tmp;
224 
225 	if (!amdgpu_sriov_vf(adev)) {
226 		/* Program the AGP BAR */
227 		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
228 		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
229 		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
230 
231 		/* Program the system aperture low logical page number. */
232 		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
233 			     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
234 		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
235 			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
236 	}
237 
238 	/* Set default page address. */
239 	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
240 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
241 		     (u32)(value >> 12));
242 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
243 		     (u32)(value >> 44));
244 
245 	/* Program "protection fault". */
246 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
247 		     (u32)(adev->dummy_page_addr >> 12));
248 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
249 		     (u32)((u64)adev->dummy_page_addr >> 44));
250 
251 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
252 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
253 			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
254 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
255 }
256 
257 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
258 {
259 	uint32_t tmp;
260 
261 	/* Setup TLB control */
262 	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
263 
264 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
265 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
266 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
267 			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
268 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
269 			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
270 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
271 			    MTYPE, MTYPE_UC); /* UC, uncached */
272 
273 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
274 }
275 
276 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
277 {
278 	uint32_t tmp;
279 
280 	/* These registers are not accessible to VF-SRIOV.
281 	 * The PF will program them instead.
282 	 */
283 	if (amdgpu_sriov_vf(adev))
284 		return;
285 
286 	/* Setup L2 cache */
287 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
288 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
289 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
290 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
291 			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
292 	/* XXX for emulation, Refer to closed source code.*/
293 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
294 			    0);
295 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
296 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
297 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
298 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
299 
300 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
301 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
302 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
303 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
304 
305 	tmp = mmMMVM_L2_CNTL3_DEFAULT;
306 	if (adev->gmc.translate_further) {
307 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
308 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
309 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
310 	} else {
311 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
312 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
313 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
314 	}
315 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
316 
317 	tmp = mmMMVM_L2_CNTL4_DEFAULT;
318 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
319 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
320 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
321 
322 	tmp = mmMMVM_L2_CNTL5_DEFAULT;
323 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
324 	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
325 }
326 
327 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
328 {
329 	uint32_t tmp;
330 
331 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
332 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
333 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
334 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
335 			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
336 	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
337 }
338 
339 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
340 {
341 	/* These registers are not accessible to VF-SRIOV.
342 	 * The PF will program them instead.
343 	 */
344 	if (amdgpu_sriov_vf(adev))
345 		return;
346 
347 	WREG32_SOC15(MMHUB, 0,
348 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
349 		     0xFFFFFFFF);
350 	WREG32_SOC15(MMHUB, 0,
351 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
352 		     0x0000000F);
353 
354 	WREG32_SOC15(MMHUB, 0,
355 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
356 	WREG32_SOC15(MMHUB, 0,
357 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
358 
359 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
360 		     0);
361 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
362 		     0);
363 }
364 
365 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
366 {
367 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
368 	int i;
369 	uint32_t tmp;
370 
371 	for (i = 0; i <= 14; i++) {
372 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
373 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
374 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
375 				    adev->vm_manager.num_level);
376 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
377 				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
378 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
379 				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
380 				    1);
381 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
382 				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
383 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
384 				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
385 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
386 				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
387 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
388 				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
389 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
390 				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
391 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
392 				    PAGE_TABLE_BLOCK_SIZE,
393 				    adev->vm_manager.block_size - 9);
394 		/* Send no-retry XNACK on fault to suppress VM fault storm. */
395 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
396 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
397 				    !adev->gmc.noretry);
398 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
399 				    i * hub->ctx_distance, tmp);
400 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
401 				    i * hub->ctx_addr_distance, 0);
402 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
403 				    i * hub->ctx_addr_distance, 0);
404 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
405 				    i * hub->ctx_addr_distance,
406 				    lower_32_bits(adev->vm_manager.max_pfn - 1));
407 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
408 				    i * hub->ctx_addr_distance,
409 				    upper_32_bits(adev->vm_manager.max_pfn - 1));
410 	}
411 
412 	hub->vm_cntx_cntl = tmp;
413 }
414 
415 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
416 {
417 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
418 	unsigned i;
419 
420 	for (i = 0; i < 18; ++i) {
421 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
422 				    i * hub->eng_addr_distance, 0xffffffff);
423 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
424 				    i * hub->eng_addr_distance, 0x1f);
425 	}
426 }
427 
428 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
429 {
430 	/* GART Enable. */
431 	mmhub_v2_0_init_gart_aperture_regs(adev);
432 	mmhub_v2_0_init_system_aperture_regs(adev);
433 	mmhub_v2_0_init_tlb_regs(adev);
434 	mmhub_v2_0_init_cache_regs(adev);
435 
436 	mmhub_v2_0_enable_system_domain(adev);
437 	mmhub_v2_0_disable_identity_aperture(adev);
438 	mmhub_v2_0_setup_vmid_config(adev);
439 	mmhub_v2_0_program_invalidation(adev);
440 
441 	return 0;
442 }
443 
444 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
445 {
446 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
447 	u32 tmp;
448 	u32 i;
449 
450 	/* Disable all tables */
451 	for (i = 0; i < AMDGPU_NUM_VMID; i++)
452 		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
453 				    i * hub->ctx_distance, 0);
454 
455 	/* Setup TLB control */
456 	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
457 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
458 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
459 			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
460 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
461 
462 	/* Setup L2 cache */
463 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
464 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
465 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
466 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
467 }
468 
469 /**
470  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
471  *
472  * @adev: amdgpu_device pointer
473  * @value: true redirects VM faults to the default page
474  */
475 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
476 {
477 	u32 tmp;
478 
479 	/* These registers are not accessible to VF-SRIOV.
480 	 * The PF will program them instead.
481 	 */
482 	if (amdgpu_sriov_vf(adev))
483 		return;
484 
485 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
486 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
487 			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
488 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
489 			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
490 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
491 			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
492 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
493 			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
494 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
495 			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
496 			    value);
497 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
498 			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
499 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
500 			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
501 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
502 			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
503 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
504 			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
505 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
506 			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
507 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
508 			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
509 	if (!value) {
510 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
511 				CRASH_ON_NO_RETRY_FAULT, 1);
512 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
513 				CRASH_ON_RETRY_FAULT, 1);
514 	}
515 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
516 }
517 
518 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
519 	.print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
520 	.get_invalidate_req = mmhub_v2_0_get_invalidate_req,
521 };
522 
523 static void mmhub_v2_0_init(struct amdgpu_device *adev)
524 {
525 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
526 
527 	hub->ctx0_ptb_addr_lo32 =
528 		SOC15_REG_OFFSET(MMHUB, 0,
529 				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
530 	hub->ctx0_ptb_addr_hi32 =
531 		SOC15_REG_OFFSET(MMHUB, 0,
532 				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
533 	hub->vm_inv_eng0_sem =
534 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
535 	hub->vm_inv_eng0_req =
536 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
537 	hub->vm_inv_eng0_ack =
538 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
539 	hub->vm_context0_cntl =
540 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
541 	hub->vm_l2_pro_fault_status =
542 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
543 	hub->vm_l2_pro_fault_cntl =
544 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
545 
546 	hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
547 	hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
548 		mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
549 	hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
550 		mmMMVM_INVALIDATE_ENG0_REQ;
551 	hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
552 		mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
553 
554 	hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
555 		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
556 		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
557 		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
558 		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
559 		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
560 		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
561 
562 	hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
563 }
564 
565 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
566 							bool enable)
567 {
568 	uint32_t def, data, def1, data1;
569 
570 	if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
571 		return;
572 
573 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
574 	case IP_VERSION(2, 1, 0):
575 	case IP_VERSION(2, 1, 1):
576 	case IP_VERSION(2, 1, 2):
577 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
578 		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
579 		break;
580 	default:
581 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
582 		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
583 		break;
584 	}
585 
586 	if (enable) {
587 		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
588 
589 		data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
590 		           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
591 		           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
592 		           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
593 		           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
594 		           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
595 
596 	} else {
597 		data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
598 
599 		data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
600 			  DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
601 			  DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
602 			  DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
603 			  DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
604 			  DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
605 	}
606 
607 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
608 	case IP_VERSION(2, 1, 0):
609 	case IP_VERSION(2, 1, 1):
610 	case IP_VERSION(2, 1, 2):
611 		if (def != data)
612 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
613 		if (def1 != data1)
614 			WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
615 		break;
616 	default:
617 		if (def != data)
618 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
619 		if (def1 != data1)
620 			WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
621 		break;
622 	}
623 }
624 
625 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
626 						       bool enable)
627 {
628 	uint32_t def, data;
629 
630 	if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
631 		return;
632 
633 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
634 	case IP_VERSION(2, 1, 0):
635 	case IP_VERSION(2, 1, 1):
636 	case IP_VERSION(2, 1, 2):
637 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
638 		break;
639 	default:
640 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
641 		break;
642 	}
643 
644 	if (enable)
645 		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
646 	else
647 		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
648 
649 	if (def != data) {
650 		switch (adev->ip_versions[MMHUB_HWIP][0]) {
651 		case IP_VERSION(2, 1, 0):
652 		case IP_VERSION(2, 1, 1):
653 		case IP_VERSION(2, 1, 2):
654 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
655 			break;
656 		default:
657 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
658 			break;
659 		}
660 	}
661 }
662 
663 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
664 			       enum amd_clockgating_state state)
665 {
666 	if (amdgpu_sriov_vf(adev))
667 		return 0;
668 
669 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
670 	case IP_VERSION(2, 0, 0):
671 	case IP_VERSION(2, 0, 2):
672 	case IP_VERSION(2, 1, 0):
673 	case IP_VERSION(2, 1, 1):
674 	case IP_VERSION(2, 1, 2):
675 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
676 				state == AMD_CG_STATE_GATE);
677 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
678 				state == AMD_CG_STATE_GATE);
679 		break;
680 	default:
681 		break;
682 	}
683 
684 	return 0;
685 }
686 
687 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
688 {
689 	int data, data1;
690 
691 	if (amdgpu_sriov_vf(adev))
692 		*flags = 0;
693 
694 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
695 	case IP_VERSION(2, 1, 0):
696 	case IP_VERSION(2, 1, 1):
697 	case IP_VERSION(2, 1, 2):
698 		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
699 		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
700 		break;
701 	default:
702 		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
703 		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
704 		break;
705 	}
706 
707 	/* AMD_CG_SUPPORT_MC_MGCG */
708 	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
709 	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
710 		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
711 		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
712 		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
713 		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
714 		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
715 		*flags |= AMD_CG_SUPPORT_MC_MGCG;
716 
717 	/* AMD_CG_SUPPORT_MC_LS */
718 	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
719 		*flags |= AMD_CG_SUPPORT_MC_LS;
720 }
721 
722 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
723 	.init = mmhub_v2_0_init,
724 	.gart_enable = mmhub_v2_0_gart_enable,
725 	.set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
726 	.gart_disable = mmhub_v2_0_gart_disable,
727 	.set_clockgating = mmhub_v2_0_set_clockgating,
728 	.get_clockgating = mmhub_v2_0_get_clockgating,
729 	.setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
730 };
731