1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d 35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0 36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070 37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0 38 39 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 40 uint64_t page_table_base) 41 { 42 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 43 44 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 45 hub->ctx_addr_distance * vmid, 46 lower_32_bits(page_table_base)); 47 48 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 49 hub->ctx_addr_distance * vmid, 50 upper_32_bits(page_table_base)); 51 } 52 53 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 54 { 55 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 56 57 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 58 59 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 60 (u32)(adev->gmc.gart_start >> 12)); 61 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 62 (u32)(adev->gmc.gart_start >> 44)); 63 64 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 65 (u32)(adev->gmc.gart_end >> 12)); 66 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 67 (u32)(adev->gmc.gart_end >> 44)); 68 } 69 70 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 71 { 72 uint64_t value; 73 uint32_t tmp; 74 75 /* Disable AGP. */ 76 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 77 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 78 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 79 80 if (!amdgpu_sriov_vf(adev)) { 81 /* 82 * the new L1 policy will block SRIOV guest from writing 83 * these regs, and they will be programed at host. 84 * so skip programing these regs. 85 */ 86 /* Program the system aperture low logical page number. */ 87 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 88 adev->gmc.vram_start >> 18); 89 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 90 adev->gmc.vram_end >> 18); 91 } 92 93 /* Set default page address. */ 94 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 95 adev->vm_manager.vram_base_offset; 96 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 97 (u32)(value >> 12)); 98 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 99 (u32)(value >> 44)); 100 101 /* Program "protection fault". */ 102 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 103 (u32)(adev->dummy_page_addr >> 12)); 104 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 105 (u32)((u64)adev->dummy_page_addr >> 44)); 106 107 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 108 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 109 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 110 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 111 } 112 113 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 114 { 115 uint32_t tmp; 116 117 /* Setup TLB control */ 118 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 119 120 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 121 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 122 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 123 ENABLE_ADVANCED_DRIVER_MODEL, 1); 124 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 125 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 126 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 127 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 128 MTYPE, MTYPE_UC); /* UC, uncached */ 129 130 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 131 } 132 133 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 134 { 135 uint32_t tmp; 136 137 /* These registers are not accessible to VF-SRIOV. 138 * The PF will program them instead. 139 */ 140 if (amdgpu_sriov_vf(adev)) 141 return; 142 143 /* Setup L2 cache */ 144 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 145 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 146 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 147 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 148 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 149 /* XXX for emulation, Refer to closed source code.*/ 150 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 151 0); 152 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 153 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 154 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 155 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 156 157 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 158 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 159 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 160 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 161 162 tmp = mmMMVM_L2_CNTL3_DEFAULT; 163 if (adev->gmc.translate_further) { 164 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 165 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 166 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 167 } else { 168 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 169 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 170 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 171 } 172 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 173 174 tmp = mmMMVM_L2_CNTL4_DEFAULT; 175 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 176 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 177 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 178 179 tmp = mmMMVM_L2_CNTL5_DEFAULT; 180 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 181 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 182 } 183 184 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 185 { 186 uint32_t tmp; 187 188 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 189 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 190 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 191 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 192 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 193 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 194 } 195 196 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 197 { 198 /* These registers are not accessible to VF-SRIOV. 199 * The PF will program them instead. 200 */ 201 if (amdgpu_sriov_vf(adev)) 202 return; 203 204 WREG32_SOC15(MMHUB, 0, 205 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 206 0xFFFFFFFF); 207 WREG32_SOC15(MMHUB, 0, 208 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 209 0x0000000F); 210 211 WREG32_SOC15(MMHUB, 0, 212 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 213 WREG32_SOC15(MMHUB, 0, 214 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 215 216 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 217 0); 218 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 219 0); 220 } 221 222 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 223 { 224 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 225 int i; 226 uint32_t tmp; 227 228 for (i = 0; i <= 14; i++) { 229 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 230 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 231 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 232 adev->vm_manager.num_level); 233 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 234 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 235 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 236 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 237 1); 238 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 239 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 240 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 241 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 242 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 243 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 244 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 245 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 246 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 247 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 248 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 249 PAGE_TABLE_BLOCK_SIZE, 250 adev->vm_manager.block_size - 9); 251 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 252 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 253 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 254 !amdgpu_noretry); 255 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, 256 i * hub->ctx_distance, tmp); 257 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 258 i * hub->ctx_addr_distance, 0); 259 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 260 i * hub->ctx_addr_distance, 0); 261 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 262 i * hub->ctx_addr_distance, 263 lower_32_bits(adev->vm_manager.max_pfn - 1)); 264 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 265 i * hub->ctx_addr_distance, 266 upper_32_bits(adev->vm_manager.max_pfn - 1)); 267 } 268 } 269 270 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 271 { 272 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 273 unsigned i; 274 275 for (i = 0; i < 18; ++i) { 276 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 277 i * hub->eng_addr_distance, 0xffffffff); 278 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 279 i * hub->eng_addr_distance, 0x1f); 280 } 281 } 282 283 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 284 { 285 /* GART Enable. */ 286 mmhub_v2_0_init_gart_aperture_regs(adev); 287 mmhub_v2_0_init_system_aperture_regs(adev); 288 mmhub_v2_0_init_tlb_regs(adev); 289 mmhub_v2_0_init_cache_regs(adev); 290 291 mmhub_v2_0_enable_system_domain(adev); 292 mmhub_v2_0_disable_identity_aperture(adev); 293 mmhub_v2_0_setup_vmid_config(adev); 294 mmhub_v2_0_program_invalidation(adev); 295 296 return 0; 297 } 298 299 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 300 { 301 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 302 u32 tmp; 303 u32 i; 304 305 /* Disable all tables */ 306 for (i = 0; i < 16; i++) 307 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, 308 i * hub->ctx_distance, 0); 309 310 /* Setup TLB control */ 311 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 312 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 313 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 314 ENABLE_ADVANCED_DRIVER_MODEL, 0); 315 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 316 317 /* Setup L2 cache */ 318 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 319 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 320 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 321 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 322 } 323 324 /** 325 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 326 * 327 * @adev: amdgpu_device pointer 328 * @value: true redirects VM faults to the default page 329 */ 330 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 331 { 332 u32 tmp; 333 334 /* These registers are not accessible to VF-SRIOV. 335 * The PF will program them instead. 336 */ 337 if (amdgpu_sriov_vf(adev)) 338 return; 339 340 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 341 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 342 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 343 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 344 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 345 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 346 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 347 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 348 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 349 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 350 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 351 value); 352 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 353 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 354 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 355 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 356 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 357 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 358 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 359 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 360 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 361 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 362 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 363 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 364 if (!value) { 365 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 366 CRASH_ON_NO_RETRY_FAULT, 1); 367 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 368 CRASH_ON_RETRY_FAULT, 1); 369 } 370 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 371 } 372 373 void mmhub_v2_0_init(struct amdgpu_device *adev) 374 { 375 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 376 377 hub->ctx0_ptb_addr_lo32 = 378 SOC15_REG_OFFSET(MMHUB, 0, 379 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 380 hub->ctx0_ptb_addr_hi32 = 381 SOC15_REG_OFFSET(MMHUB, 0, 382 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 383 hub->vm_inv_eng0_sem = 384 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM); 385 hub->vm_inv_eng0_req = 386 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 387 hub->vm_inv_eng0_ack = 388 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 389 hub->vm_context0_cntl = 390 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 391 hub->vm_l2_pro_fault_status = 392 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 393 hub->vm_l2_pro_fault_cntl = 394 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 395 396 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL; 397 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 398 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 399 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ - 400 mmMMVM_INVALIDATE_ENG0_REQ; 401 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 402 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 403 } 404 405 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 406 bool enable) 407 { 408 uint32_t def, data, def1, data1; 409 410 switch (adev->asic_type) { 411 case CHIP_SIENNA_CICHLID: 412 case CHIP_NAVY_FLOUNDER: 413 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 414 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 415 break; 416 default: 417 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 418 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 419 break; 420 } 421 422 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 423 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 424 425 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 426 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 427 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 428 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 429 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 430 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 431 432 } else { 433 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 434 435 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 436 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 437 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 438 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 439 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 440 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 441 } 442 443 switch (adev->asic_type) { 444 case CHIP_SIENNA_CICHLID: 445 case CHIP_NAVY_FLOUNDER: 446 if (def != data) 447 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 448 if (def1 != data1) 449 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1); 450 break; 451 default: 452 if (def != data) 453 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 454 if (def1 != data1) 455 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 456 break; 457 } 458 } 459 460 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 461 bool enable) 462 { 463 uint32_t def, data; 464 465 switch (adev->asic_type) { 466 case CHIP_SIENNA_CICHLID: 467 case CHIP_NAVY_FLOUNDER: 468 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 469 break; 470 default: 471 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 472 break; 473 } 474 475 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 476 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 477 else 478 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 479 480 if (def != data) { 481 switch (adev->asic_type) { 482 case CHIP_SIENNA_CICHLID: 483 case CHIP_NAVY_FLOUNDER: 484 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 485 break; 486 default: 487 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 488 break; 489 } 490 } 491 } 492 493 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 494 enum amd_clockgating_state state) 495 { 496 if (amdgpu_sriov_vf(adev)) 497 return 0; 498 499 switch (adev->asic_type) { 500 case CHIP_NAVI10: 501 case CHIP_NAVI14: 502 case CHIP_NAVI12: 503 case CHIP_SIENNA_CICHLID: 504 case CHIP_NAVY_FLOUNDER: 505 mmhub_v2_0_update_medium_grain_clock_gating(adev, 506 state == AMD_CG_STATE_GATE); 507 mmhub_v2_0_update_medium_grain_light_sleep(adev, 508 state == AMD_CG_STATE_GATE); 509 break; 510 default: 511 break; 512 } 513 514 return 0; 515 } 516 517 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 518 { 519 int data, data1; 520 521 if (amdgpu_sriov_vf(adev)) 522 *flags = 0; 523 524 switch (adev->asic_type) { 525 case CHIP_SIENNA_CICHLID: 526 case CHIP_NAVY_FLOUNDER: 527 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 528 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 529 break; 530 default: 531 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 532 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 533 break; 534 } 535 536 /* AMD_CG_SUPPORT_MC_MGCG */ 537 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 538 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 539 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 540 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 541 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 542 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 543 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 544 *flags |= AMD_CG_SUPPORT_MC_MGCG; 545 546 /* AMD_CG_SUPPORT_MC_LS */ 547 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 548 *flags |= AMD_CG_SUPPORT_MC_LS; 549 } 550