1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d 35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0 36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070 37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0 38 39 static const char *mmhub_client_ids_navi1x[][2] = { 40 [3][0] = "DCEDMC", 41 [4][0] = "DCEVGA", 42 [5][0] = "MP0", 43 [6][0] = "MP1", 44 [13][0] = "VMC", 45 [14][0] = "HDP", 46 [15][0] = "OSS", 47 [16][0] = "VCNU", 48 [17][0] = "JPEG", 49 [18][0] = "VCN", 50 [3][1] = "DCEDMC", 51 [4][1] = "DCEXFC", 52 [5][1] = "DCEVGA", 53 [6][1] = "DCEDWB", 54 [7][1] = "MP0", 55 [8][1] = "MP1", 56 [9][1] = "DBGU1", 57 [10][1] = "DBGU0", 58 [11][1] = "XDP", 59 [14][1] = "HDP", 60 [15][1] = "OSS", 61 [16][1] = "VCNU", 62 [17][1] = "JPEG", 63 [18][1] = "VCN", 64 }; 65 66 static const char *mmhub_client_ids_sienna_cichlid[][2] = { 67 [3][0] = "DCEDMC", 68 [4][0] = "DCEVGA", 69 [5][0] = "MP0", 70 [6][0] = "MP1", 71 [8][0] = "VMC", 72 [9][0] = "VCNU0", 73 [10][0] = "JPEG", 74 [12][0] = "VCNU1", 75 [13][0] = "VCN1", 76 [14][0] = "HDP", 77 [15][0] = "OSS", 78 [32+11][0] = "VCN0", 79 [0][1] = "DBGU0", 80 [1][1] = "DBGU1", 81 [2][1] = "DCEDWB", 82 [3][1] = "DCEDMC", 83 [4][1] = "DCEVGA", 84 [5][1] = "MP0", 85 [6][1] = "MP1", 86 [7][1] = "XDP", 87 [9][1] = "VCNU0", 88 [10][1] = "JPEG", 89 [11][1] = "VCN0", 90 [12][1] = "VCNU1", 91 [13][1] = "VCN1", 92 [14][1] = "HDP", 93 [15][1] = "OSS", 94 }; 95 96 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid, 97 uint32_t flush_type) 98 { 99 u32 req = 0; 100 101 /* invalidate using legacy mode on vmid*/ 102 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 103 PER_VMID_INVALIDATE_REQ, 1 << vmid); 104 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 105 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 106 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 107 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 108 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 109 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 110 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 111 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 112 113 return req; 114 } 115 116 static void 117 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 118 uint32_t status) 119 { 120 uint32_t cid, rw; 121 const char *mmhub_cid = NULL; 122 123 cid = REG_GET_FIELD(status, 124 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 125 rw = REG_GET_FIELD(status, 126 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 127 128 dev_err(adev->dev, 129 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 130 status); 131 switch (adev->asic_type) { 132 case CHIP_NAVI10: 133 case CHIP_NAVI12: 134 case CHIP_NAVI14: 135 mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; 136 break; 137 case CHIP_SIENNA_CICHLID: 138 case CHIP_NAVY_FLOUNDER: 139 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; 140 break; 141 default: 142 mmhub_cid = NULL; 143 break; 144 } 145 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 146 mmhub_cid ? mmhub_cid : "unknown", cid); 147 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 148 REG_GET_FIELD(status, 149 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 150 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 151 REG_GET_FIELD(status, 152 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 153 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 154 REG_GET_FIELD(status, 155 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 156 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 157 REG_GET_FIELD(status, 158 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 159 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 160 } 161 162 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 163 uint64_t page_table_base) 164 { 165 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 166 167 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 168 hub->ctx_addr_distance * vmid, 169 lower_32_bits(page_table_base)); 170 171 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 172 hub->ctx_addr_distance * vmid, 173 upper_32_bits(page_table_base)); 174 } 175 176 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 177 { 178 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 179 180 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 181 182 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 183 (u32)(adev->gmc.gart_start >> 12)); 184 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 185 (u32)(adev->gmc.gart_start >> 44)); 186 187 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 188 (u32)(adev->gmc.gart_end >> 12)); 189 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 190 (u32)(adev->gmc.gart_end >> 44)); 191 } 192 193 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 194 { 195 uint64_t value; 196 uint32_t tmp; 197 198 /* Disable AGP. */ 199 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 200 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 201 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 202 203 if (!amdgpu_sriov_vf(adev)) { 204 /* 205 * the new L1 policy will block SRIOV guest from writing 206 * these regs, and they will be programed at host. 207 * so skip programing these regs. 208 */ 209 /* Program the system aperture low logical page number. */ 210 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 211 adev->gmc.vram_start >> 18); 212 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 213 adev->gmc.vram_end >> 18); 214 } 215 216 /* Set default page address. */ 217 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 218 adev->vm_manager.vram_base_offset; 219 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 220 (u32)(value >> 12)); 221 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 222 (u32)(value >> 44)); 223 224 /* Program "protection fault". */ 225 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 226 (u32)(adev->dummy_page_addr >> 12)); 227 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 228 (u32)((u64)adev->dummy_page_addr >> 44)); 229 230 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 231 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 232 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 233 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 234 } 235 236 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 237 { 238 uint32_t tmp; 239 240 /* Setup TLB control */ 241 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 242 243 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 244 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 245 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 246 ENABLE_ADVANCED_DRIVER_MODEL, 1); 247 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 248 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 249 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 250 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 251 MTYPE, MTYPE_UC); /* UC, uncached */ 252 253 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 254 } 255 256 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 257 { 258 uint32_t tmp; 259 260 /* These registers are not accessible to VF-SRIOV. 261 * The PF will program them instead. 262 */ 263 if (amdgpu_sriov_vf(adev)) 264 return; 265 266 /* Setup L2 cache */ 267 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 268 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 269 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 270 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 271 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 272 /* XXX for emulation, Refer to closed source code.*/ 273 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 274 0); 275 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 276 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 277 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 278 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 279 280 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 281 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 282 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 283 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 284 285 tmp = mmMMVM_L2_CNTL3_DEFAULT; 286 if (adev->gmc.translate_further) { 287 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 288 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 289 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 290 } else { 291 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 292 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 293 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 294 } 295 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 296 297 tmp = mmMMVM_L2_CNTL4_DEFAULT; 298 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 299 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 300 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 301 302 tmp = mmMMVM_L2_CNTL5_DEFAULT; 303 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 304 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 305 } 306 307 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 308 { 309 uint32_t tmp; 310 311 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 312 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 313 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 314 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 315 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 316 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 317 } 318 319 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 320 { 321 /* These registers are not accessible to VF-SRIOV. 322 * The PF will program them instead. 323 */ 324 if (amdgpu_sriov_vf(adev)) 325 return; 326 327 WREG32_SOC15(MMHUB, 0, 328 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 329 0xFFFFFFFF); 330 WREG32_SOC15(MMHUB, 0, 331 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 332 0x0000000F); 333 334 WREG32_SOC15(MMHUB, 0, 335 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 336 WREG32_SOC15(MMHUB, 0, 337 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 338 339 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 340 0); 341 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 342 0); 343 } 344 345 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 346 { 347 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 348 int i; 349 uint32_t tmp; 350 351 for (i = 0; i <= 14; i++) { 352 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 353 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 354 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 355 adev->vm_manager.num_level); 356 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 357 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 358 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 359 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 360 1); 361 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 362 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 363 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 364 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 365 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 366 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 367 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 368 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 369 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 370 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 371 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 372 PAGE_TABLE_BLOCK_SIZE, 373 adev->vm_manager.block_size - 9); 374 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 375 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 376 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 377 !amdgpu_noretry); 378 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, 379 i * hub->ctx_distance, tmp); 380 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 381 i * hub->ctx_addr_distance, 0); 382 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 383 i * hub->ctx_addr_distance, 0); 384 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 385 i * hub->ctx_addr_distance, 386 lower_32_bits(adev->vm_manager.max_pfn - 1)); 387 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 388 i * hub->ctx_addr_distance, 389 upper_32_bits(adev->vm_manager.max_pfn - 1)); 390 } 391 } 392 393 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 394 { 395 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 396 unsigned i; 397 398 for (i = 0; i < 18; ++i) { 399 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 400 i * hub->eng_addr_distance, 0xffffffff); 401 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 402 i * hub->eng_addr_distance, 0x1f); 403 } 404 } 405 406 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 407 { 408 /* GART Enable. */ 409 mmhub_v2_0_init_gart_aperture_regs(adev); 410 mmhub_v2_0_init_system_aperture_regs(adev); 411 mmhub_v2_0_init_tlb_regs(adev); 412 mmhub_v2_0_init_cache_regs(adev); 413 414 mmhub_v2_0_enable_system_domain(adev); 415 mmhub_v2_0_disable_identity_aperture(adev); 416 mmhub_v2_0_setup_vmid_config(adev); 417 mmhub_v2_0_program_invalidation(adev); 418 419 return 0; 420 } 421 422 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 423 { 424 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 425 u32 tmp; 426 u32 i; 427 428 /* Disable all tables */ 429 for (i = 0; i < 16; i++) 430 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, 431 i * hub->ctx_distance, 0); 432 433 /* Setup TLB control */ 434 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 435 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 436 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 437 ENABLE_ADVANCED_DRIVER_MODEL, 0); 438 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 439 440 /* Setup L2 cache */ 441 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 442 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 443 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 444 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 445 } 446 447 /** 448 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 449 * 450 * @adev: amdgpu_device pointer 451 * @value: true redirects VM faults to the default page 452 */ 453 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 454 { 455 u32 tmp; 456 457 /* These registers are not accessible to VF-SRIOV. 458 * The PF will program them instead. 459 */ 460 if (amdgpu_sriov_vf(adev)) 461 return; 462 463 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 464 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 465 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 466 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 467 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 468 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 469 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 470 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 471 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 472 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 473 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 474 value); 475 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 476 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 477 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 478 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 479 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 480 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 481 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 482 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 483 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 484 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 485 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 486 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 487 if (!value) { 488 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 489 CRASH_ON_NO_RETRY_FAULT, 1); 490 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 491 CRASH_ON_RETRY_FAULT, 1); 492 } 493 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 494 } 495 496 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = { 497 .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status, 498 .get_invalidate_req = mmhub_v2_0_get_invalidate_req, 499 }; 500 501 static void mmhub_v2_0_init(struct amdgpu_device *adev) 502 { 503 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 504 505 hub->ctx0_ptb_addr_lo32 = 506 SOC15_REG_OFFSET(MMHUB, 0, 507 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 508 hub->ctx0_ptb_addr_hi32 = 509 SOC15_REG_OFFSET(MMHUB, 0, 510 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 511 hub->vm_inv_eng0_sem = 512 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM); 513 hub->vm_inv_eng0_req = 514 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 515 hub->vm_inv_eng0_ack = 516 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 517 hub->vm_context0_cntl = 518 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 519 hub->vm_l2_pro_fault_status = 520 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 521 hub->vm_l2_pro_fault_cntl = 522 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 523 524 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL; 525 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 526 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 527 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ - 528 mmMMVM_INVALIDATE_ENG0_REQ; 529 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 530 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 531 532 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 533 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 534 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 535 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 536 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 537 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 538 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 539 540 hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs; 541 } 542 543 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 544 bool enable) 545 { 546 uint32_t def, data, def1, data1; 547 548 switch (adev->asic_type) { 549 case CHIP_SIENNA_CICHLID: 550 case CHIP_NAVY_FLOUNDER: 551 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 552 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 553 break; 554 default: 555 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 556 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 557 break; 558 } 559 560 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 561 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 562 563 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 564 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 565 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 566 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 567 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 568 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 569 570 } else { 571 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 572 573 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 574 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 575 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 576 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 577 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 578 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 579 } 580 581 switch (adev->asic_type) { 582 case CHIP_SIENNA_CICHLID: 583 case CHIP_NAVY_FLOUNDER: 584 if (def != data) 585 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 586 if (def1 != data1) 587 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1); 588 break; 589 default: 590 if (def != data) 591 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 592 if (def1 != data1) 593 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 594 break; 595 } 596 } 597 598 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 599 bool enable) 600 { 601 uint32_t def, data; 602 603 switch (adev->asic_type) { 604 case CHIP_SIENNA_CICHLID: 605 case CHIP_NAVY_FLOUNDER: 606 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 607 break; 608 default: 609 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 610 break; 611 } 612 613 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 614 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 615 else 616 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 617 618 if (def != data) { 619 switch (adev->asic_type) { 620 case CHIP_SIENNA_CICHLID: 621 case CHIP_NAVY_FLOUNDER: 622 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 623 break; 624 default: 625 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 626 break; 627 } 628 } 629 } 630 631 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 632 enum amd_clockgating_state state) 633 { 634 if (amdgpu_sriov_vf(adev)) 635 return 0; 636 637 switch (adev->asic_type) { 638 case CHIP_NAVI10: 639 case CHIP_NAVI14: 640 case CHIP_NAVI12: 641 case CHIP_SIENNA_CICHLID: 642 case CHIP_NAVY_FLOUNDER: 643 mmhub_v2_0_update_medium_grain_clock_gating(adev, 644 state == AMD_CG_STATE_GATE); 645 mmhub_v2_0_update_medium_grain_light_sleep(adev, 646 state == AMD_CG_STATE_GATE); 647 break; 648 default: 649 break; 650 } 651 652 return 0; 653 } 654 655 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 656 { 657 int data, data1; 658 659 if (amdgpu_sriov_vf(adev)) 660 *flags = 0; 661 662 switch (adev->asic_type) { 663 case CHIP_SIENNA_CICHLID: 664 case CHIP_NAVY_FLOUNDER: 665 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 666 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 667 break; 668 default: 669 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 670 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 671 break; 672 } 673 674 /* AMD_CG_SUPPORT_MC_MGCG */ 675 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 676 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 677 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 678 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 679 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 680 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 681 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 682 *flags |= AMD_CG_SUPPORT_MC_MGCG; 683 684 /* AMD_CG_SUPPORT_MC_LS */ 685 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 686 *flags |= AMD_CG_SUPPORT_MC_LS; 687 } 688 689 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = { 690 .ras_late_init = amdgpu_mmhub_ras_late_init, 691 .init = mmhub_v2_0_init, 692 .gart_enable = mmhub_v2_0_gart_enable, 693 .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default, 694 .gart_disable = mmhub_v2_0_gart_disable, 695 .set_clockgating = mmhub_v2_0_set_clockgating, 696 .get_clockgating = mmhub_v2_0_get_clockgating, 697 .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs, 698 }; 699