1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d 35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0 36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070 37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0 38 39 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 40 uint64_t page_table_base) 41 { 42 /* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */ 43 int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 44 - mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 45 46 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 47 offset * vmid, lower_32_bits(page_table_base)); 48 49 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 50 offset * vmid, upper_32_bits(page_table_base)); 51 } 52 53 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 54 { 55 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 56 57 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 58 59 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 60 (u32)(adev->gmc.gart_start >> 12)); 61 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 62 (u32)(adev->gmc.gart_start >> 44)); 63 64 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 65 (u32)(adev->gmc.gart_end >> 12)); 66 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 67 (u32)(adev->gmc.gart_end >> 44)); 68 } 69 70 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 71 { 72 uint64_t value; 73 uint32_t tmp; 74 75 /* Disable AGP. */ 76 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 77 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 78 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 79 80 if (!amdgpu_sriov_vf(adev)) { 81 /* 82 * the new L1 policy will block SRIOV guest from writing 83 * these regs, and they will be programed at host. 84 * so skip programing these regs. 85 */ 86 /* Program the system aperture low logical page number. */ 87 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 88 adev->gmc.vram_start >> 18); 89 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 90 adev->gmc.vram_end >> 18); 91 } 92 93 /* Set default page address. */ 94 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 95 adev->vm_manager.vram_base_offset; 96 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 97 (u32)(value >> 12)); 98 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 99 (u32)(value >> 44)); 100 101 /* Program "protection fault". */ 102 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 103 (u32)(adev->dummy_page_addr >> 12)); 104 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 105 (u32)((u64)adev->dummy_page_addr >> 44)); 106 107 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 108 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 109 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 110 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 111 } 112 113 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 114 { 115 uint32_t tmp; 116 117 /* Setup TLB control */ 118 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 119 120 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 121 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 122 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 123 ENABLE_ADVANCED_DRIVER_MODEL, 1); 124 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 125 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 126 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 127 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 128 MTYPE, MTYPE_UC); /* UC, uncached */ 129 130 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 131 } 132 133 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 134 { 135 uint32_t tmp; 136 137 /* Setup L2 cache */ 138 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 139 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 140 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 141 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 142 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 143 /* XXX for emulation, Refer to closed source code.*/ 144 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 145 0); 146 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 147 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 148 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 149 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 150 151 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 152 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 153 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 154 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 155 156 tmp = mmMMVM_L2_CNTL3_DEFAULT; 157 if (adev->gmc.translate_further) { 158 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 159 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 160 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 161 } else { 162 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 163 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 164 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 165 } 166 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 167 168 tmp = mmMMVM_L2_CNTL4_DEFAULT; 169 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 170 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 171 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 172 173 tmp = mmMMVM_L2_CNTL5_DEFAULT; 174 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 175 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 176 } 177 178 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 179 { 180 uint32_t tmp; 181 182 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 183 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 184 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 185 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 186 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 187 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 188 } 189 190 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 191 { 192 WREG32_SOC15(MMHUB, 0, 193 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 194 0xFFFFFFFF); 195 WREG32_SOC15(MMHUB, 0, 196 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 197 0x0000000F); 198 199 WREG32_SOC15(MMHUB, 0, 200 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 201 WREG32_SOC15(MMHUB, 0, 202 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 203 204 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 205 0); 206 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 207 0); 208 } 209 210 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 211 { 212 int i; 213 uint32_t tmp; 214 215 for (i = 0; i <= 14; i++) { 216 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 217 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 218 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 219 adev->vm_manager.num_level); 220 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 221 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 222 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 223 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 224 1); 225 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 226 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 227 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 228 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 229 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 230 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 231 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 232 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 233 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 234 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 235 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 236 PAGE_TABLE_BLOCK_SIZE, 237 adev->vm_manager.block_size - 9); 238 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 239 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 240 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 241 !amdgpu_noretry); 242 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); 243 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 244 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 245 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 246 lower_32_bits(adev->vm_manager.max_pfn - 1)); 247 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 248 upper_32_bits(adev->vm_manager.max_pfn - 1)); 249 } 250 } 251 252 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 253 { 254 unsigned i; 255 256 for (i = 0; i < 18; ++i) { 257 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 258 2 * i, 0xffffffff); 259 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 260 2 * i, 0x1f); 261 } 262 } 263 264 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 265 { 266 /* GART Enable. */ 267 mmhub_v2_0_init_gart_aperture_regs(adev); 268 mmhub_v2_0_init_system_aperture_regs(adev); 269 mmhub_v2_0_init_tlb_regs(adev); 270 mmhub_v2_0_init_cache_regs(adev); 271 272 mmhub_v2_0_enable_system_domain(adev); 273 mmhub_v2_0_disable_identity_aperture(adev); 274 mmhub_v2_0_setup_vmid_config(adev); 275 mmhub_v2_0_program_invalidation(adev); 276 277 return 0; 278 } 279 280 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 281 { 282 u32 tmp; 283 u32 i; 284 285 /* Disable all tables */ 286 for (i = 0; i < 16; i++) 287 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0); 288 289 /* Setup TLB control */ 290 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 291 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 292 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 293 ENABLE_ADVANCED_DRIVER_MODEL, 0); 294 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 295 296 /* Setup L2 cache */ 297 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 298 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 299 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 300 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 301 } 302 303 /** 304 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 305 * 306 * @adev: amdgpu_device pointer 307 * @value: true redirects VM faults to the default page 308 */ 309 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 310 { 311 u32 tmp; 312 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 313 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 314 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 316 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 318 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 319 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 320 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 321 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 322 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 323 value); 324 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 325 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 326 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 327 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 328 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 329 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 330 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 331 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 332 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 333 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 334 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 335 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 336 if (!value) { 337 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 338 CRASH_ON_NO_RETRY_FAULT, 1); 339 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 340 CRASH_ON_RETRY_FAULT, 1); 341 } 342 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 343 } 344 345 void mmhub_v2_0_init(struct amdgpu_device *adev) 346 { 347 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 348 349 hub->ctx0_ptb_addr_lo32 = 350 SOC15_REG_OFFSET(MMHUB, 0, 351 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 352 hub->ctx0_ptb_addr_hi32 = 353 SOC15_REG_OFFSET(MMHUB, 0, 354 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 355 hub->vm_inv_eng0_sem = 356 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM); 357 hub->vm_inv_eng0_req = 358 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 359 hub->vm_inv_eng0_ack = 360 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 361 hub->vm_context0_cntl = 362 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 363 hub->vm_l2_pro_fault_status = 364 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 365 hub->vm_l2_pro_fault_cntl = 366 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 367 368 } 369 370 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 371 bool enable) 372 { 373 uint32_t def, data, def1, data1; 374 375 switch (adev->asic_type) { 376 case CHIP_SIENNA_CICHLID: 377 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 378 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 379 break; 380 default: 381 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 382 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 383 break; 384 } 385 386 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 387 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 388 389 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 390 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 391 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 392 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 393 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 394 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 395 396 } else { 397 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 398 399 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 400 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 401 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 402 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 403 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 404 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 405 } 406 407 switch (adev->asic_type) { 408 case CHIP_SIENNA_CICHLID: 409 if (def != data) 410 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 411 if (def1 != data1) 412 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1); 413 break; 414 default: 415 if (def != data) 416 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 417 if (def1 != data1) 418 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 419 break; 420 } 421 } 422 423 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 424 bool enable) 425 { 426 uint32_t def, data; 427 428 switch (adev->asic_type) { 429 case CHIP_SIENNA_CICHLID: 430 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 431 break; 432 default: 433 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 434 break; 435 } 436 437 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 438 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 439 else 440 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 441 442 if (def != data) { 443 switch (adev->asic_type) { 444 case CHIP_SIENNA_CICHLID: 445 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 446 break; 447 default: 448 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 449 break; 450 } 451 } 452 } 453 454 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 455 enum amd_clockgating_state state) 456 { 457 if (amdgpu_sriov_vf(adev)) 458 return 0; 459 460 switch (adev->asic_type) { 461 case CHIP_NAVI10: 462 case CHIP_NAVI14: 463 case CHIP_NAVI12: 464 mmhub_v2_0_update_medium_grain_clock_gating(adev, 465 state == AMD_CG_STATE_GATE); 466 mmhub_v2_0_update_medium_grain_light_sleep(adev, 467 state == AMD_CG_STATE_GATE); 468 break; 469 default: 470 break; 471 } 472 473 return 0; 474 } 475 476 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 477 { 478 int data, data1; 479 480 if (amdgpu_sriov_vf(adev)) 481 *flags = 0; 482 483 switch (adev->asic_type) { 484 case CHIP_SIENNA_CICHLID: 485 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 486 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 487 break; 488 default: 489 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 490 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 491 break; 492 } 493 494 /* AMD_CG_SUPPORT_MC_MGCG */ 495 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 496 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 497 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 498 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 499 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 500 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 501 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 502 *flags |= AMD_CG_SUPPORT_MC_MGCG; 503 504 /* AMD_CG_SUPPORT_MC_LS */ 505 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 506 *flags |= AMD_CG_SUPPORT_MC_LS; 507 } 508