1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_ras.h" 25 #include "mmhub_v1_7.h" 26 27 #include "mmhub/mmhub_1_7_offset.h" 28 #include "mmhub/mmhub_1_7_sh_mask.h" 29 #include "vega10_enum.h" 30 31 #include "soc15_common.h" 32 #include "soc15.h" 33 34 #define regVM_L2_CNTL3_DEFAULT 0x80100007 35 #define regVM_L2_CNTL4_DEFAULT 0x000000c1 36 37 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev) 38 { 39 u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE); 40 u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP); 41 42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 43 base <<= 24; 44 45 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 46 top <<= 24; 47 48 adev->gmc.fb_start = base; 49 adev->gmc.fb_end = top; 50 adev->gmc.fb_start_original = base; 51 adev->gmc.fb_end_original = top; 52 53 return base; 54 } 55 56 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 57 uint64_t page_table_base) 58 { 59 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 60 61 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 62 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); 63 64 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 65 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); 66 } 67 68 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev) 69 { 70 uint64_t pt_base; 71 72 if (adev->gmc.pdb0_bo) 73 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 74 else 75 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 76 77 mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base); 78 79 /* If use GART for FB translation, vmid0 page table covers both 80 * vram and system memory (gart) 81 */ 82 if (adev->gmc.pdb0_bo) { 83 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 84 (u32)(adev->gmc.fb_start >> 12)); 85 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 86 (u32)(adev->gmc.fb_start >> 44)); 87 88 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 89 (u32)(adev->gmc.gart_end >> 12)); 90 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 91 (u32)(adev->gmc.gart_end >> 44)); 92 93 } else { 94 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 95 (u32)(adev->gmc.gart_start >> 12)); 96 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 97 (u32)(adev->gmc.gart_start >> 44)); 98 99 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 100 (u32)(adev->gmc.gart_end >> 12)); 101 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 102 (u32)(adev->gmc.gart_end >> 44)); 103 } 104 } 105 106 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) 107 { 108 uint64_t value; 109 uint32_t tmp; 110 111 /* Program the AGP BAR */ 112 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0); 113 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 114 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 115 116 /* Program the system aperture low logical page number. */ 117 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 118 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 119 120 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 121 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 122 123 /* In the case squeezing vram into GART aperture, we don't use 124 * FB aperture and AGP aperture. Disable them. 125 */ 126 if (adev->gmc.pdb0_bo) { 127 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF); 128 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0); 129 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24); 130 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24); 131 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18); 132 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18); 133 } 134 if (amdgpu_sriov_vf(adev)) 135 return; 136 137 /* Set default page address. */ 138 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 139 adev->vm_manager.vram_base_offset; 140 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 141 (u32)(value >> 12)); 142 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 143 (u32)(value >> 44)); 144 145 /* Program "protection fault". */ 146 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 147 (u32)(adev->dummy_page_addr >> 12)); 148 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 149 (u32)((u64)adev->dummy_page_addr >> 44)); 150 151 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2); 152 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 153 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 154 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); 155 } 156 157 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev) 158 { 159 uint32_t tmp; 160 161 /* Setup TLB control */ 162 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); 163 164 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 166 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 167 ENABLE_ADVANCED_DRIVER_MODEL, 1); 168 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 169 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 170 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 171 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 172 MTYPE, MTYPE_UC);/* XXX for emulation. */ 173 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 174 175 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); 176 } 177 178 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev) 179 { 180 uint32_t tmp; 181 182 if (amdgpu_sriov_vf(adev)) 183 return; 184 185 /* Setup L2 cache */ 186 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 189 /* XXX for emulation, Refer to closed source code.*/ 190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 191 0); 192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 193 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 194 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 195 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); 196 197 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2); 198 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 199 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 200 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp); 201 202 tmp = regVM_L2_CNTL3_DEFAULT; 203 if (adev->gmc.translate_further) { 204 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 205 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 206 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 207 } else { 208 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 209 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 210 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 211 } 212 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp); 213 214 tmp = regVM_L2_CNTL4_DEFAULT; 215 if (adev->gmc.xgmi.connected_to_cpu) { 216 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 217 VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 218 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 219 VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 220 } else { 221 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 222 VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 223 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 224 VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 225 } 226 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp); 227 } 228 229 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev) 230 { 231 uint32_t tmp; 232 233 tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL); 234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 236 adev->gmc.vmid0_page_table_depth); 237 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, 238 adev->gmc.vmid0_page_table_block_size); 239 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 240 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 241 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp); 242 } 243 244 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev) 245 { 246 if (amdgpu_sriov_vf(adev)) 247 return; 248 249 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 250 0XFFFFFFFF); 251 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 252 0x0000000F); 253 254 WREG32_SOC15(MMHUB, 0, 255 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 256 WREG32_SOC15(MMHUB, 0, 257 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 258 259 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 260 0); 261 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 262 0); 263 } 264 265 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) 266 { 267 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 268 unsigned num_level, block_size; 269 uint32_t tmp; 270 int i; 271 272 num_level = adev->vm_manager.num_level; 273 block_size = adev->vm_manager.block_size; 274 if (adev->gmc.translate_further) 275 num_level -= 1; 276 else 277 block_size -= 9; 278 279 for (i = 0; i <= 14; i++) { 280 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i); 281 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 283 num_level); 284 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 285 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 286 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 287 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 288 1); 289 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 290 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 291 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 292 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 293 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 294 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 295 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 296 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 297 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 298 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 299 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 300 PAGE_TABLE_BLOCK_SIZE, 301 block_size); 302 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 303 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 304 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 305 !adev->gmc.noretry); 306 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, 307 i * hub->ctx_distance, tmp); 308 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 309 i * hub->ctx_addr_distance, 0); 310 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 311 i * hub->ctx_addr_distance, 0); 312 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 313 i * hub->ctx_addr_distance, 314 lower_32_bits(adev->vm_manager.max_pfn - 1)); 315 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 316 i * hub->ctx_addr_distance, 317 upper_32_bits(adev->vm_manager.max_pfn - 1)); 318 } 319 } 320 321 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev) 322 { 323 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 324 unsigned i; 325 326 for (i = 0; i < 18; ++i) { 327 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 328 i * hub->eng_addr_distance, 0xffffffff); 329 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 330 i * hub->eng_addr_distance, 0x1f); 331 } 332 } 333 334 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev) 335 { 336 if (amdgpu_sriov_vf(adev)) { 337 /* 338 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 339 * VF copy registers so vbios post doesn't program them, for 340 * SRIOV driver need to program them 341 */ 342 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 343 adev->gmc.vram_start >> 24); 344 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 345 adev->gmc.vram_end >> 24); 346 } 347 348 /* GART Enable. */ 349 mmhub_v1_7_init_gart_aperture_regs(adev); 350 mmhub_v1_7_init_system_aperture_regs(adev); 351 mmhub_v1_7_init_tlb_regs(adev); 352 mmhub_v1_7_init_cache_regs(adev); 353 354 mmhub_v1_7_enable_system_domain(adev); 355 mmhub_v1_7_disable_identity_aperture(adev); 356 mmhub_v1_7_setup_vmid_config(adev); 357 mmhub_v1_7_program_invalidation(adev); 358 359 return 0; 360 } 361 362 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev) 363 { 364 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 365 u32 tmp; 366 u32 i; 367 368 /* Disable all tables */ 369 for (i = 0; i < 16; i++) 370 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL, 371 i * hub->ctx_distance, 0); 372 373 /* Setup TLB control */ 374 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); 375 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 376 tmp = REG_SET_FIELD(tmp, 377 MC_VM_MX_L1_TLB_CNTL, 378 ENABLE_ADVANCED_DRIVER_MODEL, 379 0); 380 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); 381 382 if (!amdgpu_sriov_vf(adev)) { 383 /* Setup L2 cache */ 384 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); 385 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 386 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); 387 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0); 388 } 389 } 390 391 /** 392 * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling 393 * 394 * @adev: amdgpu_device pointer 395 * @value: true redirects VM faults to the default page 396 */ 397 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value) 398 { 399 u32 tmp; 400 401 if (amdgpu_sriov_vf(adev)) 402 return; 403 404 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); 405 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 406 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 407 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 408 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 409 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 410 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 411 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 412 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 413 tmp = REG_SET_FIELD(tmp, 414 VM_L2_PROTECTION_FAULT_CNTL, 415 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 416 value); 417 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 418 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 419 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 420 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 421 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 422 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 423 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 424 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 425 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 426 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 427 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 428 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 429 if (!value) { 430 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 431 CRASH_ON_NO_RETRY_FAULT, 1); 432 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 433 CRASH_ON_RETRY_FAULT, 1); 434 } 435 436 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp); 437 } 438 439 static void mmhub_v1_7_init(struct amdgpu_device *adev) 440 { 441 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 442 443 hub->ctx0_ptb_addr_lo32 = 444 SOC15_REG_OFFSET(MMHUB, 0, 445 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 446 hub->ctx0_ptb_addr_hi32 = 447 SOC15_REG_OFFSET(MMHUB, 0, 448 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 449 hub->vm_inv_eng0_req = 450 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ); 451 hub->vm_inv_eng0_ack = 452 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK); 453 hub->vm_context0_cntl = 454 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL); 455 hub->vm_l2_pro_fault_status = 456 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS); 457 hub->vm_l2_pro_fault_cntl = 458 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); 459 460 hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL; 461 hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 462 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 463 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ; 464 hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 465 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 466 467 } 468 469 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev, 470 bool enable) 471 { 472 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 473 474 def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); 475 476 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); 477 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); 478 479 if (enable) { 480 data |= ATC_L2_MISC_CG__ENABLE_MASK; 481 482 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 483 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 484 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 485 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 486 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 487 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 488 489 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 490 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 491 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 492 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 493 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 494 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 495 } else { 496 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 497 498 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 499 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 500 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 501 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 502 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 503 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 504 505 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 506 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 507 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 508 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 509 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 510 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 511 } 512 513 if (def != data) 514 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); 515 516 if (def1 != data1) 517 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1); 518 519 if (def2 != data2) 520 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); 521 } 522 523 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev, 524 bool enable) 525 { 526 uint32_t def, data; 527 528 def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); 529 530 if (enable) 531 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 532 else 533 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 534 535 if (def != data) 536 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); 537 } 538 539 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev, 540 enum amd_clockgating_state state) 541 { 542 if (amdgpu_sriov_vf(adev)) 543 return 0; 544 545 /* Change state only if MCCG support is enabled through driver */ 546 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) 547 mmhub_v1_7_update_medium_grain_clock_gating(adev, 548 state == AMD_CG_STATE_GATE); 549 550 /* Change state only if LS support is enabled through driver */ 551 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) 552 mmhub_v1_7_update_medium_grain_light_sleep(adev, 553 state == AMD_CG_STATE_GATE); 554 555 return 0; 556 } 557 558 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags) 559 { 560 int data, data1; 561 562 if (amdgpu_sriov_vf(adev)) 563 *flags = 0; 564 565 data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); 566 567 data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); 568 569 /* AMD_CG_SUPPORT_MC_MGCG */ 570 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && 571 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 572 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 573 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 574 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 575 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 576 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 577 *flags |= AMD_CG_SUPPORT_MC_MGCG; 578 579 /* AMD_CG_SUPPORT_MC_LS */ 580 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 581 *flags |= AMD_CG_SUPPORT_MC_LS; 582 } 583 584 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = { 585 /* MMHUB Range 0 */ 586 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 587 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 588 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 589 }, 590 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 591 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 592 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 593 }, 594 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 595 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 596 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 597 }, 598 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 599 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 600 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT), 601 }, 602 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 603 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 604 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT), 605 }, 606 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 607 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 608 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 609 }, 610 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 611 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 612 0, 0, 613 }, 614 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 615 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 616 0, 0, 617 }, 618 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 619 SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT), 620 0, 0, 621 }, 622 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 623 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 624 0, 0, 625 }, 626 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 627 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 628 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 629 }, 630 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 631 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 632 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 633 }, 634 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 635 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 636 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 637 }, 638 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 639 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 640 0, 0, 641 }, 642 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 643 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 644 0, 0, 645 }, 646 { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 647 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), 648 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), 649 }, 650 { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 651 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT), 652 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT), 653 }, 654 { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 655 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT), 656 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT), 657 }, 658 { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 659 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT), 660 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT), 661 }, 662 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 663 0, 0, 664 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 665 }, 666 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 667 0, 0, 668 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 669 }, 670 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 671 0, 0, 672 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 673 }, 674 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 675 0, 0, 676 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 677 }, 678 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 679 0, 0, 680 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 681 }, 682 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 683 0, 0, 684 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 685 }, 686 687 /* MMHUB Range 1 */ 688 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 689 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 690 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 691 }, 692 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 693 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 694 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 695 }, 696 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 697 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 698 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 699 }, 700 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 701 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 702 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT), 703 }, 704 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 705 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 706 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT), 707 }, 708 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 709 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 710 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 711 }, 712 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 713 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 714 0, 0, 715 }, 716 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 717 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 718 0, 0, 719 }, 720 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 721 SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT), 722 0, 0, 723 }, 724 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 725 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 726 0, 0, 727 }, 728 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 729 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 730 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 731 }, 732 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 733 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 734 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 735 }, 736 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 737 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 738 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 739 }, 740 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 741 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 742 0, 0, 743 }, 744 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 745 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 746 0, 0, 747 }, 748 { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 749 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT), 750 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT), 751 }, 752 { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 753 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT), 754 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT), 755 }, 756 { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 757 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT), 758 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT), 759 }, 760 { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 761 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT), 762 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT), 763 }, 764 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 765 0, 0, 766 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 767 }, 768 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 769 0, 0, 770 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 771 }, 772 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 773 0, 0, 774 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 775 }, 776 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 777 0, 0, 778 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 779 }, 780 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 781 0, 0, 782 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 783 }, 784 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 785 0, 0, 786 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 787 }, 788 789 /* MMHAB Range 2*/ 790 { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 791 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 792 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 793 }, 794 { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 795 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 796 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 797 }, 798 { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 799 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 800 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 801 }, 802 { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 803 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 804 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT), 805 }, 806 { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 807 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 808 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT), 809 }, 810 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 811 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 812 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 813 }, 814 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 815 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 816 0, 0, 817 }, 818 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 819 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 820 0, 0, 821 }, 822 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 823 SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT), 824 0, 0, 825 }, 826 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 827 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 828 0, 0, 829 }, 830 { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 831 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 832 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 833 }, 834 { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 835 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 836 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 837 }, 838 { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 839 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 840 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 841 }, 842 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 843 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 844 0, 0, 845 }, 846 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 847 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 848 0, 0, 849 }, 850 { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 851 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), 852 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), 853 }, 854 { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 855 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT), 856 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT), 857 }, 858 { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 859 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT), 860 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT), 861 }, 862 { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 863 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT), 864 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT), 865 }, 866 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 867 0, 0, 868 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 869 }, 870 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 871 0, 0, 872 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 873 }, 874 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 875 0, 0, 876 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 877 }, 878 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 879 0, 0, 880 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 881 }, 882 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 883 0, 0, 884 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 885 }, 886 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 887 0, 0, 888 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 889 }, 890 891 /* MMHUB Rang 3 */ 892 { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 893 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 894 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 895 }, 896 { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 897 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 898 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 899 }, 900 { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 901 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 902 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 903 }, 904 { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 905 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 906 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT), 907 }, 908 { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 909 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 910 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT), 911 }, 912 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 913 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 914 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 915 }, 916 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 917 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 918 0, 0, 919 }, 920 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 921 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 922 0, 0, 923 }, 924 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 925 SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT), 926 0, 0, 927 }, 928 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 929 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 930 0, 0, 931 }, 932 { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 933 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 934 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 935 }, 936 { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 937 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 938 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 939 }, 940 { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 941 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 942 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 943 }, 944 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 945 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 946 0, 0, 947 }, 948 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 949 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 950 0, 0, 951 }, 952 { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 953 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT), 954 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT), 955 }, 956 { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 957 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT), 958 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT), 959 }, 960 { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 961 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT), 962 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT), 963 }, 964 { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 965 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT), 966 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT), 967 }, 968 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 969 0, 0, 970 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 971 }, 972 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 973 0, 0, 974 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 975 }, 976 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 977 0, 0, 978 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 979 }, 980 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 981 0, 0, 982 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 983 }, 984 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 985 0, 0, 986 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 987 }, 988 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 989 0, 0, 990 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 991 }, 992 993 /* MMHUB Range 4 */ 994 { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 995 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 996 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 997 }, 998 { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 999 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1000 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1001 }, 1002 { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1003 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1004 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1005 }, 1006 { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1007 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1008 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1009 }, 1010 { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1011 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1012 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1013 }, 1014 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1015 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 1016 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 1017 }, 1018 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1019 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1020 0, 0, 1021 }, 1022 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1023 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1024 0, 0, 1025 }, 1026 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1027 SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1028 0, 0, 1029 }, 1030 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 1031 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1032 0, 0, 1033 }, 1034 { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1035 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1036 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1037 }, 1038 { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1039 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1040 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1041 }, 1042 { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1043 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1044 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1045 }, 1046 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1047 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1048 0, 0, 1049 }, 1050 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1051 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1052 0, 0, 1053 }, 1054 { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1055 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1056 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1057 }, 1058 { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1059 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1060 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1061 }, 1062 { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1063 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1064 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1065 }, 1066 { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 1067 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1068 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1069 }, 1070 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1071 0, 0, 1072 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1073 }, 1074 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1075 0, 0, 1076 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1077 }, 1078 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1079 0, 0, 1080 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1081 }, 1082 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1083 0, 0, 1084 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1085 }, 1086 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1087 0, 0, 1088 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1089 }, 1090 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 1091 0, 0, 1092 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1093 }, 1094 1095 /* MMHUAB Range 5 */ 1096 { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1097 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1098 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1099 }, 1100 { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1101 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1102 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1103 }, 1104 { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1105 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1106 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1107 }, 1108 { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1109 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1110 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1111 }, 1112 { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1113 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1114 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1115 }, 1116 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1117 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), 1118 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT), 1119 }, 1120 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1121 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1122 0, 0, 1123 }, 1124 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1125 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1126 0, 0, 1127 }, 1128 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1129 SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1130 0, 0, 1131 }, 1132 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 1133 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1134 0, 0, 1135 }, 1136 { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1137 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1138 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1139 }, 1140 { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1141 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1142 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1143 }, 1144 { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1145 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1146 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1147 }, 1148 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1149 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1150 0, 0, 1151 }, 1152 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1153 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1154 0, 0, 1155 }, 1156 { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1157 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1158 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1159 }, 1160 { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1161 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1162 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1163 }, 1164 { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1165 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1166 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1167 }, 1168 { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 1169 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1170 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1171 }, 1172 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1173 0, 0, 1174 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1175 }, 1176 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1177 0, 0, 1178 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1179 }, 1180 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1181 0, 0, 1182 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1183 }, 1184 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1185 0, 0, 1186 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1187 }, 1188 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1189 0, 0, 1190 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1191 }, 1192 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 1193 0, 0, 1194 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1195 }, 1196 }; 1197 1198 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = { 1199 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 }, 1200 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 }, 1201 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 }, 1202 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 }, 1203 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 }, 1204 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 }, 1205 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 }, 1206 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 }, 1207 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 }, 1208 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 }, 1209 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 }, 1210 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 }, 1211 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 }, 1212 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 }, 1213 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 }, 1214 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 }, 1215 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 }, 1216 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 }, 1217 }; 1218 1219 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev, 1220 const struct soc15_reg_entry *reg, 1221 uint32_t value, 1222 uint32_t *sec_count, 1223 uint32_t *ded_count) 1224 { 1225 uint32_t i; 1226 uint32_t sec_cnt, ded_cnt; 1227 1228 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) { 1229 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset) 1230 continue; 1231 1232 sec_cnt = (value & 1233 mmhub_v1_7_ras_fields[i].sec_count_mask) >> 1234 mmhub_v1_7_ras_fields[i].sec_count_shift; 1235 if (sec_cnt) { 1236 dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n", 1237 mmhub_v1_7_ras_fields[i].name, 1238 sec_cnt); 1239 *sec_count += sec_cnt; 1240 } 1241 1242 ded_cnt = (value & 1243 mmhub_v1_7_ras_fields[i].ded_count_mask) >> 1244 mmhub_v1_7_ras_fields[i].ded_count_shift; 1245 if (ded_cnt) { 1246 dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n", 1247 mmhub_v1_7_ras_fields[i].name, 1248 ded_cnt); 1249 *ded_count += ded_cnt; 1250 } 1251 } 1252 1253 return 0; 1254 } 1255 1256 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev, 1257 void *ras_error_status) 1258 { 1259 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1260 uint32_t sec_count = 0, ded_count = 0; 1261 uint32_t i; 1262 uint32_t reg_value; 1263 1264 err_data->ue_count = 0; 1265 err_data->ce_count = 0; 1266 1267 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) { 1268 reg_value = 1269 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); 1270 if (reg_value) 1271 mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i], 1272 reg_value, &sec_count, &ded_count); 1273 } 1274 1275 err_data->ce_count += sec_count; 1276 err_data->ue_count += ded_count; 1277 } 1278 1279 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev) 1280 { 1281 uint32_t i; 1282 1283 /* write 0 to reset the edc counters */ 1284 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) { 1285 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) 1286 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); 1287 } 1288 } 1289 1290 static const struct soc15_reg_entry mmhub_v1_7_err_status_regs[] = { 1291 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 }, 1292 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 }, 1293 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 }, 1294 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 }, 1295 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 }, 1296 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 }, 1297 }; 1298 1299 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev) 1300 { 1301 int i; 1302 uint32_t reg_value; 1303 1304 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) 1305 return; 1306 1307 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_err_status_regs); i++) { 1308 reg_value = 1309 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_err_status_regs[i])); 1310 if (reg_value) 1311 dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n", 1312 i, reg_value); 1313 } 1314 } 1315 1316 const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = { 1317 .ras_late_init = amdgpu_mmhub_ras_late_init, 1318 .ras_fini = amdgpu_mmhub_ras_fini, 1319 .query_ras_error_count = mmhub_v1_7_query_ras_error_count, 1320 .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count, 1321 .query_ras_error_status = mmhub_v1_7_query_ras_error_status, 1322 }; 1323 1324 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = { 1325 .get_fb_location = mmhub_v1_7_get_fb_location, 1326 .init = mmhub_v1_7_init, 1327 .gart_enable = mmhub_v1_7_gart_enable, 1328 .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default, 1329 .gart_disable = mmhub_v1_7_gart_disable, 1330 .set_clockgating = mmhub_v1_7_set_clockgating, 1331 .get_clockgating = mmhub_v1_7_get_clockgating, 1332 .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs, 1333 }; 1334