1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v1_0.h" 25 26 #include "mmhub/mmhub_1_0_offset.h" 27 #include "mmhub/mmhub_1_0_sh_mask.h" 28 #include "mmhub/mmhub_1_0_default.h" 29 #include "athub/athub_1_0_offset.h" 30 #include "athub/athub_1_0_sh_mask.h" 31 #include "vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #define mmDAGB0_CNTL_MISC2_RV 0x008f 36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 37 38 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 39 { 40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 41 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); 42 43 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 44 base <<= 24; 45 46 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 47 top <<= 24; 48 49 adev->gmc.fb_start = base; 50 adev->gmc.fb_end = top; 51 52 return base; 53 } 54 55 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 56 uint64_t page_table_base) 57 { 58 /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */ 59 int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 60 - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 61 62 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 63 offset * vmid, lower_32_bits(page_table_base)); 64 65 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 66 offset * vmid, upper_32_bits(page_table_base)); 67 } 68 69 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 70 { 71 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 72 73 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 74 75 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 76 (u32)(adev->gmc.gart_start >> 12)); 77 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 78 (u32)(adev->gmc.gart_start >> 44)); 79 80 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 81 (u32)(adev->gmc.gart_end >> 12)); 82 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 83 (u32)(adev->gmc.gart_end >> 44)); 84 } 85 86 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 87 { 88 uint64_t value; 89 uint32_t tmp; 90 91 /* Program the AGP BAR */ 92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 94 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 95 96 /* Program the system aperture low logical page number. */ 97 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 98 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 99 100 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) 101 /* 102 * Raven2 has a HW issue that it is unable to use the vram which 103 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 104 * workaround that increase system aperture high address (add 1) 105 * to get rid of the VM fault and hardware hang. 106 */ 107 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 108 max((adev->gmc.fb_end >> 18) + 0x1, 109 adev->gmc.agp_end >> 18)); 110 else 111 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 112 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 113 114 /* Set default page address. */ 115 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 116 adev->vm_manager.vram_base_offset; 117 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 118 (u32)(value >> 12)); 119 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 120 (u32)(value >> 44)); 121 122 /* Program "protection fault". */ 123 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 124 (u32)(adev->dummy_page_addr >> 12)); 125 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 126 (u32)((u64)adev->dummy_page_addr >> 44)); 127 128 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 129 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 130 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 131 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 132 } 133 134 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 135 { 136 uint32_t tmp; 137 138 /* Setup TLB control */ 139 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 140 141 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 144 ENABLE_ADVANCED_DRIVER_MODEL, 1); 145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 146 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 147 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 149 MTYPE, MTYPE_UC);/* XXX for emulation. */ 150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 151 152 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 153 } 154 155 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 156 { 157 uint32_t tmp; 158 159 /* Setup L2 cache */ 160 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 161 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 163 /* XXX for emulation, Refer to closed source code.*/ 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 165 0); 166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 169 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 170 171 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 173 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 174 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 175 176 if (adev->gmc.translate_further) { 177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 179 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 180 } else { 181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 183 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 184 } 185 186 tmp = mmVM_L2_CNTL4_DEFAULT; 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 189 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 190 } 191 192 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 193 { 194 uint32_t tmp; 195 196 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 197 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 198 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 199 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 200 } 201 202 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 203 { 204 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 205 0XFFFFFFFF); 206 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 207 0x0000000F); 208 209 WREG32_SOC15(MMHUB, 0, 210 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 211 WREG32_SOC15(MMHUB, 0, 212 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 213 214 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 215 0); 216 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 217 0); 218 } 219 220 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 221 { 222 unsigned num_level, block_size; 223 uint32_t tmp; 224 int i; 225 226 num_level = adev->vm_manager.num_level; 227 block_size = adev->vm_manager.block_size; 228 if (adev->gmc.translate_further) 229 num_level -= 1; 230 else 231 block_size -= 9; 232 233 for (i = 0; i <= 14; i++) { 234 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); 235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 237 num_level); 238 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 239 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 241 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 242 1); 243 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 244 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 245 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 246 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 247 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 248 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 249 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 250 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 252 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 253 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 254 PAGE_TABLE_BLOCK_SIZE, 255 block_size); 256 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 257 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 258 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 259 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); 260 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 261 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 262 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 263 lower_32_bits(adev->vm_manager.max_pfn - 1)); 264 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 265 upper_32_bits(adev->vm_manager.max_pfn - 1)); 266 } 267 } 268 269 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 270 { 271 unsigned i; 272 273 for (i = 0; i < 18; ++i) { 274 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 275 2 * i, 0xffffffff); 276 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 277 2 * i, 0x1f); 278 } 279 } 280 281 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 282 bool enable) 283 { 284 if (amdgpu_sriov_vf(adev)) 285 return; 286 287 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { 288 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu) 289 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true); 290 291 } 292 } 293 294 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 295 { 296 if (amdgpu_sriov_vf(adev)) { 297 /* 298 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 299 * VF copy registers so vbios post doesn't program them, for 300 * SRIOV driver need to program them 301 */ 302 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 303 adev->gmc.vram_start >> 24); 304 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 305 adev->gmc.vram_end >> 24); 306 } 307 308 /* GART Enable. */ 309 mmhub_v1_0_init_gart_aperture_regs(adev); 310 mmhub_v1_0_init_system_aperture_regs(adev); 311 mmhub_v1_0_init_tlb_regs(adev); 312 mmhub_v1_0_init_cache_regs(adev); 313 314 mmhub_v1_0_enable_system_domain(adev); 315 mmhub_v1_0_disable_identity_aperture(adev); 316 mmhub_v1_0_setup_vmid_config(adev); 317 mmhub_v1_0_program_invalidation(adev); 318 319 return 0; 320 } 321 322 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 323 { 324 u32 tmp; 325 u32 i; 326 327 /* Disable all tables */ 328 for (i = 0; i < 16; i++) 329 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); 330 331 /* Setup TLB control */ 332 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 333 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 334 tmp = REG_SET_FIELD(tmp, 335 MC_VM_MX_L1_TLB_CNTL, 336 ENABLE_ADVANCED_DRIVER_MODEL, 337 0); 338 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 339 340 /* Setup L2 cache */ 341 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 342 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 343 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 344 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 345 } 346 347 /** 348 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 349 * 350 * @adev: amdgpu_device pointer 351 * @value: true redirects VM faults to the default page 352 */ 353 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 354 { 355 u32 tmp; 356 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 357 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 358 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 359 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 360 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 361 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 362 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 363 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 364 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 365 tmp = REG_SET_FIELD(tmp, 366 VM_L2_PROTECTION_FAULT_CNTL, 367 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 368 value); 369 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 370 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 371 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 372 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 373 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 374 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 375 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 376 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 377 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 378 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 380 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 381 if (!value) { 382 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 383 CRASH_ON_NO_RETRY_FAULT, 1); 384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 385 CRASH_ON_RETRY_FAULT, 1); 386 } 387 388 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 389 } 390 391 void mmhub_v1_0_init(struct amdgpu_device *adev) 392 { 393 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 394 395 hub->ctx0_ptb_addr_lo32 = 396 SOC15_REG_OFFSET(MMHUB, 0, 397 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 398 hub->ctx0_ptb_addr_hi32 = 399 SOC15_REG_OFFSET(MMHUB, 0, 400 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 401 hub->vm_inv_eng0_req = 402 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 403 hub->vm_inv_eng0_ack = 404 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 405 hub->vm_context0_cntl = 406 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 407 hub->vm_l2_pro_fault_status = 408 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 409 hub->vm_l2_pro_fault_cntl = 410 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 411 412 } 413 414 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 415 bool enable) 416 { 417 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 418 419 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 420 421 if (adev->asic_type != CHIP_RAVEN) { 422 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 423 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 424 } else 425 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 426 427 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 428 data |= ATC_L2_MISC_CG__ENABLE_MASK; 429 430 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 431 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 432 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 433 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 434 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 435 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 436 437 if (adev->asic_type != CHIP_RAVEN) 438 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 439 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 440 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 441 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 442 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 443 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 444 } else { 445 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 446 447 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 448 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 449 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 450 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 451 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 452 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 453 454 if (adev->asic_type != CHIP_RAVEN) 455 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 456 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 457 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 458 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 459 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 460 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 461 } 462 463 if (def != data) 464 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 465 466 if (def1 != data1) { 467 if (adev->asic_type != CHIP_RAVEN) 468 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 469 else 470 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 471 } 472 473 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 474 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 475 } 476 477 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 478 bool enable) 479 { 480 uint32_t def, data; 481 482 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 483 484 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 485 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 486 else 487 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 488 489 if (def != data) 490 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 491 } 492 493 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 494 bool enable) 495 { 496 uint32_t def, data; 497 498 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 499 500 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 501 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 502 else 503 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 504 505 if (def != data) 506 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 507 } 508 509 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 510 bool enable) 511 { 512 uint32_t def, data; 513 514 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 515 516 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 517 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 518 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 519 else 520 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 521 522 if(def != data) 523 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 524 } 525 526 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 527 enum amd_clockgating_state state) 528 { 529 if (amdgpu_sriov_vf(adev)) 530 return 0; 531 532 switch (adev->asic_type) { 533 case CHIP_VEGA10: 534 case CHIP_VEGA12: 535 case CHIP_VEGA20: 536 case CHIP_RAVEN: 537 mmhub_v1_0_update_medium_grain_clock_gating(adev, 538 state == AMD_CG_STATE_GATE ? true : false); 539 athub_update_medium_grain_clock_gating(adev, 540 state == AMD_CG_STATE_GATE ? true : false); 541 mmhub_v1_0_update_medium_grain_light_sleep(adev, 542 state == AMD_CG_STATE_GATE ? true : false); 543 athub_update_medium_grain_light_sleep(adev, 544 state == AMD_CG_STATE_GATE ? true : false); 545 break; 546 default: 547 break; 548 } 549 550 return 0; 551 } 552 553 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 554 { 555 int data; 556 557 if (amdgpu_sriov_vf(adev)) 558 *flags = 0; 559 560 /* AMD_CG_SUPPORT_MC_MGCG */ 561 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 562 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 563 *flags |= AMD_CG_SUPPORT_MC_MGCG; 564 565 /* AMD_CG_SUPPORT_MC_LS */ 566 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 567 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 568 *flags |= AMD_CG_SUPPORT_MC_LS; 569 } 570