1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v1_0.h" 25 26 #include "mmhub/mmhub_1_0_offset.h" 27 #include "mmhub/mmhub_1_0_sh_mask.h" 28 #include "mmhub/mmhub_1_0_default.h" 29 #include "athub/athub_1_0_offset.h" 30 #include "athub/athub_1_0_sh_mask.h" 31 #include "vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #define mmDAGB0_CNTL_MISC2_RV 0x008f 36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 37 38 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 39 { 40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 41 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); 42 43 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 44 base <<= 24; 45 46 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 47 top <<= 24; 48 49 adev->gmc.fb_start = base; 50 adev->gmc.fb_end = top; 51 52 return base; 53 } 54 55 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 56 uint64_t page_table_base) 57 { 58 /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */ 59 int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 60 - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 61 62 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 63 offset * vmid, lower_32_bits(page_table_base)); 64 65 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 66 offset * vmid, upper_32_bits(page_table_base)); 67 } 68 69 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 70 { 71 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 72 73 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 74 75 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 76 (u32)(adev->gmc.gart_start >> 12)); 77 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 78 (u32)(adev->gmc.gart_start >> 44)); 79 80 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 81 (u32)(adev->gmc.gart_end >> 12)); 82 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 83 (u32)(adev->gmc.gart_end >> 44)); 84 } 85 86 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 87 { 88 uint64_t value; 89 uint32_t tmp; 90 91 /* Program the AGP BAR */ 92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 94 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 95 96 /* Program the system aperture low logical page number. */ 97 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 98 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 99 100 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) 101 /* 102 * Raven2 has a HW issue that it is unable to use the vram which 103 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 104 * workaround that increase system aperture high address (add 1) 105 * to get rid of the VM fault and hardware hang. 106 */ 107 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 108 max((adev->gmc.fb_end >> 18) + 0x1, 109 adev->gmc.agp_end >> 18)); 110 else 111 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 112 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 113 114 if (amdgpu_virt_support_skip_setting(adev)) 115 return; 116 117 /* Set default page address. */ 118 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 119 adev->vm_manager.vram_base_offset; 120 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 121 (u32)(value >> 12)); 122 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 123 (u32)(value >> 44)); 124 125 /* Program "protection fault". */ 126 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 127 (u32)(adev->dummy_page_addr >> 12)); 128 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 129 (u32)((u64)adev->dummy_page_addr >> 44)); 130 131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 133 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 134 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 135 } 136 137 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 138 { 139 uint32_t tmp; 140 141 /* Setup TLB control */ 142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 143 144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 147 ENABLE_ADVANCED_DRIVER_MODEL, 1); 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 149 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 151 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 152 MTYPE, MTYPE_UC);/* XXX for emulation. */ 153 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 154 155 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 156 } 157 158 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 159 { 160 uint32_t tmp; 161 162 if (amdgpu_virt_support_skip_setting(adev)) 163 return; 164 165 /* Setup L2 cache */ 166 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 169 /* XXX for emulation, Refer to closed source code.*/ 170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 171 0); 172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 173 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 174 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 175 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 176 177 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 179 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 180 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 181 182 if (adev->gmc.translate_further) { 183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 185 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 186 } else { 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 189 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 190 } 191 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); 192 193 tmp = mmVM_L2_CNTL4_DEFAULT; 194 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 197 } 198 199 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 200 { 201 uint32_t tmp; 202 203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 205 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 206 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 207 } 208 209 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 210 { 211 if (amdgpu_virt_support_skip_setting(adev)) 212 return; 213 214 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 215 0XFFFFFFFF); 216 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 217 0x0000000F); 218 219 WREG32_SOC15(MMHUB, 0, 220 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 221 WREG32_SOC15(MMHUB, 0, 222 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 223 224 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 225 0); 226 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 227 0); 228 } 229 230 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 231 { 232 unsigned num_level, block_size; 233 uint32_t tmp; 234 int i; 235 236 num_level = adev->vm_manager.num_level; 237 block_size = adev->vm_manager.block_size; 238 if (adev->gmc.translate_further) 239 num_level -= 1; 240 else 241 block_size -= 9; 242 243 for (i = 0; i <= 14; i++) { 244 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); 245 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 247 num_level); 248 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 249 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 250 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 251 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 252 1); 253 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 254 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 255 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 256 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 257 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 258 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 259 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 260 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 261 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 262 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 263 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 264 PAGE_TABLE_BLOCK_SIZE, 265 block_size); 266 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 267 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 268 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1); 269 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); 270 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 271 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 272 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 273 lower_32_bits(adev->vm_manager.max_pfn - 1)); 274 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 275 upper_32_bits(adev->vm_manager.max_pfn - 1)); 276 } 277 } 278 279 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 280 { 281 unsigned i; 282 283 for (i = 0; i < 18; ++i) { 284 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 285 2 * i, 0xffffffff); 286 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 287 2 * i, 0x1f); 288 } 289 } 290 291 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 292 bool enable) 293 { 294 if (amdgpu_sriov_vf(adev)) 295 return; 296 297 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { 298 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu) 299 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true); 300 301 } 302 } 303 304 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 305 { 306 if (amdgpu_sriov_vf(adev)) { 307 /* 308 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 309 * VF copy registers so vbios post doesn't program them, for 310 * SRIOV driver need to program them 311 */ 312 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 313 adev->gmc.vram_start >> 24); 314 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 315 adev->gmc.vram_end >> 24); 316 } 317 318 /* GART Enable. */ 319 mmhub_v1_0_init_gart_aperture_regs(adev); 320 mmhub_v1_0_init_system_aperture_regs(adev); 321 mmhub_v1_0_init_tlb_regs(adev); 322 mmhub_v1_0_init_cache_regs(adev); 323 324 mmhub_v1_0_enable_system_domain(adev); 325 mmhub_v1_0_disable_identity_aperture(adev); 326 mmhub_v1_0_setup_vmid_config(adev); 327 mmhub_v1_0_program_invalidation(adev); 328 329 return 0; 330 } 331 332 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 333 { 334 u32 tmp; 335 u32 i; 336 337 /* Disable all tables */ 338 for (i = 0; i < 16; i++) 339 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); 340 341 /* Setup TLB control */ 342 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 343 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 344 tmp = REG_SET_FIELD(tmp, 345 MC_VM_MX_L1_TLB_CNTL, 346 ENABLE_ADVANCED_DRIVER_MODEL, 347 0); 348 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 349 350 if (!amdgpu_virt_support_skip_setting(adev)) { 351 /* Setup L2 cache */ 352 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 353 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 354 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 355 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 356 } 357 } 358 359 /** 360 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 361 * 362 * @adev: amdgpu_device pointer 363 * @value: true redirects VM faults to the default page 364 */ 365 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 366 { 367 u32 tmp; 368 369 if (amdgpu_virt_support_skip_setting(adev)) 370 return; 371 372 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 373 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 374 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 375 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 376 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 377 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 378 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 380 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 381 tmp = REG_SET_FIELD(tmp, 382 VM_L2_PROTECTION_FAULT_CNTL, 383 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 384 value); 385 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 386 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 387 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 388 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 389 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 390 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 391 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 392 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 393 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 394 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 395 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 396 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 397 if (!value) { 398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 399 CRASH_ON_NO_RETRY_FAULT, 1); 400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 401 CRASH_ON_RETRY_FAULT, 1); 402 } 403 404 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 405 } 406 407 void mmhub_v1_0_init(struct amdgpu_device *adev) 408 { 409 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 410 411 hub->ctx0_ptb_addr_lo32 = 412 SOC15_REG_OFFSET(MMHUB, 0, 413 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 414 hub->ctx0_ptb_addr_hi32 = 415 SOC15_REG_OFFSET(MMHUB, 0, 416 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 417 hub->vm_inv_eng0_req = 418 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 419 hub->vm_inv_eng0_ack = 420 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 421 hub->vm_context0_cntl = 422 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 423 hub->vm_l2_pro_fault_status = 424 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 425 hub->vm_l2_pro_fault_cntl = 426 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 427 428 } 429 430 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 431 bool enable) 432 { 433 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 434 435 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 436 437 if (adev->asic_type != CHIP_RAVEN) { 438 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 439 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 440 } else 441 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 442 443 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 444 data |= ATC_L2_MISC_CG__ENABLE_MASK; 445 446 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 447 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 448 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 449 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 450 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 451 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 452 453 if (adev->asic_type != CHIP_RAVEN) 454 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 455 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 456 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 457 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 458 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 459 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 460 } else { 461 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 462 463 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 464 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 465 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 466 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 467 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 468 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 469 470 if (adev->asic_type != CHIP_RAVEN) 471 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 472 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 473 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 474 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 475 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 476 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 477 } 478 479 if (def != data) 480 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 481 482 if (def1 != data1) { 483 if (adev->asic_type != CHIP_RAVEN) 484 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 485 else 486 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 487 } 488 489 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 490 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 491 } 492 493 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 494 bool enable) 495 { 496 uint32_t def, data; 497 498 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 499 500 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 501 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 502 else 503 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 504 505 if (def != data) 506 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 507 } 508 509 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 510 bool enable) 511 { 512 uint32_t def, data; 513 514 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 515 516 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 517 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 518 else 519 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 520 521 if (def != data) 522 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 523 } 524 525 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 526 bool enable) 527 { 528 uint32_t def, data; 529 530 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 531 532 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 533 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 534 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 535 else 536 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 537 538 if(def != data) 539 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 540 } 541 542 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 543 enum amd_clockgating_state state) 544 { 545 if (amdgpu_sriov_vf(adev)) 546 return 0; 547 548 switch (adev->asic_type) { 549 case CHIP_VEGA10: 550 case CHIP_VEGA12: 551 case CHIP_VEGA20: 552 case CHIP_RAVEN: 553 mmhub_v1_0_update_medium_grain_clock_gating(adev, 554 state == AMD_CG_STATE_GATE ? true : false); 555 athub_update_medium_grain_clock_gating(adev, 556 state == AMD_CG_STATE_GATE ? true : false); 557 mmhub_v1_0_update_medium_grain_light_sleep(adev, 558 state == AMD_CG_STATE_GATE ? true : false); 559 athub_update_medium_grain_light_sleep(adev, 560 state == AMD_CG_STATE_GATE ? true : false); 561 break; 562 default: 563 break; 564 } 565 566 return 0; 567 } 568 569 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 570 { 571 int data; 572 573 if (amdgpu_sriov_vf(adev)) 574 *flags = 0; 575 576 /* AMD_CG_SUPPORT_MC_MGCG */ 577 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 578 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 579 *flags |= AMD_CG_SUPPORT_MC_MGCG; 580 581 /* AMD_CG_SUPPORT_MC_LS */ 582 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 583 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 584 *flags |= AMD_CG_SUPPORT_MC_LS; 585 } 586