1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 45 46 static int mes_v11_0_hw_fini(void *handle); 47 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 48 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 49 50 #define MES_EOP_SIZE 2048 51 52 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 53 { 54 struct amdgpu_device *adev = ring->adev; 55 56 if (ring->use_doorbell) { 57 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 58 ring->wptr); 59 WDOORBELL64(ring->doorbell_index, ring->wptr); 60 } else { 61 BUG(); 62 } 63 } 64 65 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 66 { 67 return *ring->rptr_cpu_addr; 68 } 69 70 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 71 { 72 u64 wptr; 73 74 if (ring->use_doorbell) 75 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 76 else 77 BUG(); 78 return wptr; 79 } 80 81 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 82 .type = AMDGPU_RING_TYPE_MES, 83 .align_mask = 1, 84 .nop = 0, 85 .support_64bit_ptrs = true, 86 .get_rptr = mes_v11_0_ring_get_rptr, 87 .get_wptr = mes_v11_0_ring_get_wptr, 88 .set_wptr = mes_v11_0_ring_set_wptr, 89 .insert_nop = amdgpu_ring_insert_nop, 90 }; 91 92 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 93 void *pkt, int size, 94 int api_status_off) 95 { 96 int ndw = size / 4; 97 signed long r; 98 union MESAPI__ADD_QUEUE *x_pkt = pkt; 99 struct MES_API_STATUS *api_status; 100 struct amdgpu_device *adev = mes->adev; 101 struct amdgpu_ring *ring = &mes->ring; 102 unsigned long flags; 103 signed long timeout = adev->usec_timeout; 104 105 if (amdgpu_emu_mode) { 106 timeout *= 100; 107 } else if (amdgpu_sriov_vf(adev)) { 108 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 109 timeout = 15 * 600 * 1000; 110 } 111 BUG_ON(size % 4 != 0); 112 113 spin_lock_irqsave(&mes->ring_lock, flags); 114 if (amdgpu_ring_alloc(ring, ndw)) { 115 spin_unlock_irqrestore(&mes->ring_lock, flags); 116 return -ENOMEM; 117 } 118 119 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 120 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 121 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 122 123 amdgpu_ring_write_multiple(ring, pkt, ndw); 124 amdgpu_ring_commit(ring); 125 spin_unlock_irqrestore(&mes->ring_lock, flags); 126 127 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 128 129 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 130 timeout); 131 if (r < 1) { 132 DRM_ERROR("MES failed to response msg=%d\n", 133 x_pkt->header.opcode); 134 135 while (halt_if_hws_hang) 136 schedule(); 137 138 return -ETIMEDOUT; 139 } 140 141 return 0; 142 } 143 144 static int convert_to_mes_queue_type(int queue_type) 145 { 146 if (queue_type == AMDGPU_RING_TYPE_GFX) 147 return MES_QUEUE_TYPE_GFX; 148 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 149 return MES_QUEUE_TYPE_COMPUTE; 150 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 151 return MES_QUEUE_TYPE_SDMA; 152 else 153 BUG(); 154 return -1; 155 } 156 157 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 158 struct mes_add_queue_input *input) 159 { 160 struct amdgpu_device *adev = mes->adev; 161 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 162 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 163 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 164 165 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 166 167 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 168 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 169 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 170 171 mes_add_queue_pkt.process_id = input->process_id; 172 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 173 mes_add_queue_pkt.process_va_start = input->process_va_start; 174 mes_add_queue_pkt.process_va_end = input->process_va_end; 175 mes_add_queue_pkt.process_quantum = input->process_quantum; 176 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 177 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 178 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 179 mes_add_queue_pkt.inprocess_gang_priority = 180 input->inprocess_gang_priority; 181 mes_add_queue_pkt.gang_global_priority_level = 182 input->gang_global_priority_level; 183 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 184 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 185 186 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 187 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 188 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 189 else 190 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 191 192 mes_add_queue_pkt.queue_type = 193 convert_to_mes_queue_type(input->queue_type); 194 mes_add_queue_pkt.paging = input->paging; 195 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 196 mes_add_queue_pkt.gws_base = input->gws_base; 197 mes_add_queue_pkt.gws_size = input->gws_size; 198 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 199 mes_add_queue_pkt.tma_addr = input->tma_addr; 200 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 201 202 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 203 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 204 mes_add_queue_pkt.gds_size = input->queue_size; 205 206 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 207 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 208 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 209 mes_add_queue_pkt.trap_en = 1; 210 211 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 212 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 213 mes_add_queue_pkt.gds_size = input->queue_size; 214 215 return mes_v11_0_submit_pkt_and_poll_completion(mes, 216 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 217 offsetof(union MESAPI__ADD_QUEUE, api_status)); 218 } 219 220 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 221 struct mes_remove_queue_input *input) 222 { 223 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 224 225 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 226 227 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 228 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 229 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 230 231 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 232 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 233 234 return mes_v11_0_submit_pkt_and_poll_completion(mes, 235 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 236 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 237 } 238 239 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 240 struct mes_unmap_legacy_queue_input *input) 241 { 242 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 243 244 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 245 246 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 247 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 248 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 249 250 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 251 mes_remove_queue_pkt.gang_context_addr = 0; 252 253 mes_remove_queue_pkt.pipe_id = input->pipe_id; 254 mes_remove_queue_pkt.queue_id = input->queue_id; 255 256 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 257 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 258 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 259 mes_remove_queue_pkt.tf_data = 260 lower_32_bits(input->trail_fence_data); 261 } else { 262 mes_remove_queue_pkt.unmap_legacy_queue = 1; 263 mes_remove_queue_pkt.queue_type = 264 convert_to_mes_queue_type(input->queue_type); 265 } 266 267 return mes_v11_0_submit_pkt_and_poll_completion(mes, 268 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 269 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 270 } 271 272 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 273 struct mes_suspend_gang_input *input) 274 { 275 return 0; 276 } 277 278 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 279 struct mes_resume_gang_input *input) 280 { 281 return 0; 282 } 283 284 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 285 { 286 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 287 288 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 289 290 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 291 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 292 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 293 294 return mes_v11_0_submit_pkt_and_poll_completion(mes, 295 &mes_status_pkt, sizeof(mes_status_pkt), 296 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 297 } 298 299 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 300 struct mes_misc_op_input *input) 301 { 302 union MESAPI__MISC misc_pkt; 303 304 memset(&misc_pkt, 0, sizeof(misc_pkt)); 305 306 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 307 misc_pkt.header.opcode = MES_SCH_API_MISC; 308 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 309 310 switch (input->op) { 311 case MES_MISC_OP_READ_REG: 312 misc_pkt.opcode = MESAPI_MISC__READ_REG; 313 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 314 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 315 break; 316 case MES_MISC_OP_WRITE_REG: 317 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 318 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 319 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 320 break; 321 case MES_MISC_OP_WRM_REG_WAIT: 322 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 323 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 324 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 325 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 326 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 327 misc_pkt.wait_reg_mem.reg_offset2 = 0; 328 break; 329 case MES_MISC_OP_WRM_REG_WR_WAIT: 330 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 331 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 332 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 333 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 334 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 335 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 336 break; 337 default: 338 DRM_ERROR("unsupported misc op (%d) \n", input->op); 339 return -EINVAL; 340 } 341 342 return mes_v11_0_submit_pkt_and_poll_completion(mes, 343 &misc_pkt, sizeof(misc_pkt), 344 offsetof(union MESAPI__MISC, api_status)); 345 } 346 347 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 348 { 349 int i; 350 struct amdgpu_device *adev = mes->adev; 351 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 352 353 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 354 355 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 356 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 357 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 358 359 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 360 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 361 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 362 mes_set_hw_res_pkt.paging_vmid = 0; 363 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 364 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 365 mes->query_status_fence_gpu_addr; 366 367 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 368 mes_set_hw_res_pkt.compute_hqd_mask[i] = 369 mes->compute_hqd_mask[i]; 370 371 for (i = 0; i < MAX_GFX_PIPES; i++) 372 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 373 374 for (i = 0; i < MAX_SDMA_PIPES; i++) 375 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 376 377 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 378 mes_set_hw_res_pkt.aggregated_doorbells[i] = 379 mes->aggregated_doorbells[i]; 380 381 for (i = 0; i < 5; i++) { 382 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 383 mes_set_hw_res_pkt.mmhub_base[i] = 384 adev->reg_offset[MMHUB_HWIP][0][i]; 385 mes_set_hw_res_pkt.osssys_base[i] = 386 adev->reg_offset[OSSSYS_HWIP][0][i]; 387 } 388 389 mes_set_hw_res_pkt.disable_reset = 1; 390 mes_set_hw_res_pkt.disable_mes_log = 1; 391 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 392 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 393 mes_set_hw_res_pkt.oversubscription_timer = 50; 394 395 return mes_v11_0_submit_pkt_and_poll_completion(mes, 396 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 397 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 398 } 399 400 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 401 { 402 struct amdgpu_device *adev = mes->adev; 403 uint32_t data; 404 405 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 406 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 407 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 408 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 409 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 410 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 411 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 412 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 413 414 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 415 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 416 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 417 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 418 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 419 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 420 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 421 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 422 423 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 424 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 425 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 426 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 427 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 428 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 429 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 430 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 431 432 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 433 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 434 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 435 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 436 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 437 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 438 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 439 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 440 441 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 442 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 443 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 444 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 445 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 446 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 447 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 448 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 449 450 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 451 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 452 } 453 454 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 455 .add_hw_queue = mes_v11_0_add_hw_queue, 456 .remove_hw_queue = mes_v11_0_remove_hw_queue, 457 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 458 .suspend_gang = mes_v11_0_suspend_gang, 459 .resume_gang = mes_v11_0_resume_gang, 460 .misc_op = mes_v11_0_misc_op, 461 }; 462 463 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 464 enum admgpu_mes_pipe pipe) 465 { 466 int r; 467 const struct mes_firmware_header_v1_0 *mes_hdr; 468 const __le32 *fw_data; 469 unsigned fw_size; 470 471 mes_hdr = (const struct mes_firmware_header_v1_0 *) 472 adev->mes.fw[pipe]->data; 473 474 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 475 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 476 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 477 478 r = amdgpu_bo_create_reserved(adev, fw_size, 479 PAGE_SIZE, 480 AMDGPU_GEM_DOMAIN_VRAM | 481 AMDGPU_GEM_DOMAIN_GTT, 482 &adev->mes.ucode_fw_obj[pipe], 483 &adev->mes.ucode_fw_gpu_addr[pipe], 484 (void **)&adev->mes.ucode_fw_ptr[pipe]); 485 if (r) { 486 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 487 return r; 488 } 489 490 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 491 492 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 493 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 494 495 return 0; 496 } 497 498 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 499 enum admgpu_mes_pipe pipe) 500 { 501 int r; 502 const struct mes_firmware_header_v1_0 *mes_hdr; 503 const __le32 *fw_data; 504 unsigned fw_size; 505 506 mes_hdr = (const struct mes_firmware_header_v1_0 *) 507 adev->mes.fw[pipe]->data; 508 509 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 510 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 511 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 512 513 r = amdgpu_bo_create_reserved(adev, fw_size, 514 64 * 1024, 515 AMDGPU_GEM_DOMAIN_VRAM | 516 AMDGPU_GEM_DOMAIN_GTT, 517 &adev->mes.data_fw_obj[pipe], 518 &adev->mes.data_fw_gpu_addr[pipe], 519 (void **)&adev->mes.data_fw_ptr[pipe]); 520 if (r) { 521 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 522 return r; 523 } 524 525 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 526 527 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 528 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 529 530 return 0; 531 } 532 533 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 534 enum admgpu_mes_pipe pipe) 535 { 536 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 537 &adev->mes.data_fw_gpu_addr[pipe], 538 (void **)&adev->mes.data_fw_ptr[pipe]); 539 540 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 541 &adev->mes.ucode_fw_gpu_addr[pipe], 542 (void **)&adev->mes.ucode_fw_ptr[pipe]); 543 } 544 545 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 546 { 547 uint64_t ucode_addr; 548 uint32_t pipe, data = 0; 549 550 if (enable) { 551 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 552 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 553 data = REG_SET_FIELD(data, CP_MES_CNTL, 554 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 555 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 556 557 mutex_lock(&adev->srbm_mutex); 558 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 559 if (!adev->enable_mes_kiq && 560 pipe == AMDGPU_MES_KIQ_PIPE) 561 continue; 562 563 soc21_grbm_select(adev, 3, pipe, 0, 0); 564 565 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 566 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 567 lower_32_bits(ucode_addr)); 568 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 569 upper_32_bits(ucode_addr)); 570 } 571 soc21_grbm_select(adev, 0, 0, 0, 0); 572 mutex_unlock(&adev->srbm_mutex); 573 574 /* unhalt MES and activate pipe0 */ 575 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 576 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 577 adev->enable_mes_kiq ? 1 : 0); 578 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 579 580 if (amdgpu_emu_mode) 581 msleep(100); 582 else 583 udelay(50); 584 } else { 585 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 586 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 587 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 588 data = REG_SET_FIELD(data, CP_MES_CNTL, 589 MES_INVALIDATE_ICACHE, 1); 590 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 591 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 592 adev->enable_mes_kiq ? 1 : 0); 593 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 594 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 595 } 596 } 597 598 /* This function is for backdoor MES firmware */ 599 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 600 enum admgpu_mes_pipe pipe, bool prime_icache) 601 { 602 int r; 603 uint32_t data; 604 uint64_t ucode_addr; 605 606 mes_v11_0_enable(adev, false); 607 608 if (!adev->mes.fw[pipe]) 609 return -EINVAL; 610 611 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 612 if (r) 613 return r; 614 615 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 616 if (r) { 617 mes_v11_0_free_ucode_buffers(adev, pipe); 618 return r; 619 } 620 621 mutex_lock(&adev->srbm_mutex); 622 /* me=3, pipe=0, queue=0 */ 623 soc21_grbm_select(adev, 3, pipe, 0, 0); 624 625 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 626 627 /* set ucode start address */ 628 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 629 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 630 lower_32_bits(ucode_addr)); 631 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 632 upper_32_bits(ucode_addr)); 633 634 /* set ucode fimrware address */ 635 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 636 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 637 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 638 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 639 640 /* set ucode instruction cache boundary to 2M-1 */ 641 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 642 643 /* set ucode data firmware address */ 644 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 645 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 646 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 647 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 648 649 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 650 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 651 652 if (prime_icache) { 653 /* invalidate ICACHE */ 654 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 655 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 656 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 657 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 658 659 /* prime the ICACHE. */ 660 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 661 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 662 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 663 } 664 665 soc21_grbm_select(adev, 0, 0, 0, 0); 666 mutex_unlock(&adev->srbm_mutex); 667 668 return 0; 669 } 670 671 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 672 enum admgpu_mes_pipe pipe) 673 { 674 int r; 675 u32 *eop; 676 677 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 678 AMDGPU_GEM_DOMAIN_GTT, 679 &adev->mes.eop_gpu_obj[pipe], 680 &adev->mes.eop_gpu_addr[pipe], 681 (void **)&eop); 682 if (r) { 683 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 684 return r; 685 } 686 687 memset(eop, 0, 688 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 689 690 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 691 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 692 693 return 0; 694 } 695 696 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 697 { 698 struct v11_compute_mqd *mqd = ring->mqd_ptr; 699 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 700 uint32_t tmp; 701 702 mqd->header = 0xC0310800; 703 mqd->compute_pipelinestat_enable = 0x00000001; 704 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 705 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 706 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 707 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 708 mqd->compute_misc_reserved = 0x00000007; 709 710 eop_base_addr = ring->eop_gpu_addr >> 8; 711 712 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 713 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 714 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 715 (order_base_2(MES_EOP_SIZE / 4) - 1)); 716 717 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 718 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 719 mqd->cp_hqd_eop_control = tmp; 720 721 /* disable the queue if it's active */ 722 ring->wptr = 0; 723 mqd->cp_hqd_pq_rptr = 0; 724 mqd->cp_hqd_pq_wptr_lo = 0; 725 mqd->cp_hqd_pq_wptr_hi = 0; 726 727 /* set the pointer to the MQD */ 728 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 729 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 730 731 /* set MQD vmid to 0 */ 732 tmp = regCP_MQD_CONTROL_DEFAULT; 733 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 734 mqd->cp_mqd_control = tmp; 735 736 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 737 hqd_gpu_addr = ring->gpu_addr >> 8; 738 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 739 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 740 741 /* set the wb address whether it's enabled or not */ 742 wb_gpu_addr = ring->rptr_gpu_addr; 743 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 744 mqd->cp_hqd_pq_rptr_report_addr_hi = 745 upper_32_bits(wb_gpu_addr) & 0xffff; 746 747 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 748 wb_gpu_addr = ring->wptr_gpu_addr; 749 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 750 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 751 752 /* set up the HQD, this is similar to CP_RB0_CNTL */ 753 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 754 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 755 (order_base_2(ring->ring_size / 4) - 1)); 756 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 757 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 758 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 760 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 762 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 763 mqd->cp_hqd_pq_control = tmp; 764 765 /* enable doorbell */ 766 tmp = 0; 767 if (ring->use_doorbell) { 768 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 769 DOORBELL_OFFSET, ring->doorbell_index); 770 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 771 DOORBELL_EN, 1); 772 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 773 DOORBELL_SOURCE, 0); 774 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 775 DOORBELL_HIT, 0); 776 } 777 else 778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 779 DOORBELL_EN, 0); 780 mqd->cp_hqd_pq_doorbell_control = tmp; 781 782 mqd->cp_hqd_vmid = 0; 783 /* activate the queue */ 784 mqd->cp_hqd_active = 1; 785 786 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 787 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 788 PRELOAD_SIZE, 0x55); 789 mqd->cp_hqd_persistent_state = tmp; 790 791 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 792 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 793 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 794 795 return 0; 796 } 797 798 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 799 { 800 struct v11_compute_mqd *mqd = ring->mqd_ptr; 801 struct amdgpu_device *adev = ring->adev; 802 uint32_t data = 0; 803 804 mutex_lock(&adev->srbm_mutex); 805 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 806 807 /* set CP_HQD_VMID.VMID = 0. */ 808 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 809 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 810 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 811 812 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 813 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 814 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 815 DOORBELL_EN, 0); 816 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 817 818 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 819 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 820 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 821 822 /* set CP_MQD_CONTROL.VMID=0 */ 823 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 824 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 825 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 826 827 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 828 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 829 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 830 831 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 832 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 833 mqd->cp_hqd_pq_rptr_report_addr_lo); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 835 mqd->cp_hqd_pq_rptr_report_addr_hi); 836 837 /* set CP_HQD_PQ_CONTROL */ 838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 839 840 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 841 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 842 mqd->cp_hqd_pq_wptr_poll_addr_lo); 843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 844 mqd->cp_hqd_pq_wptr_poll_addr_hi); 845 846 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 848 mqd->cp_hqd_pq_doorbell_control); 849 850 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 851 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 852 853 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 854 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 855 856 soc21_grbm_select(adev, 0, 0, 0, 0); 857 mutex_unlock(&adev->srbm_mutex); 858 } 859 860 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 861 { 862 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 863 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 864 int r; 865 866 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 867 return -EINVAL; 868 869 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 870 if (r) { 871 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 872 return r; 873 } 874 875 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 876 877 r = amdgpu_ring_test_ring(kiq_ring); 878 if (r) { 879 DRM_ERROR("kfq enable failed\n"); 880 kiq_ring->sched.ready = false; 881 } 882 return r; 883 } 884 885 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 886 enum admgpu_mes_pipe pipe) 887 { 888 struct amdgpu_ring *ring; 889 int r; 890 891 if (pipe == AMDGPU_MES_KIQ_PIPE) 892 ring = &adev->gfx.kiq.ring; 893 else if (pipe == AMDGPU_MES_SCHED_PIPE) 894 ring = &adev->mes.ring; 895 else 896 BUG(); 897 898 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 899 (amdgpu_in_reset(adev) || adev->in_suspend)) { 900 *(ring->wptr_cpu_addr) = 0; 901 *(ring->rptr_cpu_addr) = 0; 902 amdgpu_ring_clear_ring(ring); 903 } 904 905 r = mes_v11_0_mqd_init(ring); 906 if (r) 907 return r; 908 909 if (pipe == AMDGPU_MES_SCHED_PIPE) { 910 r = mes_v11_0_kiq_enable_queue(adev); 911 if (r) 912 return r; 913 } else { 914 mes_v11_0_queue_init_register(ring); 915 } 916 917 /* get MES scheduler/KIQ versions */ 918 mutex_lock(&adev->srbm_mutex); 919 soc21_grbm_select(adev, 3, pipe, 0, 0); 920 921 if (pipe == AMDGPU_MES_SCHED_PIPE) 922 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 923 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 924 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 925 926 soc21_grbm_select(adev, 0, 0, 0, 0); 927 mutex_unlock(&adev->srbm_mutex); 928 929 return 0; 930 } 931 932 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 933 { 934 struct amdgpu_ring *ring; 935 936 ring = &adev->mes.ring; 937 938 ring->funcs = &mes_v11_0_ring_funcs; 939 940 ring->me = 3; 941 ring->pipe = 0; 942 ring->queue = 0; 943 944 ring->ring_obj = NULL; 945 ring->use_doorbell = true; 946 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 947 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 948 ring->no_scheduler = true; 949 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 950 951 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 952 AMDGPU_RING_PRIO_DEFAULT, NULL); 953 } 954 955 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 956 { 957 struct amdgpu_ring *ring; 958 959 spin_lock_init(&adev->gfx.kiq.ring_lock); 960 961 ring = &adev->gfx.kiq.ring; 962 963 ring->me = 3; 964 ring->pipe = 1; 965 ring->queue = 0; 966 967 ring->adev = NULL; 968 ring->ring_obj = NULL; 969 ring->use_doorbell = true; 970 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 971 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 972 ring->no_scheduler = true; 973 sprintf(ring->name, "mes_kiq_%d.%d.%d", 974 ring->me, ring->pipe, ring->queue); 975 976 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 977 AMDGPU_RING_PRIO_DEFAULT, NULL); 978 } 979 980 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 981 enum admgpu_mes_pipe pipe) 982 { 983 int r, mqd_size = sizeof(struct v11_compute_mqd); 984 struct amdgpu_ring *ring; 985 986 if (pipe == AMDGPU_MES_KIQ_PIPE) 987 ring = &adev->gfx.kiq.ring; 988 else if (pipe == AMDGPU_MES_SCHED_PIPE) 989 ring = &adev->mes.ring; 990 else 991 BUG(); 992 993 if (ring->mqd_obj) 994 return 0; 995 996 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 997 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 998 &ring->mqd_gpu_addr, &ring->mqd_ptr); 999 if (r) { 1000 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1001 return r; 1002 } 1003 1004 memset(ring->mqd_ptr, 0, mqd_size); 1005 1006 /* prepare MQD backup */ 1007 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1008 if (!adev->mes.mqd_backup[pipe]) 1009 dev_warn(adev->dev, 1010 "no memory to create MQD backup for ring %s\n", 1011 ring->name); 1012 1013 return 0; 1014 } 1015 1016 static int mes_v11_0_sw_init(void *handle) 1017 { 1018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1019 int pipe, r; 1020 1021 adev->mes.funcs = &mes_v11_0_funcs; 1022 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1023 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1024 1025 r = amdgpu_mes_init(adev); 1026 if (r) 1027 return r; 1028 1029 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1030 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1031 continue; 1032 1033 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1034 if (r) 1035 return r; 1036 1037 r = mes_v11_0_mqd_sw_init(adev, pipe); 1038 if (r) 1039 return r; 1040 } 1041 1042 if (adev->enable_mes_kiq) { 1043 r = mes_v11_0_kiq_ring_init(adev); 1044 if (r) 1045 return r; 1046 } 1047 1048 r = mes_v11_0_ring_init(adev); 1049 if (r) 1050 return r; 1051 1052 return 0; 1053 } 1054 1055 static int mes_v11_0_sw_fini(void *handle) 1056 { 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 int pipe; 1059 1060 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1061 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1062 1063 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1064 kfree(adev->mes.mqd_backup[pipe]); 1065 1066 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1067 &adev->mes.eop_gpu_addr[pipe], 1068 NULL); 1069 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1070 } 1071 1072 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1073 &adev->gfx.kiq.ring.mqd_gpu_addr, 1074 &adev->gfx.kiq.ring.mqd_ptr); 1075 1076 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1077 &adev->mes.ring.mqd_gpu_addr, 1078 &adev->mes.ring.mqd_ptr); 1079 1080 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1081 amdgpu_ring_fini(&adev->mes.ring); 1082 1083 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1084 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1085 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1086 } 1087 1088 amdgpu_mes_fini(adev); 1089 return 0; 1090 } 1091 1092 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1093 { 1094 uint32_t data; 1095 int i; 1096 1097 mutex_lock(&adev->srbm_mutex); 1098 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1099 1100 /* disable the queue if it's active */ 1101 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1102 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1103 for (i = 0; i < adev->usec_timeout; i++) { 1104 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1105 break; 1106 udelay(1); 1107 } 1108 } 1109 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1110 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1111 DOORBELL_EN, 0); 1112 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1113 DOORBELL_HIT, 1); 1114 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1115 1116 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1117 1118 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1119 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1120 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1121 1122 soc21_grbm_select(adev, 0, 0, 0, 0); 1123 mutex_unlock(&adev->srbm_mutex); 1124 1125 adev->mes.ring.sched.ready = false; 1126 } 1127 1128 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1129 { 1130 uint32_t tmp; 1131 struct amdgpu_device *adev = ring->adev; 1132 1133 /* tell RLC which is KIQ queue */ 1134 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1135 tmp &= 0xffffff00; 1136 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1137 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1138 tmp |= 0x80; 1139 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1140 } 1141 1142 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1143 { 1144 int r = 0; 1145 1146 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1147 1148 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1149 if (r) { 1150 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1151 return r; 1152 } 1153 1154 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1155 if (r) { 1156 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1157 return r; 1158 } 1159 1160 } 1161 1162 mes_v11_0_enable(adev, true); 1163 1164 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1165 1166 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1167 if (r) 1168 goto failure; 1169 1170 return r; 1171 1172 failure: 1173 mes_v11_0_hw_fini(adev); 1174 return r; 1175 } 1176 1177 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1178 { 1179 if (adev->mes.ring.sched.ready) 1180 mes_v11_0_kiq_dequeue_sched(adev); 1181 1182 if (!amdgpu_sriov_vf(adev)) 1183 mes_v11_0_enable(adev, false); 1184 1185 return 0; 1186 } 1187 1188 static int mes_v11_0_hw_init(void *handle) 1189 { 1190 int r; 1191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1192 1193 if (!adev->enable_mes_kiq) { 1194 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1195 r = mes_v11_0_load_microcode(adev, 1196 AMDGPU_MES_SCHED_PIPE, true); 1197 if (r) { 1198 DRM_ERROR("failed to MES fw, r=%d\n", r); 1199 return r; 1200 } 1201 } 1202 1203 mes_v11_0_enable(adev, true); 1204 } 1205 1206 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1207 if (r) 1208 goto failure; 1209 1210 r = mes_v11_0_set_hw_resources(&adev->mes); 1211 if (r) 1212 goto failure; 1213 1214 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1215 1216 r = mes_v11_0_query_sched_status(&adev->mes); 1217 if (r) { 1218 DRM_ERROR("MES is busy\n"); 1219 goto failure; 1220 } 1221 1222 /* 1223 * Disable KIQ ring usage from the driver once MES is enabled. 1224 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1225 * with MES enabled. 1226 */ 1227 adev->gfx.kiq.ring.sched.ready = false; 1228 adev->mes.ring.sched.ready = true; 1229 1230 return 0; 1231 1232 failure: 1233 mes_v11_0_hw_fini(adev); 1234 return r; 1235 } 1236 1237 static int mes_v11_0_hw_fini(void *handle) 1238 { 1239 return 0; 1240 } 1241 1242 static int mes_v11_0_suspend(void *handle) 1243 { 1244 int r; 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 r = amdgpu_mes_suspend(adev); 1248 if (r) 1249 return r; 1250 1251 return mes_v11_0_hw_fini(adev); 1252 } 1253 1254 static int mes_v11_0_resume(void *handle) 1255 { 1256 int r; 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 1259 r = mes_v11_0_hw_init(adev); 1260 if (r) 1261 return r; 1262 1263 return amdgpu_mes_resume(adev); 1264 } 1265 1266 static int mes_v11_0_early_init(void *handle) 1267 { 1268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 int pipe, r; 1270 1271 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1272 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1273 continue; 1274 r = amdgpu_mes_init_microcode(adev, pipe); 1275 if (r) 1276 return r; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int mes_v11_0_late_init(void *handle) 1283 { 1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1285 1286 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1287 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1288 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1289 amdgpu_mes_self_test(adev); 1290 1291 return 0; 1292 } 1293 1294 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1295 .name = "mes_v11_0", 1296 .early_init = mes_v11_0_early_init, 1297 .late_init = mes_v11_0_late_init, 1298 .sw_init = mes_v11_0_sw_init, 1299 .sw_fini = mes_v11_0_sw_fini, 1300 .hw_init = mes_v11_0_hw_init, 1301 .hw_fini = mes_v11_0_hw_fini, 1302 .suspend = mes_v11_0_suspend, 1303 .resume = mes_v11_0_resume, 1304 }; 1305 1306 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1307 .type = AMD_IP_BLOCK_TYPE_MES, 1308 .major = 11, 1309 .minor = 0, 1310 .rev = 0, 1311 .funcs = &mes_v11_0_ip_funcs, 1312 }; 1313