1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 44 static int mes_v11_0_hw_fini(void *handle); 45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v11_0_ring_get_rptr, 85 .get_wptr = mes_v11_0_ring_get_wptr, 86 .set_wptr = mes_v11_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 91 void *pkt, int size, 92 int api_status_off) 93 { 94 int ndw = size / 4; 95 signed long r; 96 union MESAPI__ADD_QUEUE *x_pkt = pkt; 97 struct MES_API_STATUS *api_status; 98 struct amdgpu_device *adev = mes->adev; 99 struct amdgpu_ring *ring = &mes->ring; 100 unsigned long flags; 101 signed long timeout = adev->usec_timeout; 102 103 if (amdgpu_emu_mode) { 104 timeout *= 100; 105 } else if (amdgpu_sriov_vf(adev)) { 106 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 107 timeout = 15 * 600 * 1000; 108 } 109 BUG_ON(size % 4 != 0); 110 111 spin_lock_irqsave(&mes->ring_lock, flags); 112 if (amdgpu_ring_alloc(ring, ndw)) { 113 spin_unlock_irqrestore(&mes->ring_lock, flags); 114 return -ENOMEM; 115 } 116 117 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 118 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 119 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 120 121 amdgpu_ring_write_multiple(ring, pkt, ndw); 122 amdgpu_ring_commit(ring); 123 spin_unlock_irqrestore(&mes->ring_lock, flags); 124 125 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 126 127 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 128 timeout); 129 if (r < 1) { 130 DRM_ERROR("MES failed to response msg=%d\n", 131 x_pkt->header.opcode); 132 133 while (halt_if_hws_hang) 134 schedule(); 135 136 return -ETIMEDOUT; 137 } 138 139 return 0; 140 } 141 142 static int convert_to_mes_queue_type(int queue_type) 143 { 144 if (queue_type == AMDGPU_RING_TYPE_GFX) 145 return MES_QUEUE_TYPE_GFX; 146 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 147 return MES_QUEUE_TYPE_COMPUTE; 148 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 149 return MES_QUEUE_TYPE_SDMA; 150 else 151 BUG(); 152 return -1; 153 } 154 155 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 156 struct mes_add_queue_input *input) 157 { 158 struct amdgpu_device *adev = mes->adev; 159 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 160 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 161 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 162 163 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 164 165 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 166 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 167 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 168 169 mes_add_queue_pkt.process_id = input->process_id; 170 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 171 mes_add_queue_pkt.process_va_start = input->process_va_start; 172 mes_add_queue_pkt.process_va_end = input->process_va_end; 173 mes_add_queue_pkt.process_quantum = input->process_quantum; 174 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 175 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 176 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 177 mes_add_queue_pkt.inprocess_gang_priority = 178 input->inprocess_gang_priority; 179 mes_add_queue_pkt.gang_global_priority_level = 180 input->gang_global_priority_level; 181 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 182 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 183 184 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 185 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 186 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 187 else 188 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 189 190 mes_add_queue_pkt.queue_type = 191 convert_to_mes_queue_type(input->queue_type); 192 mes_add_queue_pkt.paging = input->paging; 193 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 194 mes_add_queue_pkt.gws_base = input->gws_base; 195 mes_add_queue_pkt.gws_size = input->gws_size; 196 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 197 mes_add_queue_pkt.tma_addr = input->tma_addr; 198 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 199 mes_add_queue_pkt.trap_en = 1; 200 201 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 202 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 203 mes_add_queue_pkt.gds_size = input->queue_size; 204 205 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 206 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 207 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 208 mes_add_queue_pkt.trap_en = 1; 209 210 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 211 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 212 mes_add_queue_pkt.gds_size = input->queue_size; 213 214 return mes_v11_0_submit_pkt_and_poll_completion(mes, 215 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 216 offsetof(union MESAPI__ADD_QUEUE, api_status)); 217 } 218 219 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 220 struct mes_remove_queue_input *input) 221 { 222 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 223 224 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 225 226 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 227 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 228 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 229 230 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 231 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 232 233 return mes_v11_0_submit_pkt_and_poll_completion(mes, 234 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 235 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 236 } 237 238 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 239 struct mes_unmap_legacy_queue_input *input) 240 { 241 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 242 243 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 244 245 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 246 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 247 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 248 249 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 250 mes_remove_queue_pkt.gang_context_addr = 0; 251 252 mes_remove_queue_pkt.pipe_id = input->pipe_id; 253 mes_remove_queue_pkt.queue_id = input->queue_id; 254 255 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 256 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 257 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 258 mes_remove_queue_pkt.tf_data = 259 lower_32_bits(input->trail_fence_data); 260 } else { 261 mes_remove_queue_pkt.unmap_legacy_queue = 1; 262 mes_remove_queue_pkt.queue_type = 263 convert_to_mes_queue_type(input->queue_type); 264 } 265 266 return mes_v11_0_submit_pkt_and_poll_completion(mes, 267 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 268 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 269 } 270 271 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 272 struct mes_suspend_gang_input *input) 273 { 274 return 0; 275 } 276 277 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 278 struct mes_resume_gang_input *input) 279 { 280 return 0; 281 } 282 283 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 284 { 285 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 286 287 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 288 289 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 290 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 291 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 292 293 return mes_v11_0_submit_pkt_and_poll_completion(mes, 294 &mes_status_pkt, sizeof(mes_status_pkt), 295 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 296 } 297 298 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 299 struct mes_misc_op_input *input) 300 { 301 union MESAPI__MISC misc_pkt; 302 303 memset(&misc_pkt, 0, sizeof(misc_pkt)); 304 305 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 306 misc_pkt.header.opcode = MES_SCH_API_MISC; 307 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 308 309 switch (input->op) { 310 case MES_MISC_OP_READ_REG: 311 misc_pkt.opcode = MESAPI_MISC__READ_REG; 312 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 313 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 314 break; 315 case MES_MISC_OP_WRITE_REG: 316 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 317 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 318 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 319 break; 320 case MES_MISC_OP_WRM_REG_WAIT: 321 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 322 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 323 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 324 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 325 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 326 misc_pkt.wait_reg_mem.reg_offset2 = 0; 327 break; 328 case MES_MISC_OP_WRM_REG_WR_WAIT: 329 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 330 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 331 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 332 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 333 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 334 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 335 break; 336 default: 337 DRM_ERROR("unsupported misc op (%d) \n", input->op); 338 return -EINVAL; 339 } 340 341 return mes_v11_0_submit_pkt_and_poll_completion(mes, 342 &misc_pkt, sizeof(misc_pkt), 343 offsetof(union MESAPI__MISC, api_status)); 344 } 345 346 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 347 { 348 int i; 349 struct amdgpu_device *adev = mes->adev; 350 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 351 352 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 353 354 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 355 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 356 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 357 358 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 359 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 360 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 361 mes_set_hw_res_pkt.paging_vmid = 0; 362 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 363 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 364 mes->query_status_fence_gpu_addr; 365 366 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 367 mes_set_hw_res_pkt.compute_hqd_mask[i] = 368 mes->compute_hqd_mask[i]; 369 370 for (i = 0; i < MAX_GFX_PIPES; i++) 371 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 372 373 for (i = 0; i < MAX_SDMA_PIPES; i++) 374 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 375 376 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 377 mes_set_hw_res_pkt.aggregated_doorbells[i] = 378 mes->aggregated_doorbells[i]; 379 380 for (i = 0; i < 5; i++) { 381 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 382 mes_set_hw_res_pkt.mmhub_base[i] = 383 adev->reg_offset[MMHUB_HWIP][0][i]; 384 mes_set_hw_res_pkt.osssys_base[i] = 385 adev->reg_offset[OSSSYS_HWIP][0][i]; 386 } 387 388 mes_set_hw_res_pkt.disable_reset = 1; 389 mes_set_hw_res_pkt.disable_mes_log = 1; 390 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 391 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 392 mes_set_hw_res_pkt.oversubscription_timer = 50; 393 394 return mes_v11_0_submit_pkt_and_poll_completion(mes, 395 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 396 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 397 } 398 399 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 400 { 401 struct amdgpu_device *adev = mes->adev; 402 uint32_t data; 403 404 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 405 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 406 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 407 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 408 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 409 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 410 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 411 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 412 413 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 414 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 415 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 416 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 417 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 418 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 419 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 420 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 421 422 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 423 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 424 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 425 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 426 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 427 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 428 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 429 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 430 431 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 432 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 433 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 434 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 435 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 436 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 437 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 438 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 439 440 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 441 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 442 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 443 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 444 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 445 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 446 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 447 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 448 449 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 450 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 451 } 452 453 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 454 .add_hw_queue = mes_v11_0_add_hw_queue, 455 .remove_hw_queue = mes_v11_0_remove_hw_queue, 456 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 457 .suspend_gang = mes_v11_0_suspend_gang, 458 .resume_gang = mes_v11_0_resume_gang, 459 .misc_op = mes_v11_0_misc_op, 460 }; 461 462 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 463 enum admgpu_mes_pipe pipe) 464 { 465 int r; 466 const struct mes_firmware_header_v1_0 *mes_hdr; 467 const __le32 *fw_data; 468 unsigned fw_size; 469 470 mes_hdr = (const struct mes_firmware_header_v1_0 *) 471 adev->mes.fw[pipe]->data; 472 473 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 474 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 475 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 476 477 r = amdgpu_bo_create_reserved(adev, fw_size, 478 PAGE_SIZE, 479 AMDGPU_GEM_DOMAIN_VRAM | 480 AMDGPU_GEM_DOMAIN_GTT, 481 &adev->mes.ucode_fw_obj[pipe], 482 &adev->mes.ucode_fw_gpu_addr[pipe], 483 (void **)&adev->mes.ucode_fw_ptr[pipe]); 484 if (r) { 485 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 486 return r; 487 } 488 489 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 490 491 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 492 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 493 494 return 0; 495 } 496 497 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 498 enum admgpu_mes_pipe pipe) 499 { 500 int r; 501 const struct mes_firmware_header_v1_0 *mes_hdr; 502 const __le32 *fw_data; 503 unsigned fw_size; 504 505 mes_hdr = (const struct mes_firmware_header_v1_0 *) 506 adev->mes.fw[pipe]->data; 507 508 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 509 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 510 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 511 512 r = amdgpu_bo_create_reserved(adev, fw_size, 513 64 * 1024, 514 AMDGPU_GEM_DOMAIN_VRAM | 515 AMDGPU_GEM_DOMAIN_GTT, 516 &adev->mes.data_fw_obj[pipe], 517 &adev->mes.data_fw_gpu_addr[pipe], 518 (void **)&adev->mes.data_fw_ptr[pipe]); 519 if (r) { 520 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 521 return r; 522 } 523 524 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 525 526 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 527 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 528 529 return 0; 530 } 531 532 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 533 enum admgpu_mes_pipe pipe) 534 { 535 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 536 &adev->mes.data_fw_gpu_addr[pipe], 537 (void **)&adev->mes.data_fw_ptr[pipe]); 538 539 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 540 &adev->mes.ucode_fw_gpu_addr[pipe], 541 (void **)&adev->mes.ucode_fw_ptr[pipe]); 542 } 543 544 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 545 { 546 uint64_t ucode_addr; 547 uint32_t pipe, data = 0; 548 549 if (enable) { 550 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 551 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 552 data = REG_SET_FIELD(data, CP_MES_CNTL, 553 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 554 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 555 556 mutex_lock(&adev->srbm_mutex); 557 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 558 if (!adev->enable_mes_kiq && 559 pipe == AMDGPU_MES_KIQ_PIPE) 560 continue; 561 562 soc21_grbm_select(adev, 3, pipe, 0, 0); 563 564 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 565 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 566 lower_32_bits(ucode_addr)); 567 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 568 upper_32_bits(ucode_addr)); 569 } 570 soc21_grbm_select(adev, 0, 0, 0, 0); 571 mutex_unlock(&adev->srbm_mutex); 572 573 /* unhalt MES and activate pipe0 */ 574 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 575 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 576 adev->enable_mes_kiq ? 1 : 0); 577 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 578 579 if (amdgpu_emu_mode) 580 msleep(100); 581 else 582 udelay(50); 583 } else { 584 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 585 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 586 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 587 data = REG_SET_FIELD(data, CP_MES_CNTL, 588 MES_INVALIDATE_ICACHE, 1); 589 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 590 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 591 adev->enable_mes_kiq ? 1 : 0); 592 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 593 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 594 } 595 } 596 597 /* This function is for backdoor MES firmware */ 598 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 599 enum admgpu_mes_pipe pipe, bool prime_icache) 600 { 601 int r; 602 uint32_t data; 603 uint64_t ucode_addr; 604 605 mes_v11_0_enable(adev, false); 606 607 if (!adev->mes.fw[pipe]) 608 return -EINVAL; 609 610 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 611 if (r) 612 return r; 613 614 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 615 if (r) { 616 mes_v11_0_free_ucode_buffers(adev, pipe); 617 return r; 618 } 619 620 mutex_lock(&adev->srbm_mutex); 621 /* me=3, pipe=0, queue=0 */ 622 soc21_grbm_select(adev, 3, pipe, 0, 0); 623 624 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 625 626 /* set ucode start address */ 627 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 628 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 629 lower_32_bits(ucode_addr)); 630 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 631 upper_32_bits(ucode_addr)); 632 633 /* set ucode fimrware address */ 634 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 635 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 636 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 637 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 638 639 /* set ucode instruction cache boundary to 2M-1 */ 640 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 641 642 /* set ucode data firmware address */ 643 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 644 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 645 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 646 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 647 648 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 649 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 650 651 if (prime_icache) { 652 /* invalidate ICACHE */ 653 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 654 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 655 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 656 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 657 658 /* prime the ICACHE. */ 659 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 660 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 661 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 662 } 663 664 soc21_grbm_select(adev, 0, 0, 0, 0); 665 mutex_unlock(&adev->srbm_mutex); 666 667 return 0; 668 } 669 670 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 671 enum admgpu_mes_pipe pipe) 672 { 673 int r; 674 u32 *eop; 675 676 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 677 AMDGPU_GEM_DOMAIN_GTT, 678 &adev->mes.eop_gpu_obj[pipe], 679 &adev->mes.eop_gpu_addr[pipe], 680 (void **)&eop); 681 if (r) { 682 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 683 return r; 684 } 685 686 memset(eop, 0, 687 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 688 689 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 690 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 691 692 return 0; 693 } 694 695 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 696 { 697 struct v11_compute_mqd *mqd = ring->mqd_ptr; 698 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 699 uint32_t tmp; 700 701 mqd->header = 0xC0310800; 702 mqd->compute_pipelinestat_enable = 0x00000001; 703 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 704 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 705 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 706 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 707 mqd->compute_misc_reserved = 0x00000007; 708 709 eop_base_addr = ring->eop_gpu_addr >> 8; 710 711 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 712 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 713 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 714 (order_base_2(MES_EOP_SIZE / 4) - 1)); 715 716 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 717 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 718 mqd->cp_hqd_eop_control = tmp; 719 720 /* disable the queue if it's active */ 721 ring->wptr = 0; 722 mqd->cp_hqd_pq_rptr = 0; 723 mqd->cp_hqd_pq_wptr_lo = 0; 724 mqd->cp_hqd_pq_wptr_hi = 0; 725 726 /* set the pointer to the MQD */ 727 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 728 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 729 730 /* set MQD vmid to 0 */ 731 tmp = regCP_MQD_CONTROL_DEFAULT; 732 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 733 mqd->cp_mqd_control = tmp; 734 735 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 736 hqd_gpu_addr = ring->gpu_addr >> 8; 737 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 738 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 739 740 /* set the wb address whether it's enabled or not */ 741 wb_gpu_addr = ring->rptr_gpu_addr; 742 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 743 mqd->cp_hqd_pq_rptr_report_addr_hi = 744 upper_32_bits(wb_gpu_addr) & 0xffff; 745 746 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 747 wb_gpu_addr = ring->wptr_gpu_addr; 748 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 749 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 750 751 /* set up the HQD, this is similar to CP_RB0_CNTL */ 752 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 753 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 754 (order_base_2(ring->ring_size / 4) - 1)); 755 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 756 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 757 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 758 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 760 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 762 mqd->cp_hqd_pq_control = tmp; 763 764 /* enable doorbell */ 765 tmp = 0; 766 if (ring->use_doorbell) { 767 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 768 DOORBELL_OFFSET, ring->doorbell_index); 769 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 770 DOORBELL_EN, 1); 771 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 772 DOORBELL_SOURCE, 0); 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 774 DOORBELL_HIT, 0); 775 } 776 else 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 778 DOORBELL_EN, 0); 779 mqd->cp_hqd_pq_doorbell_control = tmp; 780 781 mqd->cp_hqd_vmid = 0; 782 /* activate the queue */ 783 mqd->cp_hqd_active = 1; 784 785 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 786 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 787 PRELOAD_SIZE, 0x55); 788 mqd->cp_hqd_persistent_state = tmp; 789 790 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 791 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 792 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 793 794 return 0; 795 } 796 797 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 798 { 799 struct v11_compute_mqd *mqd = ring->mqd_ptr; 800 struct amdgpu_device *adev = ring->adev; 801 uint32_t data = 0; 802 803 mutex_lock(&adev->srbm_mutex); 804 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 805 806 /* set CP_HQD_VMID.VMID = 0. */ 807 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 808 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 809 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 810 811 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 812 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 813 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 814 DOORBELL_EN, 0); 815 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 816 817 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 818 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 819 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 820 821 /* set CP_MQD_CONTROL.VMID=0 */ 822 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 823 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 824 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 825 826 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 827 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 828 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 829 830 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 831 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 832 mqd->cp_hqd_pq_rptr_report_addr_lo); 833 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 834 mqd->cp_hqd_pq_rptr_report_addr_hi); 835 836 /* set CP_HQD_PQ_CONTROL */ 837 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 838 839 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 840 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 841 mqd->cp_hqd_pq_wptr_poll_addr_lo); 842 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 843 mqd->cp_hqd_pq_wptr_poll_addr_hi); 844 845 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 847 mqd->cp_hqd_pq_doorbell_control); 848 849 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 850 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 851 852 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 853 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 854 855 soc21_grbm_select(adev, 0, 0, 0, 0); 856 mutex_unlock(&adev->srbm_mutex); 857 } 858 859 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 860 { 861 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 862 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 863 int r; 864 865 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 866 return -EINVAL; 867 868 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 869 if (r) { 870 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 871 return r; 872 } 873 874 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 875 876 r = amdgpu_ring_test_ring(kiq_ring); 877 if (r) { 878 DRM_ERROR("kfq enable failed\n"); 879 kiq_ring->sched.ready = false; 880 } 881 return r; 882 } 883 884 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 885 enum admgpu_mes_pipe pipe) 886 { 887 struct amdgpu_ring *ring; 888 int r; 889 890 if (pipe == AMDGPU_MES_KIQ_PIPE) 891 ring = &adev->gfx.kiq.ring; 892 else if (pipe == AMDGPU_MES_SCHED_PIPE) 893 ring = &adev->mes.ring; 894 else 895 BUG(); 896 897 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 898 (amdgpu_in_reset(adev) || adev->in_suspend)) { 899 *(ring->wptr_cpu_addr) = 0; 900 *(ring->rptr_cpu_addr) = 0; 901 amdgpu_ring_clear_ring(ring); 902 } 903 904 r = mes_v11_0_mqd_init(ring); 905 if (r) 906 return r; 907 908 if (pipe == AMDGPU_MES_SCHED_PIPE) { 909 r = mes_v11_0_kiq_enable_queue(adev); 910 if (r) 911 return r; 912 } else { 913 mes_v11_0_queue_init_register(ring); 914 } 915 916 /* get MES scheduler/KIQ versions */ 917 mutex_lock(&adev->srbm_mutex); 918 soc21_grbm_select(adev, 3, pipe, 0, 0); 919 920 if (pipe == AMDGPU_MES_SCHED_PIPE) 921 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 922 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 923 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 924 925 soc21_grbm_select(adev, 0, 0, 0, 0); 926 mutex_unlock(&adev->srbm_mutex); 927 928 return 0; 929 } 930 931 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 932 { 933 struct amdgpu_ring *ring; 934 935 ring = &adev->mes.ring; 936 937 ring->funcs = &mes_v11_0_ring_funcs; 938 939 ring->me = 3; 940 ring->pipe = 0; 941 ring->queue = 0; 942 943 ring->ring_obj = NULL; 944 ring->use_doorbell = true; 945 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 946 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 947 ring->no_scheduler = true; 948 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 949 950 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 951 AMDGPU_RING_PRIO_DEFAULT, NULL); 952 } 953 954 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 955 { 956 struct amdgpu_ring *ring; 957 958 spin_lock_init(&adev->gfx.kiq.ring_lock); 959 960 ring = &adev->gfx.kiq.ring; 961 962 ring->me = 3; 963 ring->pipe = 1; 964 ring->queue = 0; 965 966 ring->adev = NULL; 967 ring->ring_obj = NULL; 968 ring->use_doorbell = true; 969 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 970 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 971 ring->no_scheduler = true; 972 sprintf(ring->name, "mes_kiq_%d.%d.%d", 973 ring->me, ring->pipe, ring->queue); 974 975 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 976 AMDGPU_RING_PRIO_DEFAULT, NULL); 977 } 978 979 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 980 enum admgpu_mes_pipe pipe) 981 { 982 int r, mqd_size = sizeof(struct v11_compute_mqd); 983 struct amdgpu_ring *ring; 984 985 if (pipe == AMDGPU_MES_KIQ_PIPE) 986 ring = &adev->gfx.kiq.ring; 987 else if (pipe == AMDGPU_MES_SCHED_PIPE) 988 ring = &adev->mes.ring; 989 else 990 BUG(); 991 992 if (ring->mqd_obj) 993 return 0; 994 995 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 996 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 997 &ring->mqd_gpu_addr, &ring->mqd_ptr); 998 if (r) { 999 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1000 return r; 1001 } 1002 1003 memset(ring->mqd_ptr, 0, mqd_size); 1004 1005 /* prepare MQD backup */ 1006 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1007 if (!adev->mes.mqd_backup[pipe]) 1008 dev_warn(adev->dev, 1009 "no memory to create MQD backup for ring %s\n", 1010 ring->name); 1011 1012 return 0; 1013 } 1014 1015 static int mes_v11_0_sw_init(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 int pipe, r; 1019 1020 adev->mes.funcs = &mes_v11_0_funcs; 1021 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1022 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1023 1024 r = amdgpu_mes_init(adev); 1025 if (r) 1026 return r; 1027 1028 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1029 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1030 continue; 1031 1032 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1033 if (r) 1034 return r; 1035 1036 r = mes_v11_0_mqd_sw_init(adev, pipe); 1037 if (r) 1038 return r; 1039 } 1040 1041 if (adev->enable_mes_kiq) { 1042 r = mes_v11_0_kiq_ring_init(adev); 1043 if (r) 1044 return r; 1045 } 1046 1047 r = mes_v11_0_ring_init(adev); 1048 if (r) 1049 return r; 1050 1051 return 0; 1052 } 1053 1054 static int mes_v11_0_sw_fini(void *handle) 1055 { 1056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1057 int pipe; 1058 1059 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1060 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1061 1062 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1063 kfree(adev->mes.mqd_backup[pipe]); 1064 1065 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1066 &adev->mes.eop_gpu_addr[pipe], 1067 NULL); 1068 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1069 } 1070 1071 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1072 &adev->gfx.kiq.ring.mqd_gpu_addr, 1073 &adev->gfx.kiq.ring.mqd_ptr); 1074 1075 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1076 &adev->mes.ring.mqd_gpu_addr, 1077 &adev->mes.ring.mqd_ptr); 1078 1079 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1080 amdgpu_ring_fini(&adev->mes.ring); 1081 1082 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1083 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1084 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1085 } 1086 1087 amdgpu_mes_fini(adev); 1088 return 0; 1089 } 1090 1091 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1092 { 1093 uint32_t data; 1094 int i; 1095 1096 mutex_lock(&adev->srbm_mutex); 1097 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1098 1099 /* disable the queue if it's active */ 1100 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1101 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1102 for (i = 0; i < adev->usec_timeout; i++) { 1103 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1104 break; 1105 udelay(1); 1106 } 1107 } 1108 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1109 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1110 DOORBELL_EN, 0); 1111 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1112 DOORBELL_HIT, 1); 1113 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1114 1115 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1116 1117 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1118 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1119 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1120 1121 soc21_grbm_select(adev, 0, 0, 0, 0); 1122 mutex_unlock(&adev->srbm_mutex); 1123 1124 adev->mes.ring.sched.ready = false; 1125 } 1126 1127 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1128 { 1129 uint32_t tmp; 1130 struct amdgpu_device *adev = ring->adev; 1131 1132 /* tell RLC which is KIQ queue */ 1133 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1134 tmp &= 0xffffff00; 1135 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1136 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1137 tmp |= 0x80; 1138 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1139 } 1140 1141 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1142 { 1143 int r = 0; 1144 1145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1146 1147 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1148 if (r) { 1149 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1150 return r; 1151 } 1152 1153 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1154 if (r) { 1155 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1156 return r; 1157 } 1158 1159 } 1160 1161 mes_v11_0_enable(adev, true); 1162 1163 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1164 1165 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1166 if (r) 1167 goto failure; 1168 1169 return r; 1170 1171 failure: 1172 mes_v11_0_hw_fini(adev); 1173 return r; 1174 } 1175 1176 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1177 { 1178 if (adev->mes.ring.sched.ready) 1179 mes_v11_0_kiq_dequeue_sched(adev); 1180 1181 if (!amdgpu_sriov_vf(adev)) 1182 mes_v11_0_enable(adev, false); 1183 1184 return 0; 1185 } 1186 1187 static int mes_v11_0_hw_init(void *handle) 1188 { 1189 int r; 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 1192 if (!adev->enable_mes_kiq) { 1193 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1194 r = mes_v11_0_load_microcode(adev, 1195 AMDGPU_MES_SCHED_PIPE, true); 1196 if (r) { 1197 DRM_ERROR("failed to MES fw, r=%d\n", r); 1198 return r; 1199 } 1200 } 1201 1202 mes_v11_0_enable(adev, true); 1203 } 1204 1205 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1206 if (r) 1207 goto failure; 1208 1209 r = mes_v11_0_set_hw_resources(&adev->mes); 1210 if (r) 1211 goto failure; 1212 1213 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1214 1215 r = mes_v11_0_query_sched_status(&adev->mes); 1216 if (r) { 1217 DRM_ERROR("MES is busy\n"); 1218 goto failure; 1219 } 1220 1221 /* 1222 * Disable KIQ ring usage from the driver once MES is enabled. 1223 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1224 * with MES enabled. 1225 */ 1226 adev->gfx.kiq.ring.sched.ready = false; 1227 adev->mes.ring.sched.ready = true; 1228 1229 return 0; 1230 1231 failure: 1232 mes_v11_0_hw_fini(adev); 1233 return r; 1234 } 1235 1236 static int mes_v11_0_hw_fini(void *handle) 1237 { 1238 return 0; 1239 } 1240 1241 static int mes_v11_0_suspend(void *handle) 1242 { 1243 int r; 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 1246 r = amdgpu_mes_suspend(adev); 1247 if (r) 1248 return r; 1249 1250 return mes_v11_0_hw_fini(adev); 1251 } 1252 1253 static int mes_v11_0_resume(void *handle) 1254 { 1255 int r; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 r = mes_v11_0_hw_init(adev); 1259 if (r) 1260 return r; 1261 1262 return amdgpu_mes_resume(adev); 1263 } 1264 1265 static int mes_v11_0_early_init(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 int pipe, r; 1269 1270 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1271 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1272 continue; 1273 r = amdgpu_mes_init_microcode(adev, pipe); 1274 if (r) 1275 return r; 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int mes_v11_0_late_init(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 1285 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1286 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && 1287 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1288 amdgpu_mes_self_test(adev); 1289 1290 return 0; 1291 } 1292 1293 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1294 .name = "mes_v11_0", 1295 .early_init = mes_v11_0_early_init, 1296 .late_init = mes_v11_0_late_init, 1297 .sw_init = mes_v11_0_sw_init, 1298 .sw_fini = mes_v11_0_sw_fini, 1299 .hw_init = mes_v11_0_hw_init, 1300 .hw_fini = mes_v11_0_hw_fini, 1301 .suspend = mes_v11_0_suspend, 1302 .resume = mes_v11_0_resume, 1303 }; 1304 1305 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1306 .type = AMD_IP_BLOCK_TYPE_MES, 1307 .major = 11, 1308 .minor = 0, 1309 .rev = 0, 1310 .funcs = &mes_v11_0_ip_funcs, 1311 }; 1312