1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 51 static int mes_v11_0_hw_fini(void *handle); 52 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 53 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 54 55 #define MES_EOP_SIZE 2048 56 57 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 58 { 59 struct amdgpu_device *adev = ring->adev; 60 61 if (ring->use_doorbell) { 62 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 63 ring->wptr); 64 WDOORBELL64(ring->doorbell_index, ring->wptr); 65 } else { 66 BUG(); 67 } 68 } 69 70 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 71 { 72 return *ring->rptr_cpu_addr; 73 } 74 75 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 76 { 77 u64 wptr; 78 79 if (ring->use_doorbell) 80 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 81 else 82 BUG(); 83 return wptr; 84 } 85 86 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 87 .type = AMDGPU_RING_TYPE_MES, 88 .align_mask = 1, 89 .nop = 0, 90 .support_64bit_ptrs = true, 91 .get_rptr = mes_v11_0_ring_get_rptr, 92 .get_wptr = mes_v11_0_ring_get_wptr, 93 .set_wptr = mes_v11_0_ring_set_wptr, 94 .insert_nop = amdgpu_ring_insert_nop, 95 }; 96 97 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 98 void *pkt, int size, 99 int api_status_off) 100 { 101 int ndw = size / 4; 102 signed long r; 103 union MESAPI__ADD_QUEUE *x_pkt = pkt; 104 struct MES_API_STATUS *api_status; 105 struct amdgpu_device *adev = mes->adev; 106 struct amdgpu_ring *ring = &mes->ring; 107 unsigned long flags; 108 signed long timeout = adev->usec_timeout; 109 110 if (amdgpu_emu_mode) { 111 timeout *= 100; 112 } else if (amdgpu_sriov_vf(adev)) { 113 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 114 timeout = 15 * 600 * 1000; 115 } 116 BUG_ON(size % 4 != 0); 117 118 spin_lock_irqsave(&mes->ring_lock, flags); 119 if (amdgpu_ring_alloc(ring, ndw)) { 120 spin_unlock_irqrestore(&mes->ring_lock, flags); 121 return -ENOMEM; 122 } 123 124 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 125 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 126 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 127 128 amdgpu_ring_write_multiple(ring, pkt, ndw); 129 amdgpu_ring_commit(ring); 130 spin_unlock_irqrestore(&mes->ring_lock, flags); 131 132 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 133 134 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 135 timeout); 136 if (r < 1) { 137 DRM_ERROR("MES failed to response msg=%d\n", 138 x_pkt->header.opcode); 139 140 while (halt_if_hws_hang) 141 schedule(); 142 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int convert_to_mes_queue_type(int queue_type) 150 { 151 if (queue_type == AMDGPU_RING_TYPE_GFX) 152 return MES_QUEUE_TYPE_GFX; 153 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 154 return MES_QUEUE_TYPE_COMPUTE; 155 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 156 return MES_QUEUE_TYPE_SDMA; 157 else 158 BUG(); 159 return -1; 160 } 161 162 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 163 struct mes_add_queue_input *input) 164 { 165 struct amdgpu_device *adev = mes->adev; 166 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 167 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 168 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 169 170 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 171 172 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 173 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 174 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 175 176 mes_add_queue_pkt.process_id = input->process_id; 177 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 178 mes_add_queue_pkt.process_va_start = input->process_va_start; 179 mes_add_queue_pkt.process_va_end = input->process_va_end; 180 mes_add_queue_pkt.process_quantum = input->process_quantum; 181 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 182 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 183 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 184 mes_add_queue_pkt.inprocess_gang_priority = 185 input->inprocess_gang_priority; 186 mes_add_queue_pkt.gang_global_priority_level = 187 input->gang_global_priority_level; 188 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 189 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 190 191 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 192 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 193 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 194 else 195 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 196 197 mes_add_queue_pkt.queue_type = 198 convert_to_mes_queue_type(input->queue_type); 199 mes_add_queue_pkt.paging = input->paging; 200 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 201 mes_add_queue_pkt.gws_base = input->gws_base; 202 mes_add_queue_pkt.gws_size = input->gws_size; 203 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 204 mes_add_queue_pkt.tma_addr = input->tma_addr; 205 mes_add_queue_pkt.trap_en = input->trap_en; 206 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 207 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 208 209 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 210 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 211 mes_add_queue_pkt.gds_size = input->queue_size; 212 213 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 214 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 215 mes_add_queue_pkt.gds_size = input->queue_size; 216 217 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 218 219 return mes_v11_0_submit_pkt_and_poll_completion(mes, 220 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 221 offsetof(union MESAPI__ADD_QUEUE, api_status)); 222 } 223 224 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 225 struct mes_remove_queue_input *input) 226 { 227 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 228 229 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 230 231 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 232 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 233 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 234 235 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 236 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 237 238 return mes_v11_0_submit_pkt_and_poll_completion(mes, 239 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 240 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 241 } 242 243 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 244 struct mes_unmap_legacy_queue_input *input) 245 { 246 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 247 248 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 249 250 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 251 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 252 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 253 254 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 255 mes_remove_queue_pkt.gang_context_addr = 0; 256 257 mes_remove_queue_pkt.pipe_id = input->pipe_id; 258 mes_remove_queue_pkt.queue_id = input->queue_id; 259 260 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 261 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 262 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 263 mes_remove_queue_pkt.tf_data = 264 lower_32_bits(input->trail_fence_data); 265 } else { 266 mes_remove_queue_pkt.unmap_legacy_queue = 1; 267 mes_remove_queue_pkt.queue_type = 268 convert_to_mes_queue_type(input->queue_type); 269 } 270 271 return mes_v11_0_submit_pkt_and_poll_completion(mes, 272 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 273 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 274 } 275 276 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 277 struct mes_suspend_gang_input *input) 278 { 279 return 0; 280 } 281 282 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 283 struct mes_resume_gang_input *input) 284 { 285 return 0; 286 } 287 288 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 289 { 290 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 291 292 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 293 294 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 295 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 296 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 297 298 return mes_v11_0_submit_pkt_and_poll_completion(mes, 299 &mes_status_pkt, sizeof(mes_status_pkt), 300 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 301 } 302 303 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 304 struct mes_misc_op_input *input) 305 { 306 union MESAPI__MISC misc_pkt; 307 308 memset(&misc_pkt, 0, sizeof(misc_pkt)); 309 310 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 311 misc_pkt.header.opcode = MES_SCH_API_MISC; 312 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 313 314 switch (input->op) { 315 case MES_MISC_OP_READ_REG: 316 misc_pkt.opcode = MESAPI_MISC__READ_REG; 317 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 318 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 319 break; 320 case MES_MISC_OP_WRITE_REG: 321 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 322 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 323 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 324 break; 325 case MES_MISC_OP_WRM_REG_WAIT: 326 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 327 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 328 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 329 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 330 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 331 misc_pkt.wait_reg_mem.reg_offset2 = 0; 332 break; 333 case MES_MISC_OP_WRM_REG_WR_WAIT: 334 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 335 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 336 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 337 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 338 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 339 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 340 break; 341 case MES_MISC_OP_SET_SHADER_DEBUGGER: 342 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 343 misc_pkt.set_shader_debugger.process_context_addr = 344 input->set_shader_debugger.process_context_addr; 345 misc_pkt.set_shader_debugger.flags.u32all = 346 input->set_shader_debugger.flags.u32all; 347 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 348 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 349 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 350 input->set_shader_debugger.tcp_watch_cntl, 351 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 352 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 353 break; 354 default: 355 DRM_ERROR("unsupported misc op (%d) \n", input->op); 356 return -EINVAL; 357 } 358 359 return mes_v11_0_submit_pkt_and_poll_completion(mes, 360 &misc_pkt, sizeof(misc_pkt), 361 offsetof(union MESAPI__MISC, api_status)); 362 } 363 364 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 365 { 366 int i; 367 struct amdgpu_device *adev = mes->adev; 368 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 369 370 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 371 372 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 373 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 374 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 375 376 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 377 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 378 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 379 mes_set_hw_res_pkt.paging_vmid = 0; 380 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 381 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 382 mes->query_status_fence_gpu_addr; 383 384 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 385 mes_set_hw_res_pkt.compute_hqd_mask[i] = 386 mes->compute_hqd_mask[i]; 387 388 for (i = 0; i < MAX_GFX_PIPES; i++) 389 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 390 391 for (i = 0; i < MAX_SDMA_PIPES; i++) 392 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 393 394 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 395 mes_set_hw_res_pkt.aggregated_doorbells[i] = 396 mes->aggregated_doorbells[i]; 397 398 for (i = 0; i < 5; i++) { 399 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 400 mes_set_hw_res_pkt.mmhub_base[i] = 401 adev->reg_offset[MMHUB_HWIP][0][i]; 402 mes_set_hw_res_pkt.osssys_base[i] = 403 adev->reg_offset[OSSSYS_HWIP][0][i]; 404 } 405 406 mes_set_hw_res_pkt.disable_reset = 1; 407 mes_set_hw_res_pkt.disable_mes_log = 1; 408 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 409 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 410 mes_set_hw_res_pkt.oversubscription_timer = 50; 411 412 return mes_v11_0_submit_pkt_and_poll_completion(mes, 413 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 414 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 415 } 416 417 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 418 { 419 struct amdgpu_device *adev = mes->adev; 420 uint32_t data; 421 422 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 423 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 424 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 425 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 426 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 427 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 428 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 429 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 430 431 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 432 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 433 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 434 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 435 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 436 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 437 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 438 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 439 440 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 441 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 442 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 443 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 444 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 445 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 446 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 447 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 448 449 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 450 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 451 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 452 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 453 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 454 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 455 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 456 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 457 458 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 459 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 460 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 461 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 462 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 463 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 464 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 465 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 466 467 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 468 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 469 } 470 471 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 472 .add_hw_queue = mes_v11_0_add_hw_queue, 473 .remove_hw_queue = mes_v11_0_remove_hw_queue, 474 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 475 .suspend_gang = mes_v11_0_suspend_gang, 476 .resume_gang = mes_v11_0_resume_gang, 477 .misc_op = mes_v11_0_misc_op, 478 }; 479 480 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 481 enum admgpu_mes_pipe pipe) 482 { 483 int r; 484 const struct mes_firmware_header_v1_0 *mes_hdr; 485 const __le32 *fw_data; 486 unsigned fw_size; 487 488 mes_hdr = (const struct mes_firmware_header_v1_0 *) 489 adev->mes.fw[pipe]->data; 490 491 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 492 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 493 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 494 495 r = amdgpu_bo_create_reserved(adev, fw_size, 496 PAGE_SIZE, 497 AMDGPU_GEM_DOMAIN_VRAM | 498 AMDGPU_GEM_DOMAIN_GTT, 499 &adev->mes.ucode_fw_obj[pipe], 500 &adev->mes.ucode_fw_gpu_addr[pipe], 501 (void **)&adev->mes.ucode_fw_ptr[pipe]); 502 if (r) { 503 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 504 return r; 505 } 506 507 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 508 509 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 510 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 511 512 return 0; 513 } 514 515 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 516 enum admgpu_mes_pipe pipe) 517 { 518 int r; 519 const struct mes_firmware_header_v1_0 *mes_hdr; 520 const __le32 *fw_data; 521 unsigned fw_size; 522 523 mes_hdr = (const struct mes_firmware_header_v1_0 *) 524 adev->mes.fw[pipe]->data; 525 526 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 527 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 528 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 529 530 r = amdgpu_bo_create_reserved(adev, fw_size, 531 64 * 1024, 532 AMDGPU_GEM_DOMAIN_VRAM | 533 AMDGPU_GEM_DOMAIN_GTT, 534 &adev->mes.data_fw_obj[pipe], 535 &adev->mes.data_fw_gpu_addr[pipe], 536 (void **)&adev->mes.data_fw_ptr[pipe]); 537 if (r) { 538 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 539 return r; 540 } 541 542 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 543 544 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 545 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 546 547 return 0; 548 } 549 550 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 551 enum admgpu_mes_pipe pipe) 552 { 553 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 554 &adev->mes.data_fw_gpu_addr[pipe], 555 (void **)&adev->mes.data_fw_ptr[pipe]); 556 557 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 558 &adev->mes.ucode_fw_gpu_addr[pipe], 559 (void **)&adev->mes.ucode_fw_ptr[pipe]); 560 } 561 562 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 563 { 564 uint64_t ucode_addr; 565 uint32_t pipe, data = 0; 566 567 if (enable) { 568 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 569 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 570 data = REG_SET_FIELD(data, CP_MES_CNTL, 571 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 572 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 573 574 mutex_lock(&adev->srbm_mutex); 575 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 576 if (!adev->enable_mes_kiq && 577 pipe == AMDGPU_MES_KIQ_PIPE) 578 continue; 579 580 soc21_grbm_select(adev, 3, pipe, 0, 0); 581 582 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 583 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 584 lower_32_bits(ucode_addr)); 585 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 586 upper_32_bits(ucode_addr)); 587 } 588 soc21_grbm_select(adev, 0, 0, 0, 0); 589 mutex_unlock(&adev->srbm_mutex); 590 591 /* unhalt MES and activate pipe0 */ 592 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 593 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 594 adev->enable_mes_kiq ? 1 : 0); 595 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 596 597 if (amdgpu_emu_mode) 598 msleep(100); 599 else 600 udelay(50); 601 } else { 602 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 603 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 604 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 605 data = REG_SET_FIELD(data, CP_MES_CNTL, 606 MES_INVALIDATE_ICACHE, 1); 607 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 608 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 609 adev->enable_mes_kiq ? 1 : 0); 610 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 611 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 612 } 613 } 614 615 /* This function is for backdoor MES firmware */ 616 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 617 enum admgpu_mes_pipe pipe, bool prime_icache) 618 { 619 int r; 620 uint32_t data; 621 uint64_t ucode_addr; 622 623 mes_v11_0_enable(adev, false); 624 625 if (!adev->mes.fw[pipe]) 626 return -EINVAL; 627 628 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 629 if (r) 630 return r; 631 632 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 633 if (r) { 634 mes_v11_0_free_ucode_buffers(adev, pipe); 635 return r; 636 } 637 638 mutex_lock(&adev->srbm_mutex); 639 /* me=3, pipe=0, queue=0 */ 640 soc21_grbm_select(adev, 3, pipe, 0, 0); 641 642 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 643 644 /* set ucode start address */ 645 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 646 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 647 lower_32_bits(ucode_addr)); 648 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 649 upper_32_bits(ucode_addr)); 650 651 /* set ucode fimrware address */ 652 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 653 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 654 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 655 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 656 657 /* set ucode instruction cache boundary to 2M-1 */ 658 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 659 660 /* set ucode data firmware address */ 661 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 662 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 663 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 664 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 665 666 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 667 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 668 669 if (prime_icache) { 670 /* invalidate ICACHE */ 671 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 672 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 673 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 674 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 675 676 /* prime the ICACHE. */ 677 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 678 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 679 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 680 } 681 682 soc21_grbm_select(adev, 0, 0, 0, 0); 683 mutex_unlock(&adev->srbm_mutex); 684 685 return 0; 686 } 687 688 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 689 enum admgpu_mes_pipe pipe) 690 { 691 int r; 692 u32 *eop; 693 694 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 695 AMDGPU_GEM_DOMAIN_GTT, 696 &adev->mes.eop_gpu_obj[pipe], 697 &adev->mes.eop_gpu_addr[pipe], 698 (void **)&eop); 699 if (r) { 700 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 701 return r; 702 } 703 704 memset(eop, 0, 705 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 706 707 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 708 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 709 710 return 0; 711 } 712 713 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 714 { 715 struct v11_compute_mqd *mqd = ring->mqd_ptr; 716 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 717 uint32_t tmp; 718 719 memset(mqd, 0, sizeof(*mqd)); 720 721 mqd->header = 0xC0310800; 722 mqd->compute_pipelinestat_enable = 0x00000001; 723 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 724 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 725 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 726 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 727 mqd->compute_misc_reserved = 0x00000007; 728 729 eop_base_addr = ring->eop_gpu_addr >> 8; 730 731 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 732 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 733 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 734 (order_base_2(MES_EOP_SIZE / 4) - 1)); 735 736 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 737 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 738 mqd->cp_hqd_eop_control = tmp; 739 740 /* disable the queue if it's active */ 741 ring->wptr = 0; 742 mqd->cp_hqd_pq_rptr = 0; 743 mqd->cp_hqd_pq_wptr_lo = 0; 744 mqd->cp_hqd_pq_wptr_hi = 0; 745 746 /* set the pointer to the MQD */ 747 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 748 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 749 750 /* set MQD vmid to 0 */ 751 tmp = regCP_MQD_CONTROL_DEFAULT; 752 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 753 mqd->cp_mqd_control = tmp; 754 755 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 756 hqd_gpu_addr = ring->gpu_addr >> 8; 757 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 758 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 759 760 /* set the wb address whether it's enabled or not */ 761 wb_gpu_addr = ring->rptr_gpu_addr; 762 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 763 mqd->cp_hqd_pq_rptr_report_addr_hi = 764 upper_32_bits(wb_gpu_addr) & 0xffff; 765 766 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 767 wb_gpu_addr = ring->wptr_gpu_addr; 768 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 769 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 770 771 /* set up the HQD, this is similar to CP_RB0_CNTL */ 772 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 774 (order_base_2(ring->ring_size / 4) - 1)); 775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 776 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 782 mqd->cp_hqd_pq_control = tmp; 783 784 /* enable doorbell */ 785 tmp = 0; 786 if (ring->use_doorbell) { 787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 788 DOORBELL_OFFSET, ring->doorbell_index); 789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 790 DOORBELL_EN, 1); 791 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 792 DOORBELL_SOURCE, 0); 793 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 794 DOORBELL_HIT, 0); 795 } 796 else 797 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 798 DOORBELL_EN, 0); 799 mqd->cp_hqd_pq_doorbell_control = tmp; 800 801 mqd->cp_hqd_vmid = 0; 802 /* activate the queue */ 803 mqd->cp_hqd_active = 1; 804 805 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 806 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 807 PRELOAD_SIZE, 0x55); 808 mqd->cp_hqd_persistent_state = tmp; 809 810 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 811 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 812 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 813 814 amdgpu_device_flush_hdp(ring->adev, NULL); 815 return 0; 816 } 817 818 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 819 { 820 struct v11_compute_mqd *mqd = ring->mqd_ptr; 821 struct amdgpu_device *adev = ring->adev; 822 uint32_t data = 0; 823 824 mutex_lock(&adev->srbm_mutex); 825 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 826 827 /* set CP_HQD_VMID.VMID = 0. */ 828 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 829 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 830 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 831 832 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 833 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 834 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 835 DOORBELL_EN, 0); 836 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 837 838 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 839 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 840 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 841 842 /* set CP_MQD_CONTROL.VMID=0 */ 843 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 844 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 845 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 846 847 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 848 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 849 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 850 851 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 853 mqd->cp_hqd_pq_rptr_report_addr_lo); 854 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 855 mqd->cp_hqd_pq_rptr_report_addr_hi); 856 857 /* set CP_HQD_PQ_CONTROL */ 858 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 859 860 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 861 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 862 mqd->cp_hqd_pq_wptr_poll_addr_lo); 863 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 864 mqd->cp_hqd_pq_wptr_poll_addr_hi); 865 866 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 867 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 868 mqd->cp_hqd_pq_doorbell_control); 869 870 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 871 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 872 873 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 874 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 875 876 soc21_grbm_select(adev, 0, 0, 0, 0); 877 mutex_unlock(&adev->srbm_mutex); 878 } 879 880 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 881 { 882 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 883 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 884 int r; 885 886 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 887 return -EINVAL; 888 889 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 890 if (r) { 891 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 892 return r; 893 } 894 895 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 896 897 return amdgpu_ring_test_helper(kiq_ring); 898 } 899 900 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 901 enum admgpu_mes_pipe pipe) 902 { 903 struct amdgpu_ring *ring; 904 int r; 905 906 if (pipe == AMDGPU_MES_KIQ_PIPE) 907 ring = &adev->gfx.kiq[0].ring; 908 else if (pipe == AMDGPU_MES_SCHED_PIPE) 909 ring = &adev->mes.ring; 910 else 911 BUG(); 912 913 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 914 (amdgpu_in_reset(adev) || adev->in_suspend)) { 915 *(ring->wptr_cpu_addr) = 0; 916 *(ring->rptr_cpu_addr) = 0; 917 amdgpu_ring_clear_ring(ring); 918 } 919 920 r = mes_v11_0_mqd_init(ring); 921 if (r) 922 return r; 923 924 if (pipe == AMDGPU_MES_SCHED_PIPE) { 925 r = mes_v11_0_kiq_enable_queue(adev); 926 if (r) 927 return r; 928 } else { 929 mes_v11_0_queue_init_register(ring); 930 } 931 932 /* get MES scheduler/KIQ versions */ 933 mutex_lock(&adev->srbm_mutex); 934 soc21_grbm_select(adev, 3, pipe, 0, 0); 935 936 if (pipe == AMDGPU_MES_SCHED_PIPE) 937 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 938 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 939 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 940 941 soc21_grbm_select(adev, 0, 0, 0, 0); 942 mutex_unlock(&adev->srbm_mutex); 943 944 return 0; 945 } 946 947 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 948 { 949 struct amdgpu_ring *ring; 950 951 ring = &adev->mes.ring; 952 953 ring->funcs = &mes_v11_0_ring_funcs; 954 955 ring->me = 3; 956 ring->pipe = 0; 957 ring->queue = 0; 958 959 ring->ring_obj = NULL; 960 ring->use_doorbell = true; 961 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 962 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 963 ring->no_scheduler = true; 964 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 965 966 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 967 AMDGPU_RING_PRIO_DEFAULT, NULL); 968 } 969 970 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 971 { 972 struct amdgpu_ring *ring; 973 974 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 975 976 ring = &adev->gfx.kiq[0].ring; 977 978 ring->me = 3; 979 ring->pipe = 1; 980 ring->queue = 0; 981 982 ring->adev = NULL; 983 ring->ring_obj = NULL; 984 ring->use_doorbell = true; 985 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 986 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 987 ring->no_scheduler = true; 988 sprintf(ring->name, "mes_kiq_%d.%d.%d", 989 ring->me, ring->pipe, ring->queue); 990 991 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 992 AMDGPU_RING_PRIO_DEFAULT, NULL); 993 } 994 995 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 996 enum admgpu_mes_pipe pipe) 997 { 998 int r, mqd_size = sizeof(struct v11_compute_mqd); 999 struct amdgpu_ring *ring; 1000 1001 if (pipe == AMDGPU_MES_KIQ_PIPE) 1002 ring = &adev->gfx.kiq[0].ring; 1003 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1004 ring = &adev->mes.ring; 1005 else 1006 BUG(); 1007 1008 if (ring->mqd_obj) 1009 return 0; 1010 1011 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1012 AMDGPU_GEM_DOMAIN_VRAM | 1013 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1014 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1015 if (r) { 1016 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1017 return r; 1018 } 1019 1020 memset(ring->mqd_ptr, 0, mqd_size); 1021 1022 /* prepare MQD backup */ 1023 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1024 if (!adev->mes.mqd_backup[pipe]) 1025 dev_warn(adev->dev, 1026 "no memory to create MQD backup for ring %s\n", 1027 ring->name); 1028 1029 return 0; 1030 } 1031 1032 static int mes_v11_0_sw_init(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 int pipe, r; 1036 1037 adev->mes.funcs = &mes_v11_0_funcs; 1038 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1039 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1040 1041 r = amdgpu_mes_init(adev); 1042 if (r) 1043 return r; 1044 1045 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1046 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1047 continue; 1048 1049 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1050 if (r) 1051 return r; 1052 1053 r = mes_v11_0_mqd_sw_init(adev, pipe); 1054 if (r) 1055 return r; 1056 } 1057 1058 if (adev->enable_mes_kiq) { 1059 r = mes_v11_0_kiq_ring_init(adev); 1060 if (r) 1061 return r; 1062 } 1063 1064 r = mes_v11_0_ring_init(adev); 1065 if (r) 1066 return r; 1067 1068 return 0; 1069 } 1070 1071 static int mes_v11_0_sw_fini(void *handle) 1072 { 1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1074 int pipe; 1075 1076 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1077 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1078 1079 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1080 kfree(adev->mes.mqd_backup[pipe]); 1081 1082 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1083 &adev->mes.eop_gpu_addr[pipe], 1084 NULL); 1085 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1086 } 1087 1088 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1089 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1090 &adev->gfx.kiq[0].ring.mqd_ptr); 1091 1092 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1093 &adev->mes.ring.mqd_gpu_addr, 1094 &adev->mes.ring.mqd_ptr); 1095 1096 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1097 amdgpu_ring_fini(&adev->mes.ring); 1098 1099 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1100 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1101 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1102 } 1103 1104 amdgpu_mes_fini(adev); 1105 return 0; 1106 } 1107 1108 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1109 { 1110 uint32_t data; 1111 int i; 1112 struct amdgpu_device *adev = ring->adev; 1113 1114 mutex_lock(&adev->srbm_mutex); 1115 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1116 1117 /* disable the queue if it's active */ 1118 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1119 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1120 for (i = 0; i < adev->usec_timeout; i++) { 1121 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1122 break; 1123 udelay(1); 1124 } 1125 } 1126 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1127 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1128 DOORBELL_EN, 0); 1129 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1130 DOORBELL_HIT, 1); 1131 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1132 1133 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1134 1135 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1136 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1137 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1138 1139 soc21_grbm_select(adev, 0, 0, 0, 0); 1140 mutex_unlock(&adev->srbm_mutex); 1141 } 1142 1143 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1144 { 1145 uint32_t tmp; 1146 struct amdgpu_device *adev = ring->adev; 1147 1148 /* tell RLC which is KIQ queue */ 1149 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1150 tmp &= 0xffffff00; 1151 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1152 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1153 tmp |= 0x80; 1154 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1155 } 1156 1157 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1158 { 1159 uint32_t tmp; 1160 1161 /* tell RLC which is KIQ dequeue */ 1162 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1163 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1164 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1165 } 1166 1167 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1168 { 1169 int r = 0; 1170 1171 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1172 1173 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1174 if (r) { 1175 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1176 return r; 1177 } 1178 1179 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1180 if (r) { 1181 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1182 return r; 1183 } 1184 1185 } 1186 1187 mes_v11_0_enable(adev, true); 1188 1189 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1190 1191 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1192 if (r) 1193 goto failure; 1194 1195 return r; 1196 1197 failure: 1198 mes_v11_0_hw_fini(adev); 1199 return r; 1200 } 1201 1202 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1203 { 1204 if (adev->mes.ring.sched.ready) { 1205 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1206 adev->mes.ring.sched.ready = false; 1207 } 1208 1209 if (amdgpu_sriov_vf(adev)) { 1210 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1211 mes_v11_0_kiq_clear(adev); 1212 } 1213 1214 mes_v11_0_enable(adev, false); 1215 1216 return 0; 1217 } 1218 1219 static int mes_v11_0_hw_init(void *handle) 1220 { 1221 int r; 1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1223 1224 if (!adev->enable_mes_kiq) { 1225 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1226 r = mes_v11_0_load_microcode(adev, 1227 AMDGPU_MES_SCHED_PIPE, true); 1228 if (r) { 1229 DRM_ERROR("failed to MES fw, r=%d\n", r); 1230 return r; 1231 } 1232 } 1233 1234 mes_v11_0_enable(adev, true); 1235 } 1236 1237 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1238 if (r) 1239 goto failure; 1240 1241 r = mes_v11_0_set_hw_resources(&adev->mes); 1242 if (r) 1243 goto failure; 1244 1245 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1246 1247 r = mes_v11_0_query_sched_status(&adev->mes); 1248 if (r) { 1249 DRM_ERROR("MES is busy\n"); 1250 goto failure; 1251 } 1252 1253 /* 1254 * Disable KIQ ring usage from the driver once MES is enabled. 1255 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1256 * with MES enabled. 1257 */ 1258 adev->gfx.kiq[0].ring.sched.ready = false; 1259 adev->mes.ring.sched.ready = true; 1260 1261 return 0; 1262 1263 failure: 1264 mes_v11_0_hw_fini(adev); 1265 return r; 1266 } 1267 1268 static int mes_v11_0_hw_fini(void *handle) 1269 { 1270 return 0; 1271 } 1272 1273 static int mes_v11_0_suspend(void *handle) 1274 { 1275 int r; 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 1278 r = amdgpu_mes_suspend(adev); 1279 if (r) 1280 return r; 1281 1282 return mes_v11_0_hw_fini(adev); 1283 } 1284 1285 static int mes_v11_0_resume(void *handle) 1286 { 1287 int r; 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 1290 r = mes_v11_0_hw_init(adev); 1291 if (r) 1292 return r; 1293 1294 return amdgpu_mes_resume(adev); 1295 } 1296 1297 static int mes_v11_0_early_init(void *handle) 1298 { 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 int pipe, r; 1301 1302 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1303 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1304 continue; 1305 r = amdgpu_mes_init_microcode(adev, pipe); 1306 if (r) 1307 return r; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int mes_v11_0_late_init(void *handle) 1314 { 1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1316 1317 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1318 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1319 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1320 amdgpu_mes_self_test(adev); 1321 1322 return 0; 1323 } 1324 1325 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1326 .name = "mes_v11_0", 1327 .early_init = mes_v11_0_early_init, 1328 .late_init = mes_v11_0_late_init, 1329 .sw_init = mes_v11_0_sw_init, 1330 .sw_fini = mes_v11_0_sw_fini, 1331 .hw_init = mes_v11_0_hw_init, 1332 .hw_fini = mes_v11_0_hw_fini, 1333 .suspend = mes_v11_0_suspend, 1334 .resume = mes_v11_0_resume, 1335 }; 1336 1337 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1338 .type = AMD_IP_BLOCK_TYPE_MES, 1339 .major = 11, 1340 .minor = 0, 1341 .rev = 0, 1342 .funcs = &mes_v11_0_ip_funcs, 1343 }; 1344