1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 44 static int mes_v11_0_hw_fini(void *handle); 45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v11_0_ring_get_rptr, 85 .get_wptr = mes_v11_0_ring_get_wptr, 86 .set_wptr = mes_v11_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 91 void *pkt, int size, 92 int api_status_off) 93 { 94 int ndw = size / 4; 95 signed long r; 96 union MESAPI__ADD_QUEUE *x_pkt = pkt; 97 struct MES_API_STATUS *api_status; 98 struct amdgpu_device *adev = mes->adev; 99 struct amdgpu_ring *ring = &mes->ring; 100 unsigned long flags; 101 102 BUG_ON(size % 4 != 0); 103 104 spin_lock_irqsave(&mes->ring_lock, flags); 105 if (amdgpu_ring_alloc(ring, ndw)) { 106 spin_unlock_irqrestore(&mes->ring_lock, flags); 107 return -ENOMEM; 108 } 109 110 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 111 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 112 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 113 114 amdgpu_ring_write_multiple(ring, pkt, ndw); 115 amdgpu_ring_commit(ring); 116 spin_unlock_irqrestore(&mes->ring_lock, flags); 117 118 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 119 120 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 121 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 122 if (r < 1) { 123 DRM_ERROR("MES failed to response msg=%d\n", 124 x_pkt->header.opcode); 125 return -ETIMEDOUT; 126 } 127 128 return 0; 129 } 130 131 static int convert_to_mes_queue_type(int queue_type) 132 { 133 if (queue_type == AMDGPU_RING_TYPE_GFX) 134 return MES_QUEUE_TYPE_GFX; 135 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 136 return MES_QUEUE_TYPE_COMPUTE; 137 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 138 return MES_QUEUE_TYPE_SDMA; 139 else 140 BUG(); 141 return -1; 142 } 143 144 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 145 struct mes_add_queue_input *input) 146 { 147 struct amdgpu_device *adev = mes->adev; 148 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 149 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 150 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 151 152 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 153 154 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 155 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 156 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 157 158 mes_add_queue_pkt.process_id = input->process_id; 159 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 160 mes_add_queue_pkt.process_va_start = input->process_va_start; 161 mes_add_queue_pkt.process_va_end = input->process_va_end; 162 mes_add_queue_pkt.process_quantum = input->process_quantum; 163 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 164 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 165 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 166 mes_add_queue_pkt.inprocess_gang_priority = 167 input->inprocess_gang_priority; 168 mes_add_queue_pkt.gang_global_priority_level = 169 input->gang_global_priority_level; 170 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 171 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 172 173 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 174 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 175 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 176 else 177 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 178 179 mes_add_queue_pkt.queue_type = 180 convert_to_mes_queue_type(input->queue_type); 181 mes_add_queue_pkt.paging = input->paging; 182 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 183 mes_add_queue_pkt.gws_base = input->gws_base; 184 mes_add_queue_pkt.gws_size = input->gws_size; 185 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 186 mes_add_queue_pkt.tma_addr = input->tma_addr; 187 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 188 mes_add_queue_pkt.trap_en = 1; 189 190 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 191 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 192 mes_add_queue_pkt.gds_size = input->queue_size; 193 194 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 195 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 196 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 197 mes_add_queue_pkt.trap_en = 1; 198 199 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 200 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 201 mes_add_queue_pkt.gds_size = input->queue_size; 202 203 return mes_v11_0_submit_pkt_and_poll_completion(mes, 204 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 205 offsetof(union MESAPI__ADD_QUEUE, api_status)); 206 } 207 208 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 209 struct mes_remove_queue_input *input) 210 { 211 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 212 213 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 214 215 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 216 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 217 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 218 219 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 220 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 221 222 return mes_v11_0_submit_pkt_and_poll_completion(mes, 223 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 224 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 225 } 226 227 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 228 struct mes_unmap_legacy_queue_input *input) 229 { 230 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 231 232 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 233 234 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 235 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 236 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 237 238 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 239 mes_remove_queue_pkt.gang_context_addr = 0; 240 241 mes_remove_queue_pkt.pipe_id = input->pipe_id; 242 mes_remove_queue_pkt.queue_id = input->queue_id; 243 244 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 245 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 246 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 247 mes_remove_queue_pkt.tf_data = 248 lower_32_bits(input->trail_fence_data); 249 } else { 250 mes_remove_queue_pkt.unmap_legacy_queue = 1; 251 mes_remove_queue_pkt.queue_type = 252 convert_to_mes_queue_type(input->queue_type); 253 } 254 255 return mes_v11_0_submit_pkt_and_poll_completion(mes, 256 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 257 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 258 } 259 260 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 261 struct mes_suspend_gang_input *input) 262 { 263 return 0; 264 } 265 266 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 267 struct mes_resume_gang_input *input) 268 { 269 return 0; 270 } 271 272 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 273 { 274 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 275 276 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 277 278 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 279 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 280 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 281 282 return mes_v11_0_submit_pkt_and_poll_completion(mes, 283 &mes_status_pkt, sizeof(mes_status_pkt), 284 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 285 } 286 287 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 288 struct mes_misc_op_input *input) 289 { 290 union MESAPI__MISC misc_pkt; 291 292 memset(&misc_pkt, 0, sizeof(misc_pkt)); 293 294 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 295 misc_pkt.header.opcode = MES_SCH_API_MISC; 296 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 297 298 switch (input->op) { 299 case MES_MISC_OP_READ_REG: 300 misc_pkt.opcode = MESAPI_MISC__READ_REG; 301 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 302 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 303 break; 304 case MES_MISC_OP_WRITE_REG: 305 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 306 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 307 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 308 break; 309 case MES_MISC_OP_WRM_REG_WAIT: 310 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 311 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 312 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 313 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 314 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 315 misc_pkt.wait_reg_mem.reg_offset2 = 0; 316 break; 317 case MES_MISC_OP_WRM_REG_WR_WAIT: 318 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 319 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 320 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 321 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 322 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 323 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 324 break; 325 default: 326 DRM_ERROR("unsupported misc op (%d) \n", input->op); 327 return -EINVAL; 328 } 329 330 return mes_v11_0_submit_pkt_and_poll_completion(mes, 331 &misc_pkt, sizeof(misc_pkt), 332 offsetof(union MESAPI__MISC, api_status)); 333 } 334 335 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 336 { 337 int i; 338 struct amdgpu_device *adev = mes->adev; 339 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 340 341 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 342 343 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 344 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 345 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 346 347 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 348 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 349 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 350 mes_set_hw_res_pkt.paging_vmid = 0; 351 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 352 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 353 mes->query_status_fence_gpu_addr; 354 355 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 356 mes_set_hw_res_pkt.compute_hqd_mask[i] = 357 mes->compute_hqd_mask[i]; 358 359 for (i = 0; i < MAX_GFX_PIPES; i++) 360 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 361 362 for (i = 0; i < MAX_SDMA_PIPES; i++) 363 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 364 365 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 366 mes_set_hw_res_pkt.aggregated_doorbells[i] = 367 mes->aggregated_doorbells[i]; 368 369 for (i = 0; i < 5; i++) { 370 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 371 mes_set_hw_res_pkt.mmhub_base[i] = 372 adev->reg_offset[MMHUB_HWIP][0][i]; 373 mes_set_hw_res_pkt.osssys_base[i] = 374 adev->reg_offset[OSSSYS_HWIP][0][i]; 375 } 376 377 mes_set_hw_res_pkt.disable_reset = 1; 378 mes_set_hw_res_pkt.disable_mes_log = 1; 379 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 380 mes_set_hw_res_pkt.oversubscription_timer = 50; 381 382 return mes_v11_0_submit_pkt_and_poll_completion(mes, 383 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 384 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 385 } 386 387 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 388 { 389 struct amdgpu_device *adev = mes->adev; 390 uint32_t data; 391 392 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 393 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 394 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 395 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 396 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 397 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 398 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 399 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 400 401 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 402 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 403 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 404 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 405 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 406 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 407 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 408 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 409 410 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 411 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 412 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 413 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 414 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 415 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 416 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 417 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 418 419 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 420 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 421 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 422 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 423 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 424 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 425 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 426 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 427 428 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 429 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 430 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 431 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 432 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 433 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 434 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 435 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 436 437 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 438 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 439 } 440 441 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 442 .add_hw_queue = mes_v11_0_add_hw_queue, 443 .remove_hw_queue = mes_v11_0_remove_hw_queue, 444 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 445 .suspend_gang = mes_v11_0_suspend_gang, 446 .resume_gang = mes_v11_0_resume_gang, 447 .misc_op = mes_v11_0_misc_op, 448 }; 449 450 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 451 enum admgpu_mes_pipe pipe) 452 { 453 char fw_name[30]; 454 char ucode_prefix[30]; 455 int err; 456 const struct mes_firmware_header_v1_0 *mes_hdr; 457 struct amdgpu_firmware_info *info; 458 459 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 460 461 if (pipe == AMDGPU_MES_SCHED_PIPE) 462 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 463 ucode_prefix); 464 else 465 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 466 ucode_prefix); 467 468 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 469 if (err) 470 return err; 471 472 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 473 if (err) { 474 release_firmware(adev->mes.fw[pipe]); 475 adev->mes.fw[pipe] = NULL; 476 return err; 477 } 478 479 mes_hdr = (const struct mes_firmware_header_v1_0 *) 480 adev->mes.fw[pipe]->data; 481 adev->mes.ucode_fw_version[pipe] = 482 le32_to_cpu(mes_hdr->mes_ucode_version); 483 adev->mes.ucode_fw_version[pipe] = 484 le32_to_cpu(mes_hdr->mes_ucode_data_version); 485 adev->mes.uc_start_addr[pipe] = 486 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 487 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 488 adev->mes.data_start_addr[pipe] = 489 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 490 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 491 492 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 493 int ucode, ucode_data; 494 495 if (pipe == AMDGPU_MES_SCHED_PIPE) { 496 ucode = AMDGPU_UCODE_ID_CP_MES; 497 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 498 } else { 499 ucode = AMDGPU_UCODE_ID_CP_MES1; 500 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 501 } 502 503 info = &adev->firmware.ucode[ucode]; 504 info->ucode_id = ucode; 505 info->fw = adev->mes.fw[pipe]; 506 adev->firmware.fw_size += 507 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 508 PAGE_SIZE); 509 510 info = &adev->firmware.ucode[ucode_data]; 511 info->ucode_id = ucode_data; 512 info->fw = adev->mes.fw[pipe]; 513 adev->firmware.fw_size += 514 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 515 PAGE_SIZE); 516 } 517 518 return 0; 519 } 520 521 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 522 enum admgpu_mes_pipe pipe) 523 { 524 release_firmware(adev->mes.fw[pipe]); 525 adev->mes.fw[pipe] = NULL; 526 } 527 528 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 529 enum admgpu_mes_pipe pipe) 530 { 531 int r; 532 const struct mes_firmware_header_v1_0 *mes_hdr; 533 const __le32 *fw_data; 534 unsigned fw_size; 535 536 mes_hdr = (const struct mes_firmware_header_v1_0 *) 537 adev->mes.fw[pipe]->data; 538 539 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 540 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 541 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 542 543 r = amdgpu_bo_create_reserved(adev, fw_size, 544 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 545 &adev->mes.ucode_fw_obj[pipe], 546 &adev->mes.ucode_fw_gpu_addr[pipe], 547 (void **)&adev->mes.ucode_fw_ptr[pipe]); 548 if (r) { 549 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 550 return r; 551 } 552 553 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 554 555 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 556 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 557 558 return 0; 559 } 560 561 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 562 enum admgpu_mes_pipe pipe) 563 { 564 int r; 565 const struct mes_firmware_header_v1_0 *mes_hdr; 566 const __le32 *fw_data; 567 unsigned fw_size; 568 569 mes_hdr = (const struct mes_firmware_header_v1_0 *) 570 adev->mes.fw[pipe]->data; 571 572 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 573 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 574 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 575 576 r = amdgpu_bo_create_reserved(adev, fw_size, 577 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 578 &adev->mes.data_fw_obj[pipe], 579 &adev->mes.data_fw_gpu_addr[pipe], 580 (void **)&adev->mes.data_fw_ptr[pipe]); 581 if (r) { 582 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 583 return r; 584 } 585 586 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 587 588 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 589 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 590 591 return 0; 592 } 593 594 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 595 enum admgpu_mes_pipe pipe) 596 { 597 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 598 &adev->mes.data_fw_gpu_addr[pipe], 599 (void **)&adev->mes.data_fw_ptr[pipe]); 600 601 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 602 &adev->mes.ucode_fw_gpu_addr[pipe], 603 (void **)&adev->mes.ucode_fw_ptr[pipe]); 604 } 605 606 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 607 { 608 uint64_t ucode_addr; 609 uint32_t pipe, data = 0; 610 611 if (enable) { 612 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 613 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 614 data = REG_SET_FIELD(data, CP_MES_CNTL, 615 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 616 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 617 618 mutex_lock(&adev->srbm_mutex); 619 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 620 if (!adev->enable_mes_kiq && 621 pipe == AMDGPU_MES_KIQ_PIPE) 622 continue; 623 624 soc21_grbm_select(adev, 3, pipe, 0, 0); 625 626 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 627 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 628 lower_32_bits(ucode_addr)); 629 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 630 upper_32_bits(ucode_addr)); 631 } 632 soc21_grbm_select(adev, 0, 0, 0, 0); 633 mutex_unlock(&adev->srbm_mutex); 634 635 /* unhalt MES and activate pipe0 */ 636 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 637 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 638 adev->enable_mes_kiq ? 1 : 0); 639 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 640 641 if (amdgpu_emu_mode) 642 msleep(100); 643 else 644 udelay(50); 645 } else { 646 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 647 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 648 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 649 data = REG_SET_FIELD(data, CP_MES_CNTL, 650 MES_INVALIDATE_ICACHE, 1); 651 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 652 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 653 adev->enable_mes_kiq ? 1 : 0); 654 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 655 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 656 } 657 } 658 659 /* This function is for backdoor MES firmware */ 660 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 661 enum admgpu_mes_pipe pipe, bool prime_icache) 662 { 663 int r; 664 uint32_t data; 665 uint64_t ucode_addr; 666 667 mes_v11_0_enable(adev, false); 668 669 if (!adev->mes.fw[pipe]) 670 return -EINVAL; 671 672 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 673 if (r) 674 return r; 675 676 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 677 if (r) { 678 mes_v11_0_free_ucode_buffers(adev, pipe); 679 return r; 680 } 681 682 mutex_lock(&adev->srbm_mutex); 683 /* me=3, pipe=0, queue=0 */ 684 soc21_grbm_select(adev, 3, pipe, 0, 0); 685 686 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 687 688 /* set ucode start address */ 689 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 690 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 691 lower_32_bits(ucode_addr)); 692 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 693 upper_32_bits(ucode_addr)); 694 695 /* set ucode fimrware address */ 696 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 697 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 698 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 699 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 700 701 /* set ucode instruction cache boundary to 2M-1 */ 702 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 703 704 /* set ucode data firmware address */ 705 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 706 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 707 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 708 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 709 710 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 711 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 712 713 if (prime_icache) { 714 /* invalidate ICACHE */ 715 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 716 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 717 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 718 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 719 720 /* prime the ICACHE. */ 721 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 722 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 723 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 724 } 725 726 soc21_grbm_select(adev, 0, 0, 0, 0); 727 mutex_unlock(&adev->srbm_mutex); 728 729 return 0; 730 } 731 732 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 733 enum admgpu_mes_pipe pipe) 734 { 735 int r; 736 u32 *eop; 737 738 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 739 AMDGPU_GEM_DOMAIN_GTT, 740 &adev->mes.eop_gpu_obj[pipe], 741 &adev->mes.eop_gpu_addr[pipe], 742 (void **)&eop); 743 if (r) { 744 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 745 return r; 746 } 747 748 memset(eop, 0, 749 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 750 751 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 752 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 753 754 return 0; 755 } 756 757 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 758 { 759 struct v11_compute_mqd *mqd = ring->mqd_ptr; 760 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 761 uint32_t tmp; 762 763 mqd->header = 0xC0310800; 764 mqd->compute_pipelinestat_enable = 0x00000001; 765 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 766 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 767 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 768 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 769 mqd->compute_misc_reserved = 0x00000007; 770 771 eop_base_addr = ring->eop_gpu_addr >> 8; 772 773 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 774 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 775 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 776 (order_base_2(MES_EOP_SIZE / 4) - 1)); 777 778 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 779 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 780 mqd->cp_hqd_eop_control = tmp; 781 782 /* disable the queue if it's active */ 783 ring->wptr = 0; 784 mqd->cp_hqd_pq_rptr = 0; 785 mqd->cp_hqd_pq_wptr_lo = 0; 786 mqd->cp_hqd_pq_wptr_hi = 0; 787 788 /* set the pointer to the MQD */ 789 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 790 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 791 792 /* set MQD vmid to 0 */ 793 tmp = regCP_MQD_CONTROL_DEFAULT; 794 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 795 mqd->cp_mqd_control = tmp; 796 797 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 798 hqd_gpu_addr = ring->gpu_addr >> 8; 799 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 800 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 801 802 /* set the wb address whether it's enabled or not */ 803 wb_gpu_addr = ring->rptr_gpu_addr; 804 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 805 mqd->cp_hqd_pq_rptr_report_addr_hi = 806 upper_32_bits(wb_gpu_addr) & 0xffff; 807 808 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 809 wb_gpu_addr = ring->wptr_gpu_addr; 810 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 811 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 812 813 /* set up the HQD, this is similar to CP_RB0_CNTL */ 814 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 816 (order_base_2(ring->ring_size / 4) - 1)); 817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 818 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 819 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 821 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 824 mqd->cp_hqd_pq_control = tmp; 825 826 /* enable doorbell */ 827 tmp = 0; 828 if (ring->use_doorbell) { 829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 830 DOORBELL_OFFSET, ring->doorbell_index); 831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 832 DOORBELL_EN, 1); 833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 834 DOORBELL_SOURCE, 0); 835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 836 DOORBELL_HIT, 0); 837 } 838 else 839 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 840 DOORBELL_EN, 0); 841 mqd->cp_hqd_pq_doorbell_control = tmp; 842 843 mqd->cp_hqd_vmid = 0; 844 /* activate the queue */ 845 mqd->cp_hqd_active = 1; 846 847 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 848 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 849 PRELOAD_SIZE, 0x55); 850 mqd->cp_hqd_persistent_state = tmp; 851 852 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 853 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 854 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 855 856 return 0; 857 } 858 859 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 860 { 861 struct v11_compute_mqd *mqd = ring->mqd_ptr; 862 struct amdgpu_device *adev = ring->adev; 863 uint32_t data = 0; 864 865 mutex_lock(&adev->srbm_mutex); 866 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 867 868 /* set CP_HQD_VMID.VMID = 0. */ 869 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 870 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 871 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 872 873 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 874 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 875 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 876 DOORBELL_EN, 0); 877 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 878 879 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 880 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 881 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 882 883 /* set CP_MQD_CONTROL.VMID=0 */ 884 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 885 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 886 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 887 888 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 889 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 890 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 891 892 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 893 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 894 mqd->cp_hqd_pq_rptr_report_addr_lo); 895 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 896 mqd->cp_hqd_pq_rptr_report_addr_hi); 897 898 /* set CP_HQD_PQ_CONTROL */ 899 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 900 901 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 902 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 903 mqd->cp_hqd_pq_wptr_poll_addr_lo); 904 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 905 mqd->cp_hqd_pq_wptr_poll_addr_hi); 906 907 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 908 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 909 mqd->cp_hqd_pq_doorbell_control); 910 911 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 912 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 913 914 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 915 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 916 917 soc21_grbm_select(adev, 0, 0, 0, 0); 918 mutex_unlock(&adev->srbm_mutex); 919 } 920 921 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 922 { 923 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 924 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 925 int r; 926 927 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 928 return -EINVAL; 929 930 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 931 if (r) { 932 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 933 return r; 934 } 935 936 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 937 938 r = amdgpu_ring_test_ring(kiq_ring); 939 if (r) { 940 DRM_ERROR("kfq enable failed\n"); 941 kiq_ring->sched.ready = false; 942 } 943 return r; 944 } 945 946 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 947 enum admgpu_mes_pipe pipe) 948 { 949 struct amdgpu_ring *ring; 950 int r; 951 952 if (pipe == AMDGPU_MES_KIQ_PIPE) 953 ring = &adev->gfx.kiq.ring; 954 else if (pipe == AMDGPU_MES_SCHED_PIPE) 955 ring = &adev->mes.ring; 956 else 957 BUG(); 958 959 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 960 (amdgpu_in_reset(adev) || adev->in_suspend)) { 961 *(ring->wptr_cpu_addr) = 0; 962 *(ring->rptr_cpu_addr) = 0; 963 amdgpu_ring_clear_ring(ring); 964 } 965 966 r = mes_v11_0_mqd_init(ring); 967 if (r) 968 return r; 969 970 if (pipe == AMDGPU_MES_SCHED_PIPE) { 971 r = mes_v11_0_kiq_enable_queue(adev); 972 if (r) 973 return r; 974 } else { 975 mes_v11_0_queue_init_register(ring); 976 } 977 978 /* get MES scheduler/KIQ versions */ 979 mutex_lock(&adev->srbm_mutex); 980 soc21_grbm_select(adev, 3, pipe, 0, 0); 981 982 if (pipe == AMDGPU_MES_SCHED_PIPE) 983 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 984 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 985 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 986 987 soc21_grbm_select(adev, 0, 0, 0, 0); 988 mutex_unlock(&adev->srbm_mutex); 989 990 return 0; 991 } 992 993 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 994 { 995 struct amdgpu_ring *ring; 996 997 ring = &adev->mes.ring; 998 999 ring->funcs = &mes_v11_0_ring_funcs; 1000 1001 ring->me = 3; 1002 ring->pipe = 0; 1003 ring->queue = 0; 1004 1005 ring->ring_obj = NULL; 1006 ring->use_doorbell = true; 1007 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1008 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1009 ring->no_scheduler = true; 1010 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1011 1012 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1013 AMDGPU_RING_PRIO_DEFAULT, NULL); 1014 } 1015 1016 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1017 { 1018 struct amdgpu_ring *ring; 1019 1020 spin_lock_init(&adev->gfx.kiq.ring_lock); 1021 1022 ring = &adev->gfx.kiq.ring; 1023 1024 ring->me = 3; 1025 ring->pipe = 1; 1026 ring->queue = 0; 1027 1028 ring->adev = NULL; 1029 ring->ring_obj = NULL; 1030 ring->use_doorbell = true; 1031 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1032 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1033 ring->no_scheduler = true; 1034 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1035 ring->me, ring->pipe, ring->queue); 1036 1037 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1038 AMDGPU_RING_PRIO_DEFAULT, NULL); 1039 } 1040 1041 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1042 enum admgpu_mes_pipe pipe) 1043 { 1044 int r, mqd_size = sizeof(struct v11_compute_mqd); 1045 struct amdgpu_ring *ring; 1046 1047 if (pipe == AMDGPU_MES_KIQ_PIPE) 1048 ring = &adev->gfx.kiq.ring; 1049 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1050 ring = &adev->mes.ring; 1051 else 1052 BUG(); 1053 1054 if (ring->mqd_obj) 1055 return 0; 1056 1057 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1058 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1059 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1060 if (r) { 1061 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1062 return r; 1063 } 1064 1065 memset(ring->mqd_ptr, 0, mqd_size); 1066 1067 /* prepare MQD backup */ 1068 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1069 if (!adev->mes.mqd_backup[pipe]) 1070 dev_warn(adev->dev, 1071 "no memory to create MQD backup for ring %s\n", 1072 ring->name); 1073 1074 return 0; 1075 } 1076 1077 static int mes_v11_0_sw_init(void *handle) 1078 { 1079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1080 int pipe, r; 1081 1082 adev->mes.adev = adev; 1083 adev->mes.funcs = &mes_v11_0_funcs; 1084 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1085 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1086 1087 r = amdgpu_mes_init(adev); 1088 if (r) 1089 return r; 1090 1091 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1092 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1093 continue; 1094 1095 r = mes_v11_0_init_microcode(adev, pipe); 1096 if (r) 1097 return r; 1098 1099 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1100 if (r) 1101 return r; 1102 1103 r = mes_v11_0_mqd_sw_init(adev, pipe); 1104 if (r) 1105 return r; 1106 } 1107 1108 if (adev->enable_mes_kiq) { 1109 r = mes_v11_0_kiq_ring_init(adev); 1110 if (r) 1111 return r; 1112 } 1113 1114 r = mes_v11_0_ring_init(adev); 1115 if (r) 1116 return r; 1117 1118 return 0; 1119 } 1120 1121 static int mes_v11_0_sw_fini(void *handle) 1122 { 1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1124 int pipe; 1125 1126 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1127 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1128 1129 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1130 kfree(adev->mes.mqd_backup[pipe]); 1131 1132 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1133 &adev->mes.eop_gpu_addr[pipe], 1134 NULL); 1135 1136 mes_v11_0_free_microcode(adev, pipe); 1137 } 1138 1139 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1140 &adev->gfx.kiq.ring.mqd_gpu_addr, 1141 &adev->gfx.kiq.ring.mqd_ptr); 1142 1143 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1144 &adev->mes.ring.mqd_gpu_addr, 1145 &adev->mes.ring.mqd_ptr); 1146 1147 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1148 amdgpu_ring_fini(&adev->mes.ring); 1149 1150 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1151 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1152 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1153 } 1154 1155 amdgpu_mes_fini(adev); 1156 return 0; 1157 } 1158 1159 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1160 { 1161 uint32_t data; 1162 int i; 1163 1164 mutex_lock(&adev->srbm_mutex); 1165 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1166 1167 /* disable the queue if it's active */ 1168 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1169 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1170 for (i = 0; i < adev->usec_timeout; i++) { 1171 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1172 break; 1173 udelay(1); 1174 } 1175 } 1176 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1177 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1178 DOORBELL_EN, 0); 1179 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1180 DOORBELL_HIT, 1); 1181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1182 1183 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1184 1185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1186 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1187 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1188 1189 soc21_grbm_select(adev, 0, 0, 0, 0); 1190 mutex_unlock(&adev->srbm_mutex); 1191 1192 adev->mes.ring.sched.ready = false; 1193 } 1194 1195 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1196 { 1197 uint32_t tmp; 1198 struct amdgpu_device *adev = ring->adev; 1199 1200 /* tell RLC which is KIQ queue */ 1201 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1202 tmp &= 0xffffff00; 1203 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1204 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1205 tmp |= 0x80; 1206 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1207 } 1208 1209 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1210 { 1211 int r = 0; 1212 1213 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1214 1215 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1216 if (r) { 1217 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1218 return r; 1219 } 1220 1221 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1222 if (r) { 1223 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1224 return r; 1225 } 1226 1227 } 1228 1229 mes_v11_0_enable(adev, true); 1230 1231 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1232 1233 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1234 if (r) 1235 goto failure; 1236 1237 return r; 1238 1239 failure: 1240 mes_v11_0_hw_fini(adev); 1241 return r; 1242 } 1243 1244 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1245 { 1246 if (adev->mes.ring.sched.ready) 1247 mes_v11_0_kiq_dequeue_sched(adev); 1248 1249 mes_v11_0_enable(adev, false); 1250 return 0; 1251 } 1252 1253 static int mes_v11_0_hw_init(void *handle) 1254 { 1255 int r; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 if (!adev->enable_mes_kiq) { 1259 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1260 r = mes_v11_0_load_microcode(adev, 1261 AMDGPU_MES_SCHED_PIPE, true); 1262 if (r) { 1263 DRM_ERROR("failed to MES fw, r=%d\n", r); 1264 return r; 1265 } 1266 } 1267 1268 mes_v11_0_enable(adev, true); 1269 } 1270 1271 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1272 if (r) 1273 goto failure; 1274 1275 r = mes_v11_0_set_hw_resources(&adev->mes); 1276 if (r) 1277 goto failure; 1278 1279 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1280 1281 r = mes_v11_0_query_sched_status(&adev->mes); 1282 if (r) { 1283 DRM_ERROR("MES is busy\n"); 1284 goto failure; 1285 } 1286 1287 /* 1288 * Disable KIQ ring usage from the driver once MES is enabled. 1289 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1290 * with MES enabled. 1291 */ 1292 adev->gfx.kiq.ring.sched.ready = false; 1293 adev->mes.ring.sched.ready = true; 1294 1295 return 0; 1296 1297 failure: 1298 mes_v11_0_hw_fini(adev); 1299 return r; 1300 } 1301 1302 static int mes_v11_0_hw_fini(void *handle) 1303 { 1304 return 0; 1305 } 1306 1307 static int mes_v11_0_suspend(void *handle) 1308 { 1309 int r; 1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1311 1312 r = amdgpu_mes_suspend(adev); 1313 if (r) 1314 return r; 1315 1316 return mes_v11_0_hw_fini(adev); 1317 } 1318 1319 static int mes_v11_0_resume(void *handle) 1320 { 1321 int r; 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 1324 r = mes_v11_0_hw_init(adev); 1325 if (r) 1326 return r; 1327 1328 return amdgpu_mes_resume(adev); 1329 } 1330 1331 static int mes_v11_0_late_init(void *handle) 1332 { 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 if (!amdgpu_in_reset(adev) && 1336 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1337 amdgpu_mes_self_test(adev); 1338 1339 return 0; 1340 } 1341 1342 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1343 .name = "mes_v11_0", 1344 .late_init = mes_v11_0_late_init, 1345 .sw_init = mes_v11_0_sw_init, 1346 .sw_fini = mes_v11_0_sw_fini, 1347 .hw_init = mes_v11_0_hw_init, 1348 .hw_fini = mes_v11_0_hw_fini, 1349 .suspend = mes_v11_0_suspend, 1350 .resume = mes_v11_0_resume, 1351 }; 1352 1353 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1354 .type = AMD_IP_BLOCK_TYPE_MES, 1355 .major = 11, 1356 .minor = 0, 1357 .rev = 0, 1358 .funcs = &mes_v11_0_ip_funcs, 1359 }; 1360