1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 44 static int mes_v11_0_hw_fini(void *handle); 45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v11_0_ring_get_rptr, 85 .get_wptr = mes_v11_0_ring_get_wptr, 86 .set_wptr = mes_v11_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 91 void *pkt, int size, 92 int api_status_off) 93 { 94 int ndw = size / 4; 95 signed long r; 96 union MESAPI__ADD_QUEUE *x_pkt = pkt; 97 struct MES_API_STATUS *api_status; 98 struct amdgpu_device *adev = mes->adev; 99 struct amdgpu_ring *ring = &mes->ring; 100 unsigned long flags; 101 102 BUG_ON(size % 4 != 0); 103 104 spin_lock_irqsave(&mes->ring_lock, flags); 105 if (amdgpu_ring_alloc(ring, ndw)) { 106 spin_unlock_irqrestore(&mes->ring_lock, flags); 107 return -ENOMEM; 108 } 109 110 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 111 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 112 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 113 114 amdgpu_ring_write_multiple(ring, pkt, ndw); 115 amdgpu_ring_commit(ring); 116 spin_unlock_irqrestore(&mes->ring_lock, flags); 117 118 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 119 120 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 121 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 122 if (r < 1) { 123 DRM_ERROR("MES failed to response msg=%d\n", 124 x_pkt->header.opcode); 125 return -ETIMEDOUT; 126 } 127 128 return 0; 129 } 130 131 static int convert_to_mes_queue_type(int queue_type) 132 { 133 if (queue_type == AMDGPU_RING_TYPE_GFX) 134 return MES_QUEUE_TYPE_GFX; 135 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 136 return MES_QUEUE_TYPE_COMPUTE; 137 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 138 return MES_QUEUE_TYPE_SDMA; 139 else 140 BUG(); 141 return -1; 142 } 143 144 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 145 struct mes_add_queue_input *input) 146 { 147 struct amdgpu_device *adev = mes->adev; 148 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 149 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 150 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 151 152 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 153 154 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 155 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 156 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 157 158 mes_add_queue_pkt.process_id = input->process_id; 159 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 160 mes_add_queue_pkt.process_va_start = input->process_va_start; 161 mes_add_queue_pkt.process_va_end = input->process_va_end; 162 mes_add_queue_pkt.process_quantum = input->process_quantum; 163 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 164 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 165 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 166 mes_add_queue_pkt.inprocess_gang_priority = 167 input->inprocess_gang_priority; 168 mes_add_queue_pkt.gang_global_priority_level = 169 input->gang_global_priority_level; 170 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 171 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 172 173 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 174 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 175 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 176 else 177 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 178 179 mes_add_queue_pkt.queue_type = 180 convert_to_mes_queue_type(input->queue_type); 181 mes_add_queue_pkt.paging = input->paging; 182 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 183 mes_add_queue_pkt.gws_base = input->gws_base; 184 mes_add_queue_pkt.gws_size = input->gws_size; 185 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 186 mes_add_queue_pkt.tma_addr = input->tma_addr; 187 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 188 189 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 190 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 191 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 192 mes_add_queue_pkt.trap_en = 1; 193 194 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 195 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 196 mes_add_queue_pkt.gds_size = input->queue_size; 197 198 return mes_v11_0_submit_pkt_and_poll_completion(mes, 199 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 200 offsetof(union MESAPI__ADD_QUEUE, api_status)); 201 } 202 203 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 204 struct mes_remove_queue_input *input) 205 { 206 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 207 208 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 209 210 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 211 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 212 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 213 214 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 215 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 216 217 return mes_v11_0_submit_pkt_and_poll_completion(mes, 218 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 219 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 220 } 221 222 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 223 struct mes_unmap_legacy_queue_input *input) 224 { 225 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 226 227 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 228 229 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 230 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 231 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 232 233 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 234 mes_remove_queue_pkt.gang_context_addr = 0; 235 236 mes_remove_queue_pkt.pipe_id = input->pipe_id; 237 mes_remove_queue_pkt.queue_id = input->queue_id; 238 239 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 240 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 241 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 242 mes_remove_queue_pkt.tf_data = 243 lower_32_bits(input->trail_fence_data); 244 } else { 245 mes_remove_queue_pkt.unmap_legacy_queue = 1; 246 mes_remove_queue_pkt.queue_type = 247 convert_to_mes_queue_type(input->queue_type); 248 } 249 250 return mes_v11_0_submit_pkt_and_poll_completion(mes, 251 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 252 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 253 } 254 255 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 256 struct mes_suspend_gang_input *input) 257 { 258 return 0; 259 } 260 261 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 262 struct mes_resume_gang_input *input) 263 { 264 return 0; 265 } 266 267 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 268 { 269 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 270 271 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 272 273 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 274 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 275 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 276 277 return mes_v11_0_submit_pkt_and_poll_completion(mes, 278 &mes_status_pkt, sizeof(mes_status_pkt), 279 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 280 } 281 282 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 283 struct mes_misc_op_input *input) 284 { 285 union MESAPI__MISC misc_pkt; 286 287 memset(&misc_pkt, 0, sizeof(misc_pkt)); 288 289 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 290 misc_pkt.header.opcode = MES_SCH_API_MISC; 291 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 292 293 switch (input->op) { 294 case MES_MISC_OP_READ_REG: 295 misc_pkt.opcode = MESAPI_MISC__READ_REG; 296 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 297 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 298 break; 299 case MES_MISC_OP_WRITE_REG: 300 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 301 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 302 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 303 break; 304 case MES_MISC_OP_WRM_REG_WAIT: 305 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 306 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 307 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 308 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 309 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 310 misc_pkt.wait_reg_mem.reg_offset2 = 0; 311 break; 312 case MES_MISC_OP_WRM_REG_WR_WAIT: 313 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 314 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 315 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 316 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 317 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 318 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 319 break; 320 default: 321 DRM_ERROR("unsupported misc op (%d) \n", input->op); 322 return -EINVAL; 323 } 324 325 return mes_v11_0_submit_pkt_and_poll_completion(mes, 326 &misc_pkt, sizeof(misc_pkt), 327 offsetof(union MESAPI__MISC, api_status)); 328 } 329 330 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 331 { 332 int i; 333 struct amdgpu_device *adev = mes->adev; 334 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 335 336 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 337 338 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 339 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 340 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 341 342 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 343 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 344 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 345 mes_set_hw_res_pkt.paging_vmid = 0; 346 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 347 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 348 mes->query_status_fence_gpu_addr; 349 350 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 351 mes_set_hw_res_pkt.compute_hqd_mask[i] = 352 mes->compute_hqd_mask[i]; 353 354 for (i = 0; i < MAX_GFX_PIPES; i++) 355 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 356 357 for (i = 0; i < MAX_SDMA_PIPES; i++) 358 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 359 360 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 361 mes_set_hw_res_pkt.aggregated_doorbells[i] = 362 mes->aggregated_doorbells[i]; 363 364 for (i = 0; i < 5; i++) { 365 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 366 mes_set_hw_res_pkt.mmhub_base[i] = 367 adev->reg_offset[MMHUB_HWIP][0][i]; 368 mes_set_hw_res_pkt.osssys_base[i] = 369 adev->reg_offset[OSSSYS_HWIP][0][i]; 370 } 371 372 mes_set_hw_res_pkt.disable_reset = 1; 373 mes_set_hw_res_pkt.disable_mes_log = 1; 374 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 375 mes_set_hw_res_pkt.oversubscription_timer = 50; 376 377 return mes_v11_0_submit_pkt_and_poll_completion(mes, 378 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 379 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 380 } 381 382 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 383 { 384 struct amdgpu_device *adev = mes->adev; 385 uint32_t data; 386 387 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 388 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 389 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 390 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 391 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 392 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 393 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 394 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 395 396 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 397 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 398 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 399 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 400 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 401 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 402 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 403 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 404 405 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 406 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 407 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 408 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 409 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 410 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 411 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 412 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 413 414 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 415 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 416 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 417 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 418 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 419 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 420 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 421 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 422 423 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 424 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 425 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 426 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 427 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 428 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 429 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 430 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 431 432 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 433 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 434 } 435 436 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 437 .add_hw_queue = mes_v11_0_add_hw_queue, 438 .remove_hw_queue = mes_v11_0_remove_hw_queue, 439 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 440 .suspend_gang = mes_v11_0_suspend_gang, 441 .resume_gang = mes_v11_0_resume_gang, 442 .misc_op = mes_v11_0_misc_op, 443 }; 444 445 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 446 enum admgpu_mes_pipe pipe) 447 { 448 char fw_name[30]; 449 char ucode_prefix[30]; 450 int err; 451 const struct mes_firmware_header_v1_0 *mes_hdr; 452 struct amdgpu_firmware_info *info; 453 454 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 455 456 if (pipe == AMDGPU_MES_SCHED_PIPE) 457 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 458 ucode_prefix); 459 else 460 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 461 ucode_prefix); 462 463 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 464 if (err) 465 return err; 466 467 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 468 if (err) { 469 release_firmware(adev->mes.fw[pipe]); 470 adev->mes.fw[pipe] = NULL; 471 return err; 472 } 473 474 mes_hdr = (const struct mes_firmware_header_v1_0 *) 475 adev->mes.fw[pipe]->data; 476 adev->mes.ucode_fw_version[pipe] = 477 le32_to_cpu(mes_hdr->mes_ucode_version); 478 adev->mes.ucode_fw_version[pipe] = 479 le32_to_cpu(mes_hdr->mes_ucode_data_version); 480 adev->mes.uc_start_addr[pipe] = 481 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 482 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 483 adev->mes.data_start_addr[pipe] = 484 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 485 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 486 487 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 488 int ucode, ucode_data; 489 490 if (pipe == AMDGPU_MES_SCHED_PIPE) { 491 ucode = AMDGPU_UCODE_ID_CP_MES; 492 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 493 } else { 494 ucode = AMDGPU_UCODE_ID_CP_MES1; 495 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 496 } 497 498 info = &adev->firmware.ucode[ucode]; 499 info->ucode_id = ucode; 500 info->fw = adev->mes.fw[pipe]; 501 adev->firmware.fw_size += 502 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 503 PAGE_SIZE); 504 505 info = &adev->firmware.ucode[ucode_data]; 506 info->ucode_id = ucode_data; 507 info->fw = adev->mes.fw[pipe]; 508 adev->firmware.fw_size += 509 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 510 PAGE_SIZE); 511 } 512 513 return 0; 514 } 515 516 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 517 enum admgpu_mes_pipe pipe) 518 { 519 release_firmware(adev->mes.fw[pipe]); 520 adev->mes.fw[pipe] = NULL; 521 } 522 523 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 524 enum admgpu_mes_pipe pipe) 525 { 526 int r; 527 const struct mes_firmware_header_v1_0 *mes_hdr; 528 const __le32 *fw_data; 529 unsigned fw_size; 530 531 mes_hdr = (const struct mes_firmware_header_v1_0 *) 532 adev->mes.fw[pipe]->data; 533 534 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 535 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 536 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 537 538 r = amdgpu_bo_create_reserved(adev, fw_size, 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 540 &adev->mes.ucode_fw_obj[pipe], 541 &adev->mes.ucode_fw_gpu_addr[pipe], 542 (void **)&adev->mes.ucode_fw_ptr[pipe]); 543 if (r) { 544 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 545 return r; 546 } 547 548 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 549 550 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 551 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 552 553 return 0; 554 } 555 556 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 557 enum admgpu_mes_pipe pipe) 558 { 559 int r; 560 const struct mes_firmware_header_v1_0 *mes_hdr; 561 const __le32 *fw_data; 562 unsigned fw_size; 563 564 mes_hdr = (const struct mes_firmware_header_v1_0 *) 565 adev->mes.fw[pipe]->data; 566 567 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 568 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 569 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 570 571 r = amdgpu_bo_create_reserved(adev, fw_size, 572 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 573 &adev->mes.data_fw_obj[pipe], 574 &adev->mes.data_fw_gpu_addr[pipe], 575 (void **)&adev->mes.data_fw_ptr[pipe]); 576 if (r) { 577 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 578 return r; 579 } 580 581 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 582 583 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 584 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 585 586 return 0; 587 } 588 589 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 590 enum admgpu_mes_pipe pipe) 591 { 592 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 593 &adev->mes.data_fw_gpu_addr[pipe], 594 (void **)&adev->mes.data_fw_ptr[pipe]); 595 596 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 597 &adev->mes.ucode_fw_gpu_addr[pipe], 598 (void **)&adev->mes.ucode_fw_ptr[pipe]); 599 } 600 601 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 602 { 603 uint64_t ucode_addr; 604 uint32_t pipe, data = 0; 605 606 if (enable) { 607 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 608 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 609 data = REG_SET_FIELD(data, CP_MES_CNTL, 610 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 611 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 612 613 mutex_lock(&adev->srbm_mutex); 614 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 615 if (!adev->enable_mes_kiq && 616 pipe == AMDGPU_MES_KIQ_PIPE) 617 continue; 618 619 soc21_grbm_select(adev, 3, pipe, 0, 0); 620 621 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 622 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 623 lower_32_bits(ucode_addr)); 624 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 625 upper_32_bits(ucode_addr)); 626 } 627 soc21_grbm_select(adev, 0, 0, 0, 0); 628 mutex_unlock(&adev->srbm_mutex); 629 630 /* unhalt MES and activate pipe0 */ 631 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 632 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 633 adev->enable_mes_kiq ? 1 : 0); 634 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 635 636 if (amdgpu_emu_mode) 637 msleep(100); 638 else 639 udelay(50); 640 } else { 641 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 642 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 643 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 644 data = REG_SET_FIELD(data, CP_MES_CNTL, 645 MES_INVALIDATE_ICACHE, 1); 646 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 647 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 648 adev->enable_mes_kiq ? 1 : 0); 649 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 650 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 651 } 652 } 653 654 /* This function is for backdoor MES firmware */ 655 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 656 enum admgpu_mes_pipe pipe, bool prime_icache) 657 { 658 int r; 659 uint32_t data; 660 uint64_t ucode_addr; 661 662 mes_v11_0_enable(adev, false); 663 664 if (!adev->mes.fw[pipe]) 665 return -EINVAL; 666 667 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 668 if (r) 669 return r; 670 671 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 672 if (r) { 673 mes_v11_0_free_ucode_buffers(adev, pipe); 674 return r; 675 } 676 677 mutex_lock(&adev->srbm_mutex); 678 /* me=3, pipe=0, queue=0 */ 679 soc21_grbm_select(adev, 3, pipe, 0, 0); 680 681 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 682 683 /* set ucode start address */ 684 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 685 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 686 lower_32_bits(ucode_addr)); 687 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 688 upper_32_bits(ucode_addr)); 689 690 /* set ucode fimrware address */ 691 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 692 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 693 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 694 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 695 696 /* set ucode instruction cache boundary to 2M-1 */ 697 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 698 699 /* set ucode data firmware address */ 700 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 701 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 702 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 703 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 704 705 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 706 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 707 708 if (prime_icache) { 709 /* invalidate ICACHE */ 710 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 711 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 712 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 713 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 714 715 /* prime the ICACHE. */ 716 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 717 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 718 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 719 } 720 721 soc21_grbm_select(adev, 0, 0, 0, 0); 722 mutex_unlock(&adev->srbm_mutex); 723 724 return 0; 725 } 726 727 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 728 enum admgpu_mes_pipe pipe) 729 { 730 int r; 731 u32 *eop; 732 733 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 734 AMDGPU_GEM_DOMAIN_GTT, 735 &adev->mes.eop_gpu_obj[pipe], 736 &adev->mes.eop_gpu_addr[pipe], 737 (void **)&eop); 738 if (r) { 739 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 740 return r; 741 } 742 743 memset(eop, 0, 744 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 745 746 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 747 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 748 749 return 0; 750 } 751 752 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 753 { 754 struct v11_compute_mqd *mqd = ring->mqd_ptr; 755 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 756 uint32_t tmp; 757 758 mqd->header = 0xC0310800; 759 mqd->compute_pipelinestat_enable = 0x00000001; 760 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 761 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 762 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 763 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 764 mqd->compute_misc_reserved = 0x00000007; 765 766 eop_base_addr = ring->eop_gpu_addr >> 8; 767 768 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 769 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 770 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 771 (order_base_2(MES_EOP_SIZE / 4) - 1)); 772 773 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 774 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 775 mqd->cp_hqd_eop_control = tmp; 776 777 /* disable the queue if it's active */ 778 ring->wptr = 0; 779 mqd->cp_hqd_pq_rptr = 0; 780 mqd->cp_hqd_pq_wptr_lo = 0; 781 mqd->cp_hqd_pq_wptr_hi = 0; 782 783 /* set the pointer to the MQD */ 784 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 785 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 786 787 /* set MQD vmid to 0 */ 788 tmp = regCP_MQD_CONTROL_DEFAULT; 789 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 790 mqd->cp_mqd_control = tmp; 791 792 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 793 hqd_gpu_addr = ring->gpu_addr >> 8; 794 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 795 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 796 797 /* set the wb address whether it's enabled or not */ 798 wb_gpu_addr = ring->rptr_gpu_addr; 799 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 800 mqd->cp_hqd_pq_rptr_report_addr_hi = 801 upper_32_bits(wb_gpu_addr) & 0xffff; 802 803 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 804 wb_gpu_addr = ring->wptr_gpu_addr; 805 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 806 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 807 808 /* set up the HQD, this is similar to CP_RB0_CNTL */ 809 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 810 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 811 (order_base_2(ring->ring_size / 4) - 1)); 812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 813 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 819 mqd->cp_hqd_pq_control = tmp; 820 821 /* enable doorbell */ 822 tmp = 0; 823 if (ring->use_doorbell) { 824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 825 DOORBELL_OFFSET, ring->doorbell_index); 826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 827 DOORBELL_EN, 1); 828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 829 DOORBELL_SOURCE, 0); 830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 831 DOORBELL_HIT, 0); 832 } 833 else 834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 835 DOORBELL_EN, 0); 836 mqd->cp_hqd_pq_doorbell_control = tmp; 837 838 mqd->cp_hqd_vmid = 0; 839 /* activate the queue */ 840 mqd->cp_hqd_active = 1; 841 842 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 843 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 844 PRELOAD_SIZE, 0x55); 845 mqd->cp_hqd_persistent_state = tmp; 846 847 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 848 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 849 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 850 851 return 0; 852 } 853 854 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 855 { 856 struct v11_compute_mqd *mqd = ring->mqd_ptr; 857 struct amdgpu_device *adev = ring->adev; 858 uint32_t data = 0; 859 860 mutex_lock(&adev->srbm_mutex); 861 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 862 863 /* set CP_HQD_VMID.VMID = 0. */ 864 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 865 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 866 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 867 868 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 869 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 870 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 871 DOORBELL_EN, 0); 872 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 873 874 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 875 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 876 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 877 878 /* set CP_MQD_CONTROL.VMID=0 */ 879 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 880 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 881 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 882 883 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 884 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 885 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 886 887 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 888 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 889 mqd->cp_hqd_pq_rptr_report_addr_lo); 890 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 891 mqd->cp_hqd_pq_rptr_report_addr_hi); 892 893 /* set CP_HQD_PQ_CONTROL */ 894 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 895 896 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 897 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 898 mqd->cp_hqd_pq_wptr_poll_addr_lo); 899 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 900 mqd->cp_hqd_pq_wptr_poll_addr_hi); 901 902 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 903 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 904 mqd->cp_hqd_pq_doorbell_control); 905 906 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 907 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 908 909 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 910 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 911 912 soc21_grbm_select(adev, 0, 0, 0, 0); 913 mutex_unlock(&adev->srbm_mutex); 914 } 915 916 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 917 { 918 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 919 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 920 int r; 921 922 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 923 return -EINVAL; 924 925 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 926 if (r) { 927 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 928 return r; 929 } 930 931 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 932 933 r = amdgpu_ring_test_ring(kiq_ring); 934 if (r) { 935 DRM_ERROR("kfq enable failed\n"); 936 kiq_ring->sched.ready = false; 937 } 938 return r; 939 } 940 941 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 942 enum admgpu_mes_pipe pipe) 943 { 944 struct amdgpu_ring *ring; 945 int r; 946 947 if (pipe == AMDGPU_MES_KIQ_PIPE) 948 ring = &adev->gfx.kiq.ring; 949 else if (pipe == AMDGPU_MES_SCHED_PIPE) 950 ring = &adev->mes.ring; 951 else 952 BUG(); 953 954 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 955 (amdgpu_in_reset(adev) || adev->in_suspend)) { 956 *(ring->wptr_cpu_addr) = 0; 957 *(ring->rptr_cpu_addr) = 0; 958 amdgpu_ring_clear_ring(ring); 959 } 960 961 r = mes_v11_0_mqd_init(ring); 962 if (r) 963 return r; 964 965 if (pipe == AMDGPU_MES_SCHED_PIPE) { 966 r = mes_v11_0_kiq_enable_queue(adev); 967 if (r) 968 return r; 969 } else { 970 mes_v11_0_queue_init_register(ring); 971 } 972 973 /* get MES scheduler/KIQ versions */ 974 mutex_lock(&adev->srbm_mutex); 975 soc21_grbm_select(adev, 3, pipe, 0, 0); 976 977 if (pipe == AMDGPU_MES_SCHED_PIPE) 978 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 979 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 980 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 981 982 soc21_grbm_select(adev, 0, 0, 0, 0); 983 mutex_unlock(&adev->srbm_mutex); 984 985 return 0; 986 } 987 988 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 989 { 990 struct amdgpu_ring *ring; 991 992 ring = &adev->mes.ring; 993 994 ring->funcs = &mes_v11_0_ring_funcs; 995 996 ring->me = 3; 997 ring->pipe = 0; 998 ring->queue = 0; 999 1000 ring->ring_obj = NULL; 1001 ring->use_doorbell = true; 1002 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1003 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1004 ring->no_scheduler = true; 1005 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1006 1007 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1008 AMDGPU_RING_PRIO_DEFAULT, NULL); 1009 } 1010 1011 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1012 { 1013 struct amdgpu_ring *ring; 1014 1015 spin_lock_init(&adev->gfx.kiq.ring_lock); 1016 1017 ring = &adev->gfx.kiq.ring; 1018 1019 ring->me = 3; 1020 ring->pipe = 1; 1021 ring->queue = 0; 1022 1023 ring->adev = NULL; 1024 ring->ring_obj = NULL; 1025 ring->use_doorbell = true; 1026 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1027 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1028 ring->no_scheduler = true; 1029 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1030 ring->me, ring->pipe, ring->queue); 1031 1032 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1033 AMDGPU_RING_PRIO_DEFAULT, NULL); 1034 } 1035 1036 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1037 enum admgpu_mes_pipe pipe) 1038 { 1039 int r, mqd_size = sizeof(struct v11_compute_mqd); 1040 struct amdgpu_ring *ring; 1041 1042 if (pipe == AMDGPU_MES_KIQ_PIPE) 1043 ring = &adev->gfx.kiq.ring; 1044 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1045 ring = &adev->mes.ring; 1046 else 1047 BUG(); 1048 1049 if (ring->mqd_obj) 1050 return 0; 1051 1052 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1053 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1054 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1055 if (r) { 1056 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1057 return r; 1058 } 1059 1060 memset(ring->mqd_ptr, 0, mqd_size); 1061 1062 /* prepare MQD backup */ 1063 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1064 if (!adev->mes.mqd_backup[pipe]) 1065 dev_warn(adev->dev, 1066 "no memory to create MQD backup for ring %s\n", 1067 ring->name); 1068 1069 return 0; 1070 } 1071 1072 static int mes_v11_0_sw_init(void *handle) 1073 { 1074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1075 int pipe, r; 1076 1077 adev->mes.adev = adev; 1078 adev->mes.funcs = &mes_v11_0_funcs; 1079 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1080 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1081 1082 r = amdgpu_mes_init(adev); 1083 if (r) 1084 return r; 1085 1086 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1087 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1088 continue; 1089 1090 r = mes_v11_0_init_microcode(adev, pipe); 1091 if (r) 1092 return r; 1093 1094 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1095 if (r) 1096 return r; 1097 1098 r = mes_v11_0_mqd_sw_init(adev, pipe); 1099 if (r) 1100 return r; 1101 } 1102 1103 if (adev->enable_mes_kiq) { 1104 r = mes_v11_0_kiq_ring_init(adev); 1105 if (r) 1106 return r; 1107 } 1108 1109 r = mes_v11_0_ring_init(adev); 1110 if (r) 1111 return r; 1112 1113 return 0; 1114 } 1115 1116 static int mes_v11_0_sw_fini(void *handle) 1117 { 1118 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1119 int pipe; 1120 1121 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1122 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1123 1124 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1125 kfree(adev->mes.mqd_backup[pipe]); 1126 1127 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1128 &adev->mes.eop_gpu_addr[pipe], 1129 NULL); 1130 1131 mes_v11_0_free_microcode(adev, pipe); 1132 } 1133 1134 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1135 &adev->gfx.kiq.ring.mqd_gpu_addr, 1136 &adev->gfx.kiq.ring.mqd_ptr); 1137 1138 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1139 &adev->mes.ring.mqd_gpu_addr, 1140 &adev->mes.ring.mqd_ptr); 1141 1142 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1143 amdgpu_ring_fini(&adev->mes.ring); 1144 1145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1146 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1147 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1148 } 1149 1150 amdgpu_mes_fini(adev); 1151 return 0; 1152 } 1153 1154 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1155 { 1156 uint32_t tmp; 1157 struct amdgpu_device *adev = ring->adev; 1158 1159 /* tell RLC which is KIQ queue */ 1160 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1161 tmp &= 0xffffff00; 1162 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1163 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1164 tmp |= 0x80; 1165 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1166 } 1167 1168 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1169 { 1170 int r = 0; 1171 1172 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1173 1174 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1175 if (r) { 1176 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1177 return r; 1178 } 1179 1180 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1181 if (r) { 1182 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1183 return r; 1184 } 1185 1186 } 1187 1188 mes_v11_0_enable(adev, true); 1189 1190 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1191 1192 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1193 if (r) 1194 goto failure; 1195 1196 return r; 1197 1198 failure: 1199 mes_v11_0_hw_fini(adev); 1200 return r; 1201 } 1202 1203 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1204 { 1205 mes_v11_0_enable(adev, false); 1206 return 0; 1207 } 1208 1209 static int mes_v11_0_hw_init(void *handle) 1210 { 1211 int r; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 if (!adev->enable_mes_kiq) { 1215 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1216 r = mes_v11_0_load_microcode(adev, 1217 AMDGPU_MES_SCHED_PIPE, true); 1218 if (r) { 1219 DRM_ERROR("failed to MES fw, r=%d\n", r); 1220 return r; 1221 } 1222 } 1223 1224 mes_v11_0_enable(adev, true); 1225 } 1226 1227 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1228 if (r) 1229 goto failure; 1230 1231 r = mes_v11_0_set_hw_resources(&adev->mes); 1232 if (r) 1233 goto failure; 1234 1235 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1236 1237 r = mes_v11_0_query_sched_status(&adev->mes); 1238 if (r) { 1239 DRM_ERROR("MES is busy\n"); 1240 goto failure; 1241 } 1242 1243 /* 1244 * Disable KIQ ring usage from the driver once MES is enabled. 1245 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1246 * with MES enabled. 1247 */ 1248 adev->gfx.kiq.ring.sched.ready = false; 1249 adev->mes.ring.sched.ready = true; 1250 1251 return 0; 1252 1253 failure: 1254 mes_v11_0_hw_fini(adev); 1255 return r; 1256 } 1257 1258 static int mes_v11_0_hw_fini(void *handle) 1259 { 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 1262 adev->mes.ring.sched.ready = false; 1263 return 0; 1264 } 1265 1266 static int mes_v11_0_suspend(void *handle) 1267 { 1268 int r; 1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1270 1271 r = amdgpu_mes_suspend(adev); 1272 if (r) 1273 return r; 1274 1275 return mes_v11_0_hw_fini(adev); 1276 } 1277 1278 static int mes_v11_0_resume(void *handle) 1279 { 1280 int r; 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 1283 r = mes_v11_0_hw_init(adev); 1284 if (r) 1285 return r; 1286 1287 return amdgpu_mes_resume(adev); 1288 } 1289 1290 static int mes_v11_0_late_init(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 1294 if (!amdgpu_in_reset(adev)) 1295 amdgpu_mes_self_test(adev); 1296 1297 return 0; 1298 } 1299 1300 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1301 .name = "mes_v11_0", 1302 .late_init = mes_v11_0_late_init, 1303 .sw_init = mes_v11_0_sw_init, 1304 .sw_fini = mes_v11_0_sw_fini, 1305 .hw_init = mes_v11_0_hw_init, 1306 .hw_fini = mes_v11_0_hw_fini, 1307 .suspend = mes_v11_0_suspend, 1308 .resume = mes_v11_0_resume, 1309 }; 1310 1311 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1312 .type = AMD_IP_BLOCK_TYPE_MES, 1313 .major = 11, 1314 .minor = 0, 1315 .rev = 0, 1316 .funcs = &mes_v11_0_ip_funcs, 1317 }; 1318