1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 42 static int mes_v11_0_hw_fini(void *handle); 43 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 44 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 45 46 #define MES_EOP_SIZE 2048 47 48 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 49 { 50 struct amdgpu_device *adev = ring->adev; 51 52 if (ring->use_doorbell) { 53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 54 ring->wptr); 55 WDOORBELL64(ring->doorbell_index, ring->wptr); 56 } else { 57 BUG(); 58 } 59 } 60 61 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 return *ring->rptr_cpu_addr; 64 } 65 66 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 67 { 68 u64 wptr; 69 70 if (ring->use_doorbell) 71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 72 else 73 BUG(); 74 return wptr; 75 } 76 77 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 78 .type = AMDGPU_RING_TYPE_MES, 79 .align_mask = 1, 80 .nop = 0, 81 .support_64bit_ptrs = true, 82 .get_rptr = mes_v11_0_ring_get_rptr, 83 .get_wptr = mes_v11_0_ring_get_wptr, 84 .set_wptr = mes_v11_0_ring_set_wptr, 85 .insert_nop = amdgpu_ring_insert_nop, 86 }; 87 88 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 89 void *pkt, int size) 90 { 91 int ndw = size / 4; 92 signed long r; 93 union MESAPI__ADD_QUEUE *x_pkt = pkt; 94 struct amdgpu_device *adev = mes->adev; 95 struct amdgpu_ring *ring = &mes->ring; 96 97 BUG_ON(size % 4 != 0); 98 99 if (amdgpu_ring_alloc(ring, ndw)) 100 return -ENOMEM; 101 102 amdgpu_ring_write_multiple(ring, pkt, ndw); 103 amdgpu_ring_commit(ring); 104 105 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 106 107 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 108 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 109 if (r < 1) { 110 DRM_ERROR("MES failed to response msg=%d\n", 111 x_pkt->header.opcode); 112 return -ETIMEDOUT; 113 } 114 115 return 0; 116 } 117 118 static int convert_to_mes_queue_type(int queue_type) 119 { 120 if (queue_type == AMDGPU_RING_TYPE_GFX) 121 return MES_QUEUE_TYPE_GFX; 122 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 123 return MES_QUEUE_TYPE_COMPUTE; 124 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 125 return MES_QUEUE_TYPE_SDMA; 126 else 127 BUG(); 128 return -1; 129 } 130 131 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 132 struct mes_add_queue_input *input) 133 { 134 struct amdgpu_device *adev = mes->adev; 135 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 136 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 137 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 138 139 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 140 141 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 142 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 143 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 144 145 mes_add_queue_pkt.process_id = input->process_id; 146 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 147 mes_add_queue_pkt.process_va_start = input->process_va_start; 148 mes_add_queue_pkt.process_va_end = input->process_va_end; 149 mes_add_queue_pkt.process_quantum = input->process_quantum; 150 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 151 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 152 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 153 mes_add_queue_pkt.inprocess_gang_priority = 154 input->inprocess_gang_priority; 155 mes_add_queue_pkt.gang_global_priority_level = 156 input->gang_global_priority_level; 157 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 158 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 159 160 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 161 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 162 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 163 else 164 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 165 166 mes_add_queue_pkt.queue_type = 167 convert_to_mes_queue_type(input->queue_type); 168 mes_add_queue_pkt.paging = input->paging; 169 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 170 mes_add_queue_pkt.gws_base = input->gws_base; 171 mes_add_queue_pkt.gws_size = input->gws_size; 172 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 173 mes_add_queue_pkt.tma_addr = input->tma_addr; 174 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 175 176 mes_add_queue_pkt.api_status.api_completion_fence_addr = 177 mes->ring.fence_drv.gpu_addr; 178 mes_add_queue_pkt.api_status.api_completion_fence_value = 179 ++mes->ring.fence_drv.sync_seq; 180 181 return mes_v11_0_submit_pkt_and_poll_completion(mes, 182 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt)); 183 } 184 185 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 186 struct mes_remove_queue_input *input) 187 { 188 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 189 190 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 191 192 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 193 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 194 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 195 196 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 197 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 198 199 mes_remove_queue_pkt.api_status.api_completion_fence_addr = 200 mes->ring.fence_drv.gpu_addr; 201 mes_remove_queue_pkt.api_status.api_completion_fence_value = 202 ++mes->ring.fence_drv.sync_seq; 203 204 return mes_v11_0_submit_pkt_and_poll_completion(mes, 205 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt)); 206 } 207 208 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 209 struct mes_unmap_legacy_queue_input *input) 210 { 211 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 212 213 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 214 215 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 216 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 217 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 218 219 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset << 2; 220 mes_remove_queue_pkt.gang_context_addr = 0; 221 222 mes_remove_queue_pkt.pipe_id = input->pipe_id; 223 mes_remove_queue_pkt.queue_id = input->queue_id; 224 225 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 226 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 227 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 228 mes_remove_queue_pkt.tf_data = 229 lower_32_bits(input->trail_fence_data); 230 } else { 231 if (input->queue_type == AMDGPU_RING_TYPE_GFX) 232 mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1; 233 else 234 mes_remove_queue_pkt.unmap_kiq_utility_queue = 1; 235 } 236 237 mes_remove_queue_pkt.api_status.api_completion_fence_addr = 238 mes->ring.fence_drv.gpu_addr; 239 mes_remove_queue_pkt.api_status.api_completion_fence_value = 240 ++mes->ring.fence_drv.sync_seq; 241 242 return mes_v11_0_submit_pkt_and_poll_completion(mes, 243 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt)); 244 } 245 246 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 247 struct mes_suspend_gang_input *input) 248 { 249 return 0; 250 } 251 252 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 253 struct mes_resume_gang_input *input) 254 { 255 return 0; 256 } 257 258 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 259 { 260 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 261 262 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 263 264 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 265 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 266 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 267 268 mes_status_pkt.api_status.api_completion_fence_addr = 269 mes->ring.fence_drv.gpu_addr; 270 mes_status_pkt.api_status.api_completion_fence_value = 271 ++mes->ring.fence_drv.sync_seq; 272 273 return mes_v11_0_submit_pkt_and_poll_completion(mes, 274 &mes_status_pkt, sizeof(mes_status_pkt)); 275 } 276 277 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 278 struct mes_misc_op_input *input) 279 { 280 union MESAPI__MISC misc_pkt; 281 282 memset(&misc_pkt, 0, sizeof(misc_pkt)); 283 284 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 285 misc_pkt.header.opcode = MES_SCH_API_MISC; 286 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 287 288 switch (input->op) { 289 case MES_MISC_OP_READ_REG: 290 misc_pkt.opcode = MESAPI_MISC__READ_REG; 291 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 292 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 293 break; 294 case MES_MISC_OP_WRITE_REG: 295 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 296 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 297 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 298 break; 299 case MES_MISC_OP_WRM_REG_WAIT: 300 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 301 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 302 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 303 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 304 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 305 misc_pkt.wait_reg_mem.reg_offset2 = 0; 306 break; 307 case MES_MISC_OP_WRM_REG_WR_WAIT: 308 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 309 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 310 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 311 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 312 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 313 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 314 break; 315 default: 316 DRM_ERROR("unsupported misc op (%d) \n", input->op); 317 return -EINVAL; 318 } 319 320 misc_pkt.api_status.api_completion_fence_addr = 321 mes->ring.fence_drv.gpu_addr; 322 misc_pkt.api_status.api_completion_fence_value = 323 ++mes->ring.fence_drv.sync_seq; 324 325 return mes_v11_0_submit_pkt_and_poll_completion(mes, 326 &misc_pkt, sizeof(misc_pkt)); 327 } 328 329 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 330 { 331 int i; 332 struct amdgpu_device *adev = mes->adev; 333 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 334 335 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 336 337 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 338 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 339 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 340 341 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 342 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 343 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 344 mes_set_hw_res_pkt.paging_vmid = 0; 345 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 346 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 347 mes->query_status_fence_gpu_addr; 348 349 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 350 mes_set_hw_res_pkt.compute_hqd_mask[i] = 351 mes->compute_hqd_mask[i]; 352 353 for (i = 0; i < MAX_GFX_PIPES; i++) 354 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 355 356 for (i = 0; i < MAX_SDMA_PIPES; i++) 357 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 358 359 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 360 mes_set_hw_res_pkt.aggregated_doorbells[i] = 361 mes->agreegated_doorbells[i]; 362 363 for (i = 0; i < 5; i++) { 364 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 365 mes_set_hw_res_pkt.mmhub_base[i] = 366 adev->reg_offset[MMHUB_HWIP][0][i]; 367 mes_set_hw_res_pkt.osssys_base[i] = 368 adev->reg_offset[OSSSYS_HWIP][0][i]; 369 } 370 371 mes_set_hw_res_pkt.disable_reset = 1; 372 mes_set_hw_res_pkt.disable_mes_log = 1; 373 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 374 mes_set_hw_res_pkt.oversubscription_timer = 50; 375 376 mes_set_hw_res_pkt.api_status.api_completion_fence_addr = 377 mes->ring.fence_drv.gpu_addr; 378 mes_set_hw_res_pkt.api_status.api_completion_fence_value = 379 ++mes->ring.fence_drv.sync_seq; 380 381 return mes_v11_0_submit_pkt_and_poll_completion(mes, 382 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt)); 383 } 384 385 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 386 .add_hw_queue = mes_v11_0_add_hw_queue, 387 .remove_hw_queue = mes_v11_0_remove_hw_queue, 388 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 389 .suspend_gang = mes_v11_0_suspend_gang, 390 .resume_gang = mes_v11_0_resume_gang, 391 .misc_op = mes_v11_0_misc_op, 392 }; 393 394 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 395 enum admgpu_mes_pipe pipe) 396 { 397 char fw_name[30]; 398 char ucode_prefix[30]; 399 int err; 400 const struct mes_firmware_header_v1_0 *mes_hdr; 401 struct amdgpu_firmware_info *info; 402 403 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 404 405 if (pipe == AMDGPU_MES_SCHED_PIPE) 406 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 407 ucode_prefix); 408 else 409 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 410 ucode_prefix); 411 412 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 413 if (err) 414 return err; 415 416 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 417 if (err) { 418 release_firmware(adev->mes.fw[pipe]); 419 adev->mes.fw[pipe] = NULL; 420 return err; 421 } 422 423 mes_hdr = (const struct mes_firmware_header_v1_0 *) 424 adev->mes.fw[pipe]->data; 425 adev->mes.ucode_fw_version[pipe] = 426 le32_to_cpu(mes_hdr->mes_ucode_version); 427 adev->mes.ucode_fw_version[pipe] = 428 le32_to_cpu(mes_hdr->mes_ucode_data_version); 429 adev->mes.uc_start_addr[pipe] = 430 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 431 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 432 adev->mes.data_start_addr[pipe] = 433 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 434 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 435 436 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 437 int ucode, ucode_data; 438 439 if (pipe == AMDGPU_MES_SCHED_PIPE) { 440 ucode = AMDGPU_UCODE_ID_CP_MES; 441 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 442 } else { 443 ucode = AMDGPU_UCODE_ID_CP_MES1; 444 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 445 } 446 447 info = &adev->firmware.ucode[ucode]; 448 info->ucode_id = ucode; 449 info->fw = adev->mes.fw[pipe]; 450 adev->firmware.fw_size += 451 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 452 PAGE_SIZE); 453 454 info = &adev->firmware.ucode[ucode_data]; 455 info->ucode_id = ucode_data; 456 info->fw = adev->mes.fw[pipe]; 457 adev->firmware.fw_size += 458 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 459 PAGE_SIZE); 460 } 461 462 return 0; 463 } 464 465 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 466 enum admgpu_mes_pipe pipe) 467 { 468 release_firmware(adev->mes.fw[pipe]); 469 adev->mes.fw[pipe] = NULL; 470 } 471 472 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 473 enum admgpu_mes_pipe pipe) 474 { 475 int r; 476 const struct mes_firmware_header_v1_0 *mes_hdr; 477 const __le32 *fw_data; 478 unsigned fw_size; 479 480 mes_hdr = (const struct mes_firmware_header_v1_0 *) 481 adev->mes.fw[pipe]->data; 482 483 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 484 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 485 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 486 487 r = amdgpu_bo_create_reserved(adev, fw_size, 488 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 489 &adev->mes.ucode_fw_obj[pipe], 490 &adev->mes.ucode_fw_gpu_addr[pipe], 491 (void **)&adev->mes.ucode_fw_ptr[pipe]); 492 if (r) { 493 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 494 return r; 495 } 496 497 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 498 499 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 500 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 501 502 return 0; 503 } 504 505 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 506 enum admgpu_mes_pipe pipe) 507 { 508 int r; 509 const struct mes_firmware_header_v1_0 *mes_hdr; 510 const __le32 *fw_data; 511 unsigned fw_size; 512 513 mes_hdr = (const struct mes_firmware_header_v1_0 *) 514 adev->mes.fw[pipe]->data; 515 516 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 517 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 518 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 519 520 r = amdgpu_bo_create_reserved(adev, fw_size, 521 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 522 &adev->mes.data_fw_obj[pipe], 523 &adev->mes.data_fw_gpu_addr[pipe], 524 (void **)&adev->mes.data_fw_ptr[pipe]); 525 if (r) { 526 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 527 return r; 528 } 529 530 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 531 532 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 533 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 534 535 return 0; 536 } 537 538 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 539 enum admgpu_mes_pipe pipe) 540 { 541 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 542 &adev->mes.data_fw_gpu_addr[pipe], 543 (void **)&adev->mes.data_fw_ptr[pipe]); 544 545 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 546 &adev->mes.ucode_fw_gpu_addr[pipe], 547 (void **)&adev->mes.ucode_fw_ptr[pipe]); 548 } 549 550 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 551 { 552 uint64_t ucode_addr; 553 uint32_t pipe, data = 0; 554 555 if (enable) { 556 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 557 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 558 data = REG_SET_FIELD(data, CP_MES_CNTL, 559 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 560 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 561 562 mutex_lock(&adev->srbm_mutex); 563 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 564 if (!adev->enable_mes_kiq && 565 pipe == AMDGPU_MES_KIQ_PIPE) 566 continue; 567 568 soc21_grbm_select(adev, 3, pipe, 0, 0); 569 570 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 571 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 572 lower_32_bits(ucode_addr)); 573 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 574 upper_32_bits(ucode_addr)); 575 } 576 soc21_grbm_select(adev, 0, 0, 0, 0); 577 mutex_unlock(&adev->srbm_mutex); 578 579 /* unhalt MES and activate pipe0 */ 580 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 581 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 582 adev->enable_mes_kiq ? 1 : 0); 583 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 584 585 if (amdgpu_emu_mode) 586 msleep(100); 587 else 588 udelay(50); 589 } else { 590 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 591 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 592 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 593 data = REG_SET_FIELD(data, CP_MES_CNTL, 594 MES_INVALIDATE_ICACHE, 1); 595 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 596 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 597 adev->enable_mes_kiq ? 1 : 0); 598 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 599 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 600 } 601 } 602 603 /* This function is for backdoor MES firmware */ 604 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 605 enum admgpu_mes_pipe pipe, bool prime_icache) 606 { 607 int r; 608 uint32_t data; 609 uint64_t ucode_addr; 610 611 mes_v11_0_enable(adev, false); 612 613 if (!adev->mes.fw[pipe]) 614 return -EINVAL; 615 616 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 617 if (r) 618 return r; 619 620 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 621 if (r) { 622 mes_v11_0_free_ucode_buffers(adev, pipe); 623 return r; 624 } 625 626 mutex_lock(&adev->srbm_mutex); 627 /* me=3, pipe=0, queue=0 */ 628 soc21_grbm_select(adev, 3, pipe, 0, 0); 629 630 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 631 632 /* set ucode start address */ 633 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 634 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 635 lower_32_bits(ucode_addr)); 636 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 637 upper_32_bits(ucode_addr)); 638 639 /* set ucode fimrware address */ 640 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 641 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 642 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 643 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 644 645 /* set ucode instruction cache boundary to 2M-1 */ 646 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 647 648 /* set ucode data firmware address */ 649 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 650 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 651 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 652 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 653 654 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 655 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 656 657 if (prime_icache) { 658 /* invalidate ICACHE */ 659 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 660 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 661 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 662 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 663 664 /* prime the ICACHE. */ 665 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 666 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 667 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 668 } 669 670 soc21_grbm_select(adev, 0, 0, 0, 0); 671 mutex_unlock(&adev->srbm_mutex); 672 673 return 0; 674 } 675 676 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 677 enum admgpu_mes_pipe pipe) 678 { 679 int r; 680 u32 *eop; 681 682 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 683 AMDGPU_GEM_DOMAIN_GTT, 684 &adev->mes.eop_gpu_obj[pipe], 685 &adev->mes.eop_gpu_addr[pipe], 686 (void **)&eop); 687 if (r) { 688 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 689 return r; 690 } 691 692 memset(eop, 0, 693 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 694 695 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 696 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 697 698 return 0; 699 } 700 701 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 702 { 703 struct v11_compute_mqd *mqd = ring->mqd_ptr; 704 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 705 uint32_t tmp; 706 707 mqd->header = 0xC0310800; 708 mqd->compute_pipelinestat_enable = 0x00000001; 709 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 710 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 711 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 712 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 713 mqd->compute_misc_reserved = 0x00000007; 714 715 eop_base_addr = ring->eop_gpu_addr >> 8; 716 717 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 718 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 719 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 720 (order_base_2(MES_EOP_SIZE / 4) - 1)); 721 722 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 723 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 724 mqd->cp_hqd_eop_control = tmp; 725 726 /* disable the queue if it's active */ 727 ring->wptr = 0; 728 mqd->cp_hqd_pq_rptr = 0; 729 mqd->cp_hqd_pq_wptr_lo = 0; 730 mqd->cp_hqd_pq_wptr_hi = 0; 731 732 /* set the pointer to the MQD */ 733 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 734 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 735 736 /* set MQD vmid to 0 */ 737 tmp = regCP_MQD_CONTROL_DEFAULT; 738 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 739 mqd->cp_mqd_control = tmp; 740 741 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 742 hqd_gpu_addr = ring->gpu_addr >> 8; 743 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 744 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 745 746 /* set the wb address whether it's enabled or not */ 747 wb_gpu_addr = ring->rptr_gpu_addr; 748 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 749 mqd->cp_hqd_pq_rptr_report_addr_hi = 750 upper_32_bits(wb_gpu_addr) & 0xffff; 751 752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 753 wb_gpu_addr = ring->wptr_gpu_addr; 754 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 755 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 756 757 /* set up the HQD, this is similar to CP_RB0_CNTL */ 758 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 760 (order_base_2(ring->ring_size / 4) - 1)); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 762 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 763 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 764 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 765 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 766 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 767 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 768 mqd->cp_hqd_pq_control = tmp; 769 770 /* enable doorbell */ 771 tmp = 0; 772 if (ring->use_doorbell) { 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 774 DOORBELL_OFFSET, ring->doorbell_index); 775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 776 DOORBELL_EN, 1); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 778 DOORBELL_SOURCE, 0); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 780 DOORBELL_HIT, 0); 781 } 782 else 783 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 784 DOORBELL_EN, 0); 785 mqd->cp_hqd_pq_doorbell_control = tmp; 786 787 mqd->cp_hqd_vmid = 0; 788 /* activate the queue */ 789 mqd->cp_hqd_active = 1; 790 791 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 792 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 793 PRELOAD_SIZE, 0x55); 794 mqd->cp_hqd_persistent_state = tmp; 795 796 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 797 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 798 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 799 800 return 0; 801 } 802 803 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 804 { 805 struct v11_compute_mqd *mqd = ring->mqd_ptr; 806 struct amdgpu_device *adev = ring->adev; 807 uint32_t data = 0; 808 809 mutex_lock(&adev->srbm_mutex); 810 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 811 812 /* set CP_HQD_VMID.VMID = 0. */ 813 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 814 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 815 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 816 817 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 818 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 819 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 820 DOORBELL_EN, 0); 821 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 822 823 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 824 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 825 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 826 827 /* set CP_MQD_CONTROL.VMID=0 */ 828 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 829 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 830 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 831 832 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 833 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 835 836 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 837 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 838 mqd->cp_hqd_pq_rptr_report_addr_lo); 839 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 840 mqd->cp_hqd_pq_rptr_report_addr_hi); 841 842 /* set CP_HQD_PQ_CONTROL */ 843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 844 845 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 847 mqd->cp_hqd_pq_wptr_poll_addr_lo); 848 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 849 mqd->cp_hqd_pq_wptr_poll_addr_hi); 850 851 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 853 mqd->cp_hqd_pq_doorbell_control); 854 855 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 856 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 857 858 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 859 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 860 861 soc21_grbm_select(adev, 0, 0, 0, 0); 862 mutex_unlock(&adev->srbm_mutex); 863 } 864 865 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 866 { 867 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 868 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 869 int r; 870 871 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 872 return -EINVAL; 873 874 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 875 if (r) { 876 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 877 return r; 878 } 879 880 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 881 882 r = amdgpu_ring_test_ring(kiq_ring); 883 if (r) { 884 DRM_ERROR("kfq enable failed\n"); 885 kiq_ring->sched.ready = false; 886 } 887 return r; 888 } 889 890 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 891 enum admgpu_mes_pipe pipe) 892 { 893 struct amdgpu_ring *ring; 894 int r; 895 896 if (pipe == AMDGPU_MES_KIQ_PIPE) 897 ring = &adev->gfx.kiq.ring; 898 else if (pipe == AMDGPU_MES_SCHED_PIPE) 899 ring = &adev->mes.ring; 900 else 901 BUG(); 902 903 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 904 (amdgpu_in_reset(adev) || adev->in_suspend)) { 905 *(ring->wptr_cpu_addr) = 0; 906 *(ring->rptr_cpu_addr) = 0; 907 amdgpu_ring_clear_ring(ring); 908 } 909 910 r = mes_v11_0_mqd_init(ring); 911 if (r) 912 return r; 913 914 if (pipe == AMDGPU_MES_SCHED_PIPE) { 915 r = mes_v11_0_kiq_enable_queue(adev); 916 if (r) 917 return r; 918 } else { 919 mes_v11_0_queue_init_register(ring); 920 } 921 922 /* get MES scheduler/KIQ versions */ 923 mutex_lock(&adev->srbm_mutex); 924 soc21_grbm_select(adev, 3, pipe, 0, 0); 925 926 if (pipe == AMDGPU_MES_SCHED_PIPE) 927 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 928 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 929 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 930 931 soc21_grbm_select(adev, 0, 0, 0, 0); 932 mutex_unlock(&adev->srbm_mutex); 933 934 return 0; 935 } 936 937 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 938 { 939 struct amdgpu_ring *ring; 940 941 ring = &adev->mes.ring; 942 943 ring->funcs = &mes_v11_0_ring_funcs; 944 945 ring->me = 3; 946 ring->pipe = 0; 947 ring->queue = 0; 948 949 ring->ring_obj = NULL; 950 ring->use_doorbell = true; 951 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 952 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 953 ring->no_scheduler = true; 954 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 955 956 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 957 AMDGPU_RING_PRIO_DEFAULT, NULL); 958 } 959 960 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 961 { 962 struct amdgpu_ring *ring; 963 964 spin_lock_init(&adev->gfx.kiq.ring_lock); 965 966 ring = &adev->gfx.kiq.ring; 967 968 ring->me = 3; 969 ring->pipe = 1; 970 ring->queue = 0; 971 972 ring->adev = NULL; 973 ring->ring_obj = NULL; 974 ring->use_doorbell = true; 975 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 976 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 977 ring->no_scheduler = true; 978 sprintf(ring->name, "mes_kiq_%d.%d.%d", 979 ring->me, ring->pipe, ring->queue); 980 981 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 } 984 985 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 986 enum admgpu_mes_pipe pipe) 987 { 988 int r, mqd_size = sizeof(struct v11_compute_mqd); 989 struct amdgpu_ring *ring; 990 991 if (pipe == AMDGPU_MES_KIQ_PIPE) 992 ring = &adev->gfx.kiq.ring; 993 else if (pipe == AMDGPU_MES_SCHED_PIPE) 994 ring = &adev->mes.ring; 995 else 996 BUG(); 997 998 if (ring->mqd_obj) 999 return 0; 1000 1001 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1002 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1003 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1004 if (r) { 1005 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1006 return r; 1007 } 1008 1009 memset(ring->mqd_ptr, 0, mqd_size); 1010 1011 /* prepare MQD backup */ 1012 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1013 if (!adev->mes.mqd_backup[pipe]) 1014 dev_warn(adev->dev, 1015 "no memory to create MQD backup for ring %s\n", 1016 ring->name); 1017 1018 return 0; 1019 } 1020 1021 static int mes_v11_0_sw_init(void *handle) 1022 { 1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1024 int pipe, r; 1025 1026 adev->mes.adev = adev; 1027 adev->mes.funcs = &mes_v11_0_funcs; 1028 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1029 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1030 1031 r = amdgpu_mes_init(adev); 1032 if (r) 1033 return r; 1034 1035 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1036 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1037 continue; 1038 1039 r = mes_v11_0_init_microcode(adev, pipe); 1040 if (r) 1041 return r; 1042 1043 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1044 if (r) 1045 return r; 1046 1047 r = mes_v11_0_mqd_sw_init(adev, pipe); 1048 if (r) 1049 return r; 1050 } 1051 1052 if (adev->enable_mes_kiq) { 1053 r = mes_v11_0_kiq_ring_init(adev); 1054 if (r) 1055 return r; 1056 } 1057 1058 r = mes_v11_0_ring_init(adev); 1059 if (r) 1060 return r; 1061 1062 return 0; 1063 } 1064 1065 static int mes_v11_0_sw_fini(void *handle) 1066 { 1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068 int pipe; 1069 1070 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1071 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1072 1073 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1074 kfree(adev->mes.mqd_backup[pipe]); 1075 1076 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1077 &adev->mes.eop_gpu_addr[pipe], 1078 NULL); 1079 1080 mes_v11_0_free_microcode(adev, pipe); 1081 } 1082 1083 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1084 &adev->gfx.kiq.ring.mqd_gpu_addr, 1085 &adev->gfx.kiq.ring.mqd_ptr); 1086 1087 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1088 &adev->mes.ring.mqd_gpu_addr, 1089 &adev->mes.ring.mqd_ptr); 1090 1091 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1092 amdgpu_ring_fini(&adev->mes.ring); 1093 1094 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1095 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1096 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1097 } 1098 1099 amdgpu_mes_fini(adev); 1100 return 0; 1101 } 1102 1103 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1104 { 1105 uint32_t tmp; 1106 struct amdgpu_device *adev = ring->adev; 1107 1108 /* tell RLC which is KIQ queue */ 1109 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1110 tmp &= 0xffffff00; 1111 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1112 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1113 tmp |= 0x80; 1114 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1115 } 1116 1117 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1118 { 1119 int r = 0; 1120 1121 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1122 1123 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1124 if (r) { 1125 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1126 return r; 1127 } 1128 1129 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1130 if (r) { 1131 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1132 return r; 1133 } 1134 1135 } 1136 1137 mes_v11_0_enable(adev, true); 1138 1139 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1140 1141 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1142 if (r) 1143 goto failure; 1144 1145 return r; 1146 1147 failure: 1148 mes_v11_0_hw_fini(adev); 1149 return r; 1150 } 1151 1152 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1153 { 1154 mes_v11_0_enable(adev, false); 1155 return 0; 1156 } 1157 1158 static int mes_v11_0_hw_init(void *handle) 1159 { 1160 int r; 1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1162 1163 if (!adev->enable_mes_kiq) { 1164 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1165 r = mes_v11_0_load_microcode(adev, 1166 AMDGPU_MES_SCHED_PIPE, true); 1167 if (r) { 1168 DRM_ERROR("failed to MES fw, r=%d\n", r); 1169 return r; 1170 } 1171 } 1172 1173 mes_v11_0_enable(adev, true); 1174 } 1175 1176 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1177 if (r) 1178 goto failure; 1179 1180 r = mes_v11_0_set_hw_resources(&adev->mes); 1181 if (r) 1182 goto failure; 1183 1184 r = mes_v11_0_query_sched_status(&adev->mes); 1185 if (r) { 1186 DRM_ERROR("MES is busy\n"); 1187 goto failure; 1188 } 1189 1190 /* 1191 * Disable KIQ ring usage from the driver once MES is enabled. 1192 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1193 * with MES enabled. 1194 */ 1195 adev->gfx.kiq.ring.sched.ready = false; 1196 adev->mes.ring.sched.ready = true; 1197 1198 return 0; 1199 1200 failure: 1201 mes_v11_0_hw_fini(adev); 1202 return r; 1203 } 1204 1205 static int mes_v11_0_hw_fini(void *handle) 1206 { 1207 return 0; 1208 } 1209 1210 static int mes_v11_0_suspend(void *handle) 1211 { 1212 int r; 1213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214 1215 r = amdgpu_mes_suspend(adev); 1216 if (r) 1217 return r; 1218 1219 return mes_v11_0_hw_fini(adev); 1220 } 1221 1222 static int mes_v11_0_resume(void *handle) 1223 { 1224 int r; 1225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1226 1227 r = mes_v11_0_hw_init(adev); 1228 if (r) 1229 return r; 1230 1231 return amdgpu_mes_resume(adev); 1232 } 1233 1234 static int mes_v11_0_late_init(void *handle) 1235 { 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 1238 amdgpu_mes_self_test(adev); 1239 1240 return 0; 1241 } 1242 1243 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1244 .name = "mes_v11_0", 1245 .late_init = mes_v11_0_late_init, 1246 .sw_init = mes_v11_0_sw_init, 1247 .sw_fini = mes_v11_0_sw_fini, 1248 .hw_init = mes_v11_0_hw_init, 1249 .hw_fini = mes_v11_0_hw_fini, 1250 .suspend = mes_v11_0_suspend, 1251 .resume = mes_v11_0_resume, 1252 }; 1253 1254 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1255 .type = AMD_IP_BLOCK_TYPE_MES, 1256 .major = 11, 1257 .minor = 0, 1258 .rev = 0, 1259 .funcs = &mes_v11_0_ip_funcs, 1260 }; 1261