1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 42 static int mes_v11_0_hw_fini(void *handle); 43 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 44 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 45 46 #define MES_EOP_SIZE 2048 47 48 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 49 { 50 struct amdgpu_device *adev = ring->adev; 51 52 if (ring->use_doorbell) { 53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 54 ring->wptr); 55 WDOORBELL64(ring->doorbell_index, ring->wptr); 56 } else { 57 BUG(); 58 } 59 } 60 61 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 return *ring->rptr_cpu_addr; 64 } 65 66 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 67 { 68 u64 wptr; 69 70 if (ring->use_doorbell) 71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 72 else 73 BUG(); 74 return wptr; 75 } 76 77 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 78 .type = AMDGPU_RING_TYPE_MES, 79 .align_mask = 1, 80 .nop = 0, 81 .support_64bit_ptrs = true, 82 .get_rptr = mes_v11_0_ring_get_rptr, 83 .get_wptr = mes_v11_0_ring_get_wptr, 84 .set_wptr = mes_v11_0_ring_set_wptr, 85 .insert_nop = amdgpu_ring_insert_nop, 86 }; 87 88 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 89 void *pkt, int size, 90 int api_status_off) 91 { 92 int ndw = size / 4; 93 signed long r; 94 union MESAPI__ADD_QUEUE *x_pkt = pkt; 95 struct MES_API_STATUS *api_status; 96 struct amdgpu_device *adev = mes->adev; 97 struct amdgpu_ring *ring = &mes->ring; 98 unsigned long flags; 99 100 BUG_ON(size % 4 != 0); 101 102 spin_lock_irqsave(&mes->ring_lock, flags); 103 if (amdgpu_ring_alloc(ring, ndw)) { 104 spin_unlock_irqrestore(&mes->ring_lock, flags); 105 return -ENOMEM; 106 } 107 108 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 109 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 110 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 111 112 amdgpu_ring_write_multiple(ring, pkt, ndw); 113 amdgpu_ring_commit(ring); 114 spin_unlock_irqrestore(&mes->ring_lock, flags); 115 116 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 117 118 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 119 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 120 if (r < 1) { 121 DRM_ERROR("MES failed to response msg=%d\n", 122 x_pkt->header.opcode); 123 return -ETIMEDOUT; 124 } 125 126 return 0; 127 } 128 129 static int convert_to_mes_queue_type(int queue_type) 130 { 131 if (queue_type == AMDGPU_RING_TYPE_GFX) 132 return MES_QUEUE_TYPE_GFX; 133 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 134 return MES_QUEUE_TYPE_COMPUTE; 135 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 136 return MES_QUEUE_TYPE_SDMA; 137 else 138 BUG(); 139 return -1; 140 } 141 142 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 143 struct mes_add_queue_input *input) 144 { 145 struct amdgpu_device *adev = mes->adev; 146 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 147 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 148 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 149 150 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 151 152 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 153 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 154 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 155 156 mes_add_queue_pkt.process_id = input->process_id; 157 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 158 mes_add_queue_pkt.process_va_start = input->process_va_start; 159 mes_add_queue_pkt.process_va_end = input->process_va_end; 160 mes_add_queue_pkt.process_quantum = input->process_quantum; 161 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 162 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 163 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 164 mes_add_queue_pkt.inprocess_gang_priority = 165 input->inprocess_gang_priority; 166 mes_add_queue_pkt.gang_global_priority_level = 167 input->gang_global_priority_level; 168 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 169 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 170 171 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 172 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 173 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 174 else 175 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 176 177 mes_add_queue_pkt.queue_type = 178 convert_to_mes_queue_type(input->queue_type); 179 mes_add_queue_pkt.paging = input->paging; 180 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 181 mes_add_queue_pkt.gws_base = input->gws_base; 182 mes_add_queue_pkt.gws_size = input->gws_size; 183 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 184 mes_add_queue_pkt.tma_addr = input->tma_addr; 185 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 186 mes_add_queue_pkt.trap_en = 1; 187 188 return mes_v11_0_submit_pkt_and_poll_completion(mes, 189 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 190 offsetof(union MESAPI__ADD_QUEUE, api_status)); 191 } 192 193 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 194 struct mes_remove_queue_input *input) 195 { 196 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 197 198 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 199 200 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 201 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 202 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 203 204 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 205 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 206 207 return mes_v11_0_submit_pkt_and_poll_completion(mes, 208 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 209 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 210 } 211 212 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 213 struct mes_unmap_legacy_queue_input *input) 214 { 215 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 216 217 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 218 219 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 220 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 221 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 222 223 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 224 mes_remove_queue_pkt.gang_context_addr = 0; 225 226 mes_remove_queue_pkt.pipe_id = input->pipe_id; 227 mes_remove_queue_pkt.queue_id = input->queue_id; 228 229 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 230 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 231 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 232 mes_remove_queue_pkt.tf_data = 233 lower_32_bits(input->trail_fence_data); 234 } else { 235 mes_remove_queue_pkt.unmap_legacy_queue = 1; 236 mes_remove_queue_pkt.queue_type = 237 convert_to_mes_queue_type(input->queue_type); 238 } 239 240 return mes_v11_0_submit_pkt_and_poll_completion(mes, 241 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 242 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 243 } 244 245 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 246 struct mes_suspend_gang_input *input) 247 { 248 return 0; 249 } 250 251 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 252 struct mes_resume_gang_input *input) 253 { 254 return 0; 255 } 256 257 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 258 { 259 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 260 261 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 262 263 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 264 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 265 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 266 267 return mes_v11_0_submit_pkt_and_poll_completion(mes, 268 &mes_status_pkt, sizeof(mes_status_pkt), 269 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 270 } 271 272 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 273 struct mes_misc_op_input *input) 274 { 275 union MESAPI__MISC misc_pkt; 276 277 memset(&misc_pkt, 0, sizeof(misc_pkt)); 278 279 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 280 misc_pkt.header.opcode = MES_SCH_API_MISC; 281 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 282 283 switch (input->op) { 284 case MES_MISC_OP_READ_REG: 285 misc_pkt.opcode = MESAPI_MISC__READ_REG; 286 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 287 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 288 break; 289 case MES_MISC_OP_WRITE_REG: 290 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 291 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 292 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 293 break; 294 case MES_MISC_OP_WRM_REG_WAIT: 295 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 296 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 297 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 298 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 299 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 300 misc_pkt.wait_reg_mem.reg_offset2 = 0; 301 break; 302 case MES_MISC_OP_WRM_REG_WR_WAIT: 303 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 304 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 305 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 306 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 307 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 308 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 309 break; 310 default: 311 DRM_ERROR("unsupported misc op (%d) \n", input->op); 312 return -EINVAL; 313 } 314 315 return mes_v11_0_submit_pkt_and_poll_completion(mes, 316 &misc_pkt, sizeof(misc_pkt), 317 offsetof(union MESAPI__MISC, api_status)); 318 } 319 320 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 321 { 322 int i; 323 struct amdgpu_device *adev = mes->adev; 324 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 325 326 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 327 328 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 329 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 330 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 331 332 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 333 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 334 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 335 mes_set_hw_res_pkt.paging_vmid = 0; 336 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 337 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 338 mes->query_status_fence_gpu_addr; 339 340 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 341 mes_set_hw_res_pkt.compute_hqd_mask[i] = 342 mes->compute_hqd_mask[i]; 343 344 for (i = 0; i < MAX_GFX_PIPES; i++) 345 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 346 347 for (i = 0; i < MAX_SDMA_PIPES; i++) 348 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 349 350 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 351 mes_set_hw_res_pkt.aggregated_doorbells[i] = 352 mes->aggregated_doorbells[i]; 353 354 for (i = 0; i < 5; i++) { 355 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 356 mes_set_hw_res_pkt.mmhub_base[i] = 357 adev->reg_offset[MMHUB_HWIP][0][i]; 358 mes_set_hw_res_pkt.osssys_base[i] = 359 adev->reg_offset[OSSSYS_HWIP][0][i]; 360 } 361 362 mes_set_hw_res_pkt.disable_reset = 1; 363 mes_set_hw_res_pkt.disable_mes_log = 1; 364 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 365 mes_set_hw_res_pkt.oversubscription_timer = 50; 366 367 return mes_v11_0_submit_pkt_and_poll_completion(mes, 368 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 369 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 370 } 371 372 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 373 { 374 struct amdgpu_device *adev = mes->adev; 375 uint32_t data; 376 377 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 378 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 379 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 380 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 381 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 382 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 383 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 384 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 385 386 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 387 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 388 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 389 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 390 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 391 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 392 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 393 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 394 395 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 396 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 397 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 398 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 399 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 400 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 401 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 402 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 403 404 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 405 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 406 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 407 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 408 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 409 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 410 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 411 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 412 413 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 414 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 415 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 416 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 417 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 418 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 419 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 420 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 421 422 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 423 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 424 } 425 426 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 427 .add_hw_queue = mes_v11_0_add_hw_queue, 428 .remove_hw_queue = mes_v11_0_remove_hw_queue, 429 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 430 .suspend_gang = mes_v11_0_suspend_gang, 431 .resume_gang = mes_v11_0_resume_gang, 432 .misc_op = mes_v11_0_misc_op, 433 }; 434 435 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 436 enum admgpu_mes_pipe pipe) 437 { 438 char fw_name[30]; 439 char ucode_prefix[30]; 440 int err; 441 const struct mes_firmware_header_v1_0 *mes_hdr; 442 struct amdgpu_firmware_info *info; 443 444 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 445 446 if (pipe == AMDGPU_MES_SCHED_PIPE) 447 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 448 ucode_prefix); 449 else 450 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 451 ucode_prefix); 452 453 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 454 if (err) 455 return err; 456 457 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 458 if (err) { 459 release_firmware(adev->mes.fw[pipe]); 460 adev->mes.fw[pipe] = NULL; 461 return err; 462 } 463 464 mes_hdr = (const struct mes_firmware_header_v1_0 *) 465 adev->mes.fw[pipe]->data; 466 adev->mes.ucode_fw_version[pipe] = 467 le32_to_cpu(mes_hdr->mes_ucode_version); 468 adev->mes.ucode_fw_version[pipe] = 469 le32_to_cpu(mes_hdr->mes_ucode_data_version); 470 adev->mes.uc_start_addr[pipe] = 471 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 472 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 473 adev->mes.data_start_addr[pipe] = 474 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 475 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 476 477 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 478 int ucode, ucode_data; 479 480 if (pipe == AMDGPU_MES_SCHED_PIPE) { 481 ucode = AMDGPU_UCODE_ID_CP_MES; 482 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 483 } else { 484 ucode = AMDGPU_UCODE_ID_CP_MES1; 485 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 486 } 487 488 info = &adev->firmware.ucode[ucode]; 489 info->ucode_id = ucode; 490 info->fw = adev->mes.fw[pipe]; 491 adev->firmware.fw_size += 492 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 493 PAGE_SIZE); 494 495 info = &adev->firmware.ucode[ucode_data]; 496 info->ucode_id = ucode_data; 497 info->fw = adev->mes.fw[pipe]; 498 adev->firmware.fw_size += 499 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 500 PAGE_SIZE); 501 } 502 503 return 0; 504 } 505 506 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 507 enum admgpu_mes_pipe pipe) 508 { 509 release_firmware(adev->mes.fw[pipe]); 510 adev->mes.fw[pipe] = NULL; 511 } 512 513 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 514 enum admgpu_mes_pipe pipe) 515 { 516 int r; 517 const struct mes_firmware_header_v1_0 *mes_hdr; 518 const __le32 *fw_data; 519 unsigned fw_size; 520 521 mes_hdr = (const struct mes_firmware_header_v1_0 *) 522 adev->mes.fw[pipe]->data; 523 524 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 525 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 526 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 527 528 r = amdgpu_bo_create_reserved(adev, fw_size, 529 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 530 &adev->mes.ucode_fw_obj[pipe], 531 &adev->mes.ucode_fw_gpu_addr[pipe], 532 (void **)&adev->mes.ucode_fw_ptr[pipe]); 533 if (r) { 534 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 535 return r; 536 } 537 538 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 539 540 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 541 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 542 543 return 0; 544 } 545 546 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 547 enum admgpu_mes_pipe pipe) 548 { 549 int r; 550 const struct mes_firmware_header_v1_0 *mes_hdr; 551 const __le32 *fw_data; 552 unsigned fw_size; 553 554 mes_hdr = (const struct mes_firmware_header_v1_0 *) 555 adev->mes.fw[pipe]->data; 556 557 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 558 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 559 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 560 561 r = amdgpu_bo_create_reserved(adev, fw_size, 562 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 563 &adev->mes.data_fw_obj[pipe], 564 &adev->mes.data_fw_gpu_addr[pipe], 565 (void **)&adev->mes.data_fw_ptr[pipe]); 566 if (r) { 567 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 568 return r; 569 } 570 571 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 572 573 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 574 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 575 576 return 0; 577 } 578 579 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 580 enum admgpu_mes_pipe pipe) 581 { 582 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 583 &adev->mes.data_fw_gpu_addr[pipe], 584 (void **)&adev->mes.data_fw_ptr[pipe]); 585 586 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 587 &adev->mes.ucode_fw_gpu_addr[pipe], 588 (void **)&adev->mes.ucode_fw_ptr[pipe]); 589 } 590 591 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 592 { 593 uint64_t ucode_addr; 594 uint32_t pipe, data = 0; 595 596 if (enable) { 597 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 598 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 599 data = REG_SET_FIELD(data, CP_MES_CNTL, 600 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 601 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 602 603 mutex_lock(&adev->srbm_mutex); 604 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 605 if (!adev->enable_mes_kiq && 606 pipe == AMDGPU_MES_KIQ_PIPE) 607 continue; 608 609 soc21_grbm_select(adev, 3, pipe, 0, 0); 610 611 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 612 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 613 lower_32_bits(ucode_addr)); 614 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 615 upper_32_bits(ucode_addr)); 616 } 617 soc21_grbm_select(adev, 0, 0, 0, 0); 618 mutex_unlock(&adev->srbm_mutex); 619 620 /* unhalt MES and activate pipe0 */ 621 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 622 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 623 adev->enable_mes_kiq ? 1 : 0); 624 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 625 626 if (amdgpu_emu_mode) 627 msleep(100); 628 else 629 udelay(50); 630 } else { 631 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 632 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 633 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 634 data = REG_SET_FIELD(data, CP_MES_CNTL, 635 MES_INVALIDATE_ICACHE, 1); 636 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 637 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 638 adev->enable_mes_kiq ? 1 : 0); 639 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 640 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 641 } 642 } 643 644 /* This function is for backdoor MES firmware */ 645 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 646 enum admgpu_mes_pipe pipe, bool prime_icache) 647 { 648 int r; 649 uint32_t data; 650 uint64_t ucode_addr; 651 652 mes_v11_0_enable(adev, false); 653 654 if (!adev->mes.fw[pipe]) 655 return -EINVAL; 656 657 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 658 if (r) 659 return r; 660 661 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 662 if (r) { 663 mes_v11_0_free_ucode_buffers(adev, pipe); 664 return r; 665 } 666 667 mutex_lock(&adev->srbm_mutex); 668 /* me=3, pipe=0, queue=0 */ 669 soc21_grbm_select(adev, 3, pipe, 0, 0); 670 671 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 672 673 /* set ucode start address */ 674 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 675 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 676 lower_32_bits(ucode_addr)); 677 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 678 upper_32_bits(ucode_addr)); 679 680 /* set ucode fimrware address */ 681 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 682 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 683 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 684 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 685 686 /* set ucode instruction cache boundary to 2M-1 */ 687 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 688 689 /* set ucode data firmware address */ 690 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 691 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 692 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 693 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 694 695 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 696 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 697 698 if (prime_icache) { 699 /* invalidate ICACHE */ 700 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 701 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 702 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 703 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 704 705 /* prime the ICACHE. */ 706 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 707 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 708 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 709 } 710 711 soc21_grbm_select(adev, 0, 0, 0, 0); 712 mutex_unlock(&adev->srbm_mutex); 713 714 return 0; 715 } 716 717 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 718 enum admgpu_mes_pipe pipe) 719 { 720 int r; 721 u32 *eop; 722 723 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 724 AMDGPU_GEM_DOMAIN_GTT, 725 &adev->mes.eop_gpu_obj[pipe], 726 &adev->mes.eop_gpu_addr[pipe], 727 (void **)&eop); 728 if (r) { 729 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 730 return r; 731 } 732 733 memset(eop, 0, 734 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 735 736 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 737 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 738 739 return 0; 740 } 741 742 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 743 { 744 struct v11_compute_mqd *mqd = ring->mqd_ptr; 745 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 746 uint32_t tmp; 747 748 mqd->header = 0xC0310800; 749 mqd->compute_pipelinestat_enable = 0x00000001; 750 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 751 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 752 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 753 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 754 mqd->compute_misc_reserved = 0x00000007; 755 756 eop_base_addr = ring->eop_gpu_addr >> 8; 757 758 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 759 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 760 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 761 (order_base_2(MES_EOP_SIZE / 4) - 1)); 762 763 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 764 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 765 mqd->cp_hqd_eop_control = tmp; 766 767 /* disable the queue if it's active */ 768 ring->wptr = 0; 769 mqd->cp_hqd_pq_rptr = 0; 770 mqd->cp_hqd_pq_wptr_lo = 0; 771 mqd->cp_hqd_pq_wptr_hi = 0; 772 773 /* set the pointer to the MQD */ 774 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 775 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 776 777 /* set MQD vmid to 0 */ 778 tmp = regCP_MQD_CONTROL_DEFAULT; 779 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 780 mqd->cp_mqd_control = tmp; 781 782 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 783 hqd_gpu_addr = ring->gpu_addr >> 8; 784 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 785 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 786 787 /* set the wb address whether it's enabled or not */ 788 wb_gpu_addr = ring->rptr_gpu_addr; 789 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 790 mqd->cp_hqd_pq_rptr_report_addr_hi = 791 upper_32_bits(wb_gpu_addr) & 0xffff; 792 793 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 794 wb_gpu_addr = ring->wptr_gpu_addr; 795 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 796 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 797 798 /* set up the HQD, this is similar to CP_RB0_CNTL */ 799 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 800 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 801 (order_base_2(ring->ring_size / 4) - 1)); 802 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 803 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 805 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 806 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 807 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 808 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 809 mqd->cp_hqd_pq_control = tmp; 810 811 /* enable doorbell */ 812 tmp = 0; 813 if (ring->use_doorbell) { 814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 815 DOORBELL_OFFSET, ring->doorbell_index); 816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 817 DOORBELL_EN, 1); 818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 819 DOORBELL_SOURCE, 0); 820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 821 DOORBELL_HIT, 0); 822 } 823 else 824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 825 DOORBELL_EN, 0); 826 mqd->cp_hqd_pq_doorbell_control = tmp; 827 828 mqd->cp_hqd_vmid = 0; 829 /* activate the queue */ 830 mqd->cp_hqd_active = 1; 831 832 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 833 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 834 PRELOAD_SIZE, 0x55); 835 mqd->cp_hqd_persistent_state = tmp; 836 837 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 838 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 839 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 840 841 return 0; 842 } 843 844 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 845 { 846 struct v11_compute_mqd *mqd = ring->mqd_ptr; 847 struct amdgpu_device *adev = ring->adev; 848 uint32_t data = 0; 849 850 mutex_lock(&adev->srbm_mutex); 851 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 852 853 /* set CP_HQD_VMID.VMID = 0. */ 854 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 855 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 856 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 857 858 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 859 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 860 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 861 DOORBELL_EN, 0); 862 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 863 864 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 865 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 866 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 867 868 /* set CP_MQD_CONTROL.VMID=0 */ 869 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 870 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 871 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 872 873 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 874 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 875 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 876 877 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 878 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 879 mqd->cp_hqd_pq_rptr_report_addr_lo); 880 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 881 mqd->cp_hqd_pq_rptr_report_addr_hi); 882 883 /* set CP_HQD_PQ_CONTROL */ 884 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 885 886 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 887 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 888 mqd->cp_hqd_pq_wptr_poll_addr_lo); 889 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 890 mqd->cp_hqd_pq_wptr_poll_addr_hi); 891 892 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 893 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 894 mqd->cp_hqd_pq_doorbell_control); 895 896 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 897 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 898 899 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 900 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 901 902 soc21_grbm_select(adev, 0, 0, 0, 0); 903 mutex_unlock(&adev->srbm_mutex); 904 } 905 906 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 907 { 908 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 909 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 910 int r; 911 912 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 913 return -EINVAL; 914 915 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 916 if (r) { 917 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 918 return r; 919 } 920 921 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 922 923 r = amdgpu_ring_test_ring(kiq_ring); 924 if (r) { 925 DRM_ERROR("kfq enable failed\n"); 926 kiq_ring->sched.ready = false; 927 } 928 return r; 929 } 930 931 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 932 enum admgpu_mes_pipe pipe) 933 { 934 struct amdgpu_ring *ring; 935 int r; 936 937 if (pipe == AMDGPU_MES_KIQ_PIPE) 938 ring = &adev->gfx.kiq.ring; 939 else if (pipe == AMDGPU_MES_SCHED_PIPE) 940 ring = &adev->mes.ring; 941 else 942 BUG(); 943 944 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 945 (amdgpu_in_reset(adev) || adev->in_suspend)) { 946 *(ring->wptr_cpu_addr) = 0; 947 *(ring->rptr_cpu_addr) = 0; 948 amdgpu_ring_clear_ring(ring); 949 } 950 951 r = mes_v11_0_mqd_init(ring); 952 if (r) 953 return r; 954 955 if (pipe == AMDGPU_MES_SCHED_PIPE) { 956 r = mes_v11_0_kiq_enable_queue(adev); 957 if (r) 958 return r; 959 } else { 960 mes_v11_0_queue_init_register(ring); 961 } 962 963 /* get MES scheduler/KIQ versions */ 964 mutex_lock(&adev->srbm_mutex); 965 soc21_grbm_select(adev, 3, pipe, 0, 0); 966 967 if (pipe == AMDGPU_MES_SCHED_PIPE) 968 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 969 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 970 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 971 972 soc21_grbm_select(adev, 0, 0, 0, 0); 973 mutex_unlock(&adev->srbm_mutex); 974 975 return 0; 976 } 977 978 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 979 { 980 struct amdgpu_ring *ring; 981 982 ring = &adev->mes.ring; 983 984 ring->funcs = &mes_v11_0_ring_funcs; 985 986 ring->me = 3; 987 ring->pipe = 0; 988 ring->queue = 0; 989 990 ring->ring_obj = NULL; 991 ring->use_doorbell = true; 992 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 993 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 994 ring->no_scheduler = true; 995 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 996 997 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 998 AMDGPU_RING_PRIO_DEFAULT, NULL); 999 } 1000 1001 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1002 { 1003 struct amdgpu_ring *ring; 1004 1005 spin_lock_init(&adev->gfx.kiq.ring_lock); 1006 1007 ring = &adev->gfx.kiq.ring; 1008 1009 ring->me = 3; 1010 ring->pipe = 1; 1011 ring->queue = 0; 1012 1013 ring->adev = NULL; 1014 ring->ring_obj = NULL; 1015 ring->use_doorbell = true; 1016 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1017 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1018 ring->no_scheduler = true; 1019 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1020 ring->me, ring->pipe, ring->queue); 1021 1022 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1023 AMDGPU_RING_PRIO_DEFAULT, NULL); 1024 } 1025 1026 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1027 enum admgpu_mes_pipe pipe) 1028 { 1029 int r, mqd_size = sizeof(struct v11_compute_mqd); 1030 struct amdgpu_ring *ring; 1031 1032 if (pipe == AMDGPU_MES_KIQ_PIPE) 1033 ring = &adev->gfx.kiq.ring; 1034 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1035 ring = &adev->mes.ring; 1036 else 1037 BUG(); 1038 1039 if (ring->mqd_obj) 1040 return 0; 1041 1042 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1043 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1044 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1045 if (r) { 1046 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1047 return r; 1048 } 1049 1050 memset(ring->mqd_ptr, 0, mqd_size); 1051 1052 /* prepare MQD backup */ 1053 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1054 if (!adev->mes.mqd_backup[pipe]) 1055 dev_warn(adev->dev, 1056 "no memory to create MQD backup for ring %s\n", 1057 ring->name); 1058 1059 return 0; 1060 } 1061 1062 static int mes_v11_0_sw_init(void *handle) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 int pipe, r; 1066 1067 adev->mes.adev = adev; 1068 adev->mes.funcs = &mes_v11_0_funcs; 1069 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1070 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1071 1072 r = amdgpu_mes_init(adev); 1073 if (r) 1074 return r; 1075 1076 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1077 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1078 continue; 1079 1080 r = mes_v11_0_init_microcode(adev, pipe); 1081 if (r) 1082 return r; 1083 1084 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1085 if (r) 1086 return r; 1087 1088 r = mes_v11_0_mqd_sw_init(adev, pipe); 1089 if (r) 1090 return r; 1091 } 1092 1093 if (adev->enable_mes_kiq) { 1094 r = mes_v11_0_kiq_ring_init(adev); 1095 if (r) 1096 return r; 1097 } 1098 1099 r = mes_v11_0_ring_init(adev); 1100 if (r) 1101 return r; 1102 1103 return 0; 1104 } 1105 1106 static int mes_v11_0_sw_fini(void *handle) 1107 { 1108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1109 int pipe; 1110 1111 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1112 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1113 1114 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1115 kfree(adev->mes.mqd_backup[pipe]); 1116 1117 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1118 &adev->mes.eop_gpu_addr[pipe], 1119 NULL); 1120 1121 mes_v11_0_free_microcode(adev, pipe); 1122 } 1123 1124 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1125 &adev->gfx.kiq.ring.mqd_gpu_addr, 1126 &adev->gfx.kiq.ring.mqd_ptr); 1127 1128 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1129 &adev->mes.ring.mqd_gpu_addr, 1130 &adev->mes.ring.mqd_ptr); 1131 1132 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1133 amdgpu_ring_fini(&adev->mes.ring); 1134 1135 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1136 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1137 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1138 } 1139 1140 amdgpu_mes_fini(adev); 1141 return 0; 1142 } 1143 1144 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1145 { 1146 uint32_t tmp; 1147 struct amdgpu_device *adev = ring->adev; 1148 1149 /* tell RLC which is KIQ queue */ 1150 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1151 tmp &= 0xffffff00; 1152 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1153 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1154 tmp |= 0x80; 1155 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1156 } 1157 1158 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1159 { 1160 int r = 0; 1161 1162 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1163 1164 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1165 if (r) { 1166 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1167 return r; 1168 } 1169 1170 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1171 if (r) { 1172 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1173 return r; 1174 } 1175 1176 } 1177 1178 mes_v11_0_enable(adev, true); 1179 1180 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1181 1182 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1183 if (r) 1184 goto failure; 1185 1186 return r; 1187 1188 failure: 1189 mes_v11_0_hw_fini(adev); 1190 return r; 1191 } 1192 1193 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1194 { 1195 mes_v11_0_enable(adev, false); 1196 return 0; 1197 } 1198 1199 static int mes_v11_0_hw_init(void *handle) 1200 { 1201 int r; 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 1204 if (!adev->enable_mes_kiq) { 1205 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1206 r = mes_v11_0_load_microcode(adev, 1207 AMDGPU_MES_SCHED_PIPE, true); 1208 if (r) { 1209 DRM_ERROR("failed to MES fw, r=%d\n", r); 1210 return r; 1211 } 1212 } 1213 1214 mes_v11_0_enable(adev, true); 1215 } 1216 1217 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1218 if (r) 1219 goto failure; 1220 1221 r = mes_v11_0_set_hw_resources(&adev->mes); 1222 if (r) 1223 goto failure; 1224 1225 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1226 1227 r = mes_v11_0_query_sched_status(&adev->mes); 1228 if (r) { 1229 DRM_ERROR("MES is busy\n"); 1230 goto failure; 1231 } 1232 1233 /* 1234 * Disable KIQ ring usage from the driver once MES is enabled. 1235 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1236 * with MES enabled. 1237 */ 1238 adev->gfx.kiq.ring.sched.ready = false; 1239 adev->mes.ring.sched.ready = true; 1240 1241 return 0; 1242 1243 failure: 1244 mes_v11_0_hw_fini(adev); 1245 return r; 1246 } 1247 1248 static int mes_v11_0_hw_fini(void *handle) 1249 { 1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1251 1252 adev->mes.ring.sched.ready = false; 1253 return 0; 1254 } 1255 1256 static int mes_v11_0_suspend(void *handle) 1257 { 1258 int r; 1259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1260 1261 r = amdgpu_mes_suspend(adev); 1262 if (r) 1263 return r; 1264 1265 return mes_v11_0_hw_fini(adev); 1266 } 1267 1268 static int mes_v11_0_resume(void *handle) 1269 { 1270 int r; 1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1272 1273 r = mes_v11_0_hw_init(adev); 1274 if (r) 1275 return r; 1276 1277 return amdgpu_mes_resume(adev); 1278 } 1279 1280 static int mes_v11_0_late_init(void *handle) 1281 { 1282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1283 1284 if (!amdgpu_in_reset(adev)) 1285 amdgpu_mes_self_test(adev); 1286 1287 return 0; 1288 } 1289 1290 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1291 .name = "mes_v11_0", 1292 .late_init = mes_v11_0_late_init, 1293 .sw_init = mes_v11_0_sw_init, 1294 .sw_fini = mes_v11_0_sw_fini, 1295 .hw_init = mes_v11_0_hw_init, 1296 .hw_fini = mes_v11_0_hw_fini, 1297 .suspend = mes_v11_0_suspend, 1298 .resume = mes_v11_0_resume, 1299 }; 1300 1301 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1302 .type = AMD_IP_BLOCK_TYPE_MES, 1303 .major = 11, 1304 .minor = 0, 1305 .rev = 0, 1306 .funcs = &mes_v11_0_ip_funcs, 1307 }; 1308