1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 51 static int mes_v11_0_hw_fini(void *handle); 52 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 53 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 54 55 #define MES_EOP_SIZE 2048 56 57 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 58 { 59 struct amdgpu_device *adev = ring->adev; 60 61 if (ring->use_doorbell) { 62 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 63 ring->wptr); 64 WDOORBELL64(ring->doorbell_index, ring->wptr); 65 } else { 66 BUG(); 67 } 68 } 69 70 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 71 { 72 return *ring->rptr_cpu_addr; 73 } 74 75 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 76 { 77 u64 wptr; 78 79 if (ring->use_doorbell) 80 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 81 else 82 BUG(); 83 return wptr; 84 } 85 86 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 87 .type = AMDGPU_RING_TYPE_MES, 88 .align_mask = 1, 89 .nop = 0, 90 .support_64bit_ptrs = true, 91 .get_rptr = mes_v11_0_ring_get_rptr, 92 .get_wptr = mes_v11_0_ring_get_wptr, 93 .set_wptr = mes_v11_0_ring_set_wptr, 94 .insert_nop = amdgpu_ring_insert_nop, 95 }; 96 97 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 98 void *pkt, int size, 99 int api_status_off) 100 { 101 int ndw = size / 4; 102 signed long r; 103 union MESAPI__ADD_QUEUE *x_pkt = pkt; 104 struct MES_API_STATUS *api_status; 105 struct amdgpu_device *adev = mes->adev; 106 struct amdgpu_ring *ring = &mes->ring; 107 unsigned long flags; 108 signed long timeout = adev->usec_timeout; 109 110 if (amdgpu_emu_mode) { 111 timeout *= 100; 112 } else if (amdgpu_sriov_vf(adev)) { 113 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 114 timeout = 15 * 600 * 1000; 115 } 116 BUG_ON(size % 4 != 0); 117 118 spin_lock_irqsave(&mes->ring_lock, flags); 119 if (amdgpu_ring_alloc(ring, ndw)) { 120 spin_unlock_irqrestore(&mes->ring_lock, flags); 121 return -ENOMEM; 122 } 123 124 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 125 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 126 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 127 128 amdgpu_ring_write_multiple(ring, pkt, ndw); 129 amdgpu_ring_commit(ring); 130 spin_unlock_irqrestore(&mes->ring_lock, flags); 131 132 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 133 134 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 135 timeout); 136 if (r < 1) { 137 DRM_ERROR("MES failed to response msg=%d\n", 138 x_pkt->header.opcode); 139 140 while (halt_if_hws_hang) 141 schedule(); 142 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int convert_to_mes_queue_type(int queue_type) 150 { 151 if (queue_type == AMDGPU_RING_TYPE_GFX) 152 return MES_QUEUE_TYPE_GFX; 153 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 154 return MES_QUEUE_TYPE_COMPUTE; 155 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 156 return MES_QUEUE_TYPE_SDMA; 157 else 158 BUG(); 159 return -1; 160 } 161 162 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 163 struct mes_add_queue_input *input) 164 { 165 struct amdgpu_device *adev = mes->adev; 166 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 167 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 168 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 169 170 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 171 172 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 173 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 174 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 175 176 mes_add_queue_pkt.process_id = input->process_id; 177 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 178 mes_add_queue_pkt.process_va_start = input->process_va_start; 179 mes_add_queue_pkt.process_va_end = input->process_va_end; 180 mes_add_queue_pkt.process_quantum = input->process_quantum; 181 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 182 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 183 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 184 mes_add_queue_pkt.inprocess_gang_priority = 185 input->inprocess_gang_priority; 186 mes_add_queue_pkt.gang_global_priority_level = 187 input->gang_global_priority_level; 188 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 189 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 190 191 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 192 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 193 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 194 else 195 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 196 197 mes_add_queue_pkt.queue_type = 198 convert_to_mes_queue_type(input->queue_type); 199 mes_add_queue_pkt.paging = input->paging; 200 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 201 mes_add_queue_pkt.gws_base = input->gws_base; 202 mes_add_queue_pkt.gws_size = input->gws_size; 203 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 204 mes_add_queue_pkt.tma_addr = input->tma_addr; 205 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 206 207 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 208 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 209 mes_add_queue_pkt.gds_size = input->queue_size; 210 211 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 212 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 213 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 214 mes_add_queue_pkt.trap_en = 1; 215 216 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 217 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 218 mes_add_queue_pkt.gds_size = input->queue_size; 219 220 return mes_v11_0_submit_pkt_and_poll_completion(mes, 221 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 222 offsetof(union MESAPI__ADD_QUEUE, api_status)); 223 } 224 225 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 226 struct mes_remove_queue_input *input) 227 { 228 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 229 230 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 231 232 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 233 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 234 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 235 236 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 237 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 238 239 return mes_v11_0_submit_pkt_and_poll_completion(mes, 240 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 241 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 242 } 243 244 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 245 struct mes_unmap_legacy_queue_input *input) 246 { 247 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 248 249 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 250 251 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 252 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 253 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 254 255 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 256 mes_remove_queue_pkt.gang_context_addr = 0; 257 258 mes_remove_queue_pkt.pipe_id = input->pipe_id; 259 mes_remove_queue_pkt.queue_id = input->queue_id; 260 261 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 262 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 263 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 264 mes_remove_queue_pkt.tf_data = 265 lower_32_bits(input->trail_fence_data); 266 } else { 267 mes_remove_queue_pkt.unmap_legacy_queue = 1; 268 mes_remove_queue_pkt.queue_type = 269 convert_to_mes_queue_type(input->queue_type); 270 } 271 272 return mes_v11_0_submit_pkt_and_poll_completion(mes, 273 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 274 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 275 } 276 277 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 278 struct mes_suspend_gang_input *input) 279 { 280 return 0; 281 } 282 283 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 284 struct mes_resume_gang_input *input) 285 { 286 return 0; 287 } 288 289 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 290 { 291 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 292 293 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 294 295 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 296 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 297 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 298 299 return mes_v11_0_submit_pkt_and_poll_completion(mes, 300 &mes_status_pkt, sizeof(mes_status_pkt), 301 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 302 } 303 304 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 305 struct mes_misc_op_input *input) 306 { 307 union MESAPI__MISC misc_pkt; 308 309 memset(&misc_pkt, 0, sizeof(misc_pkt)); 310 311 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 312 misc_pkt.header.opcode = MES_SCH_API_MISC; 313 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 314 315 switch (input->op) { 316 case MES_MISC_OP_READ_REG: 317 misc_pkt.opcode = MESAPI_MISC__READ_REG; 318 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 319 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 320 break; 321 case MES_MISC_OP_WRITE_REG: 322 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 323 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 324 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 325 break; 326 case MES_MISC_OP_WRM_REG_WAIT: 327 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 328 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 329 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 330 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 331 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 332 misc_pkt.wait_reg_mem.reg_offset2 = 0; 333 break; 334 case MES_MISC_OP_WRM_REG_WR_WAIT: 335 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 336 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 337 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 338 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 339 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 340 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 341 break; 342 default: 343 DRM_ERROR("unsupported misc op (%d) \n", input->op); 344 return -EINVAL; 345 } 346 347 return mes_v11_0_submit_pkt_and_poll_completion(mes, 348 &misc_pkt, sizeof(misc_pkt), 349 offsetof(union MESAPI__MISC, api_status)); 350 } 351 352 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 353 { 354 int i; 355 struct amdgpu_device *adev = mes->adev; 356 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 357 358 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 359 360 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 361 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 362 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 363 364 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 365 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 366 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 367 mes_set_hw_res_pkt.paging_vmid = 0; 368 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 369 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 370 mes->query_status_fence_gpu_addr; 371 372 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 373 mes_set_hw_res_pkt.compute_hqd_mask[i] = 374 mes->compute_hqd_mask[i]; 375 376 for (i = 0; i < MAX_GFX_PIPES; i++) 377 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 378 379 for (i = 0; i < MAX_SDMA_PIPES; i++) 380 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 381 382 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 383 mes_set_hw_res_pkt.aggregated_doorbells[i] = 384 mes->aggregated_doorbells[i]; 385 386 for (i = 0; i < 5; i++) { 387 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 388 mes_set_hw_res_pkt.mmhub_base[i] = 389 adev->reg_offset[MMHUB_HWIP][0][i]; 390 mes_set_hw_res_pkt.osssys_base[i] = 391 adev->reg_offset[OSSSYS_HWIP][0][i]; 392 } 393 394 mes_set_hw_res_pkt.disable_reset = 1; 395 mes_set_hw_res_pkt.disable_mes_log = 1; 396 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 397 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 398 mes_set_hw_res_pkt.oversubscription_timer = 50; 399 400 return mes_v11_0_submit_pkt_and_poll_completion(mes, 401 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 402 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 403 } 404 405 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 406 { 407 struct amdgpu_device *adev = mes->adev; 408 uint32_t data; 409 410 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 411 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 412 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 413 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 414 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 415 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 416 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 417 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 418 419 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 420 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 421 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 422 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 423 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 424 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 425 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 426 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 427 428 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 429 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 430 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 431 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 432 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 433 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 434 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 435 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 436 437 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 438 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 439 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 440 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 441 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 442 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 443 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 444 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 445 446 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 447 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 448 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 449 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 450 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 451 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 452 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 453 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 454 455 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 456 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 457 } 458 459 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 460 .add_hw_queue = mes_v11_0_add_hw_queue, 461 .remove_hw_queue = mes_v11_0_remove_hw_queue, 462 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 463 .suspend_gang = mes_v11_0_suspend_gang, 464 .resume_gang = mes_v11_0_resume_gang, 465 .misc_op = mes_v11_0_misc_op, 466 }; 467 468 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 469 enum admgpu_mes_pipe pipe) 470 { 471 int r; 472 const struct mes_firmware_header_v1_0 *mes_hdr; 473 const __le32 *fw_data; 474 unsigned fw_size; 475 476 mes_hdr = (const struct mes_firmware_header_v1_0 *) 477 adev->mes.fw[pipe]->data; 478 479 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 480 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 481 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 482 483 r = amdgpu_bo_create_reserved(adev, fw_size, 484 PAGE_SIZE, 485 AMDGPU_GEM_DOMAIN_VRAM | 486 AMDGPU_GEM_DOMAIN_GTT, 487 &adev->mes.ucode_fw_obj[pipe], 488 &adev->mes.ucode_fw_gpu_addr[pipe], 489 (void **)&adev->mes.ucode_fw_ptr[pipe]); 490 if (r) { 491 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 492 return r; 493 } 494 495 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 496 497 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 498 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 499 500 return 0; 501 } 502 503 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 504 enum admgpu_mes_pipe pipe) 505 { 506 int r; 507 const struct mes_firmware_header_v1_0 *mes_hdr; 508 const __le32 *fw_data; 509 unsigned fw_size; 510 511 mes_hdr = (const struct mes_firmware_header_v1_0 *) 512 adev->mes.fw[pipe]->data; 513 514 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 515 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 516 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 517 518 r = amdgpu_bo_create_reserved(adev, fw_size, 519 64 * 1024, 520 AMDGPU_GEM_DOMAIN_VRAM | 521 AMDGPU_GEM_DOMAIN_GTT, 522 &adev->mes.data_fw_obj[pipe], 523 &adev->mes.data_fw_gpu_addr[pipe], 524 (void **)&adev->mes.data_fw_ptr[pipe]); 525 if (r) { 526 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 527 return r; 528 } 529 530 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 531 532 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 533 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 534 535 return 0; 536 } 537 538 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 539 enum admgpu_mes_pipe pipe) 540 { 541 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 542 &adev->mes.data_fw_gpu_addr[pipe], 543 (void **)&adev->mes.data_fw_ptr[pipe]); 544 545 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 546 &adev->mes.ucode_fw_gpu_addr[pipe], 547 (void **)&adev->mes.ucode_fw_ptr[pipe]); 548 } 549 550 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 551 { 552 uint64_t ucode_addr; 553 uint32_t pipe, data = 0; 554 555 if (enable) { 556 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 557 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 558 data = REG_SET_FIELD(data, CP_MES_CNTL, 559 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 560 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 561 562 mutex_lock(&adev->srbm_mutex); 563 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 564 if (!adev->enable_mes_kiq && 565 pipe == AMDGPU_MES_KIQ_PIPE) 566 continue; 567 568 soc21_grbm_select(adev, 3, pipe, 0, 0); 569 570 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 571 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 572 lower_32_bits(ucode_addr)); 573 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 574 upper_32_bits(ucode_addr)); 575 } 576 soc21_grbm_select(adev, 0, 0, 0, 0); 577 mutex_unlock(&adev->srbm_mutex); 578 579 /* unhalt MES and activate pipe0 */ 580 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 581 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 582 adev->enable_mes_kiq ? 1 : 0); 583 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 584 585 if (amdgpu_emu_mode) 586 msleep(100); 587 else 588 udelay(50); 589 } else { 590 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 591 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 592 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 593 data = REG_SET_FIELD(data, CP_MES_CNTL, 594 MES_INVALIDATE_ICACHE, 1); 595 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 596 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 597 adev->enable_mes_kiq ? 1 : 0); 598 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 599 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 600 } 601 } 602 603 /* This function is for backdoor MES firmware */ 604 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 605 enum admgpu_mes_pipe pipe, bool prime_icache) 606 { 607 int r; 608 uint32_t data; 609 uint64_t ucode_addr; 610 611 mes_v11_0_enable(adev, false); 612 613 if (!adev->mes.fw[pipe]) 614 return -EINVAL; 615 616 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 617 if (r) 618 return r; 619 620 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 621 if (r) { 622 mes_v11_0_free_ucode_buffers(adev, pipe); 623 return r; 624 } 625 626 mutex_lock(&adev->srbm_mutex); 627 /* me=3, pipe=0, queue=0 */ 628 soc21_grbm_select(adev, 3, pipe, 0, 0); 629 630 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 631 632 /* set ucode start address */ 633 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 634 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 635 lower_32_bits(ucode_addr)); 636 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 637 upper_32_bits(ucode_addr)); 638 639 /* set ucode fimrware address */ 640 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 641 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 642 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 643 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 644 645 /* set ucode instruction cache boundary to 2M-1 */ 646 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 647 648 /* set ucode data firmware address */ 649 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 650 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 651 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 652 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 653 654 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 655 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 656 657 if (prime_icache) { 658 /* invalidate ICACHE */ 659 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 660 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 661 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 662 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 663 664 /* prime the ICACHE. */ 665 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 666 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 667 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 668 } 669 670 soc21_grbm_select(adev, 0, 0, 0, 0); 671 mutex_unlock(&adev->srbm_mutex); 672 673 return 0; 674 } 675 676 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 677 enum admgpu_mes_pipe pipe) 678 { 679 int r; 680 u32 *eop; 681 682 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 683 AMDGPU_GEM_DOMAIN_GTT, 684 &adev->mes.eop_gpu_obj[pipe], 685 &adev->mes.eop_gpu_addr[pipe], 686 (void **)&eop); 687 if (r) { 688 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 689 return r; 690 } 691 692 memset(eop, 0, 693 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 694 695 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 696 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 697 698 return 0; 699 } 700 701 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 702 { 703 struct v11_compute_mqd *mqd = ring->mqd_ptr; 704 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 705 uint32_t tmp; 706 707 mqd->header = 0xC0310800; 708 mqd->compute_pipelinestat_enable = 0x00000001; 709 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 710 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 711 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 712 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 713 mqd->compute_misc_reserved = 0x00000007; 714 715 eop_base_addr = ring->eop_gpu_addr >> 8; 716 717 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 718 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 719 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 720 (order_base_2(MES_EOP_SIZE / 4) - 1)); 721 722 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 723 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 724 mqd->cp_hqd_eop_control = tmp; 725 726 /* disable the queue if it's active */ 727 ring->wptr = 0; 728 mqd->cp_hqd_pq_rptr = 0; 729 mqd->cp_hqd_pq_wptr_lo = 0; 730 mqd->cp_hqd_pq_wptr_hi = 0; 731 732 /* set the pointer to the MQD */ 733 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 734 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 735 736 /* set MQD vmid to 0 */ 737 tmp = regCP_MQD_CONTROL_DEFAULT; 738 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 739 mqd->cp_mqd_control = tmp; 740 741 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 742 hqd_gpu_addr = ring->gpu_addr >> 8; 743 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 744 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 745 746 /* set the wb address whether it's enabled or not */ 747 wb_gpu_addr = ring->rptr_gpu_addr; 748 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 749 mqd->cp_hqd_pq_rptr_report_addr_hi = 750 upper_32_bits(wb_gpu_addr) & 0xffff; 751 752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 753 wb_gpu_addr = ring->wptr_gpu_addr; 754 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 755 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 756 757 /* set up the HQD, this is similar to CP_RB0_CNTL */ 758 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 760 (order_base_2(ring->ring_size / 4) - 1)); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 762 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 763 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 764 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 765 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 766 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 767 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 768 mqd->cp_hqd_pq_control = tmp; 769 770 /* enable doorbell */ 771 tmp = 0; 772 if (ring->use_doorbell) { 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 774 DOORBELL_OFFSET, ring->doorbell_index); 775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 776 DOORBELL_EN, 1); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 778 DOORBELL_SOURCE, 0); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 780 DOORBELL_HIT, 0); 781 } 782 else 783 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 784 DOORBELL_EN, 0); 785 mqd->cp_hqd_pq_doorbell_control = tmp; 786 787 mqd->cp_hqd_vmid = 0; 788 /* activate the queue */ 789 mqd->cp_hqd_active = 1; 790 791 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 792 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 793 PRELOAD_SIZE, 0x55); 794 mqd->cp_hqd_persistent_state = tmp; 795 796 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 797 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 798 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 799 800 return 0; 801 } 802 803 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 804 { 805 struct v11_compute_mqd *mqd = ring->mqd_ptr; 806 struct amdgpu_device *adev = ring->adev; 807 uint32_t data = 0; 808 809 mutex_lock(&adev->srbm_mutex); 810 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 811 812 /* set CP_HQD_VMID.VMID = 0. */ 813 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 814 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 815 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 816 817 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 818 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 819 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 820 DOORBELL_EN, 0); 821 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 822 823 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 824 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 825 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 826 827 /* set CP_MQD_CONTROL.VMID=0 */ 828 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 829 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 830 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 831 832 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 833 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 835 836 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 837 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 838 mqd->cp_hqd_pq_rptr_report_addr_lo); 839 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 840 mqd->cp_hqd_pq_rptr_report_addr_hi); 841 842 /* set CP_HQD_PQ_CONTROL */ 843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 844 845 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 847 mqd->cp_hqd_pq_wptr_poll_addr_lo); 848 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 849 mqd->cp_hqd_pq_wptr_poll_addr_hi); 850 851 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 853 mqd->cp_hqd_pq_doorbell_control); 854 855 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 856 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 857 858 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 859 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 860 861 soc21_grbm_select(adev, 0, 0, 0, 0); 862 mutex_unlock(&adev->srbm_mutex); 863 } 864 865 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 866 { 867 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 868 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 869 int r; 870 871 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 872 return -EINVAL; 873 874 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 875 if (r) { 876 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 877 return r; 878 } 879 880 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 881 882 r = amdgpu_ring_test_ring(kiq_ring); 883 if (r) { 884 DRM_ERROR("kfq enable failed\n"); 885 kiq_ring->sched.ready = false; 886 } 887 return r; 888 } 889 890 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 891 enum admgpu_mes_pipe pipe) 892 { 893 struct amdgpu_ring *ring; 894 int r; 895 896 if (pipe == AMDGPU_MES_KIQ_PIPE) 897 ring = &adev->gfx.kiq.ring; 898 else if (pipe == AMDGPU_MES_SCHED_PIPE) 899 ring = &adev->mes.ring; 900 else 901 BUG(); 902 903 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 904 (amdgpu_in_reset(adev) || adev->in_suspend)) { 905 *(ring->wptr_cpu_addr) = 0; 906 *(ring->rptr_cpu_addr) = 0; 907 amdgpu_ring_clear_ring(ring); 908 } 909 910 r = mes_v11_0_mqd_init(ring); 911 if (r) 912 return r; 913 914 if (pipe == AMDGPU_MES_SCHED_PIPE) { 915 r = mes_v11_0_kiq_enable_queue(adev); 916 if (r) 917 return r; 918 } else { 919 mes_v11_0_queue_init_register(ring); 920 } 921 922 /* get MES scheduler/KIQ versions */ 923 mutex_lock(&adev->srbm_mutex); 924 soc21_grbm_select(adev, 3, pipe, 0, 0); 925 926 if (pipe == AMDGPU_MES_SCHED_PIPE) 927 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 928 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 929 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 930 931 soc21_grbm_select(adev, 0, 0, 0, 0); 932 mutex_unlock(&adev->srbm_mutex); 933 934 return 0; 935 } 936 937 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 938 { 939 struct amdgpu_ring *ring; 940 941 ring = &adev->mes.ring; 942 943 ring->funcs = &mes_v11_0_ring_funcs; 944 945 ring->me = 3; 946 ring->pipe = 0; 947 ring->queue = 0; 948 949 ring->ring_obj = NULL; 950 ring->use_doorbell = true; 951 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 952 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 953 ring->no_scheduler = true; 954 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 955 956 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 957 AMDGPU_RING_PRIO_DEFAULT, NULL); 958 } 959 960 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 961 { 962 struct amdgpu_ring *ring; 963 964 spin_lock_init(&adev->gfx.kiq.ring_lock); 965 966 ring = &adev->gfx.kiq.ring; 967 968 ring->me = 3; 969 ring->pipe = 1; 970 ring->queue = 0; 971 972 ring->adev = NULL; 973 ring->ring_obj = NULL; 974 ring->use_doorbell = true; 975 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 976 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 977 ring->no_scheduler = true; 978 sprintf(ring->name, "mes_kiq_%d.%d.%d", 979 ring->me, ring->pipe, ring->queue); 980 981 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 } 984 985 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 986 enum admgpu_mes_pipe pipe) 987 { 988 int r, mqd_size = sizeof(struct v11_compute_mqd); 989 struct amdgpu_ring *ring; 990 991 if (pipe == AMDGPU_MES_KIQ_PIPE) 992 ring = &adev->gfx.kiq.ring; 993 else if (pipe == AMDGPU_MES_SCHED_PIPE) 994 ring = &adev->mes.ring; 995 else 996 BUG(); 997 998 if (ring->mqd_obj) 999 return 0; 1000 1001 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1002 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1003 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1004 if (r) { 1005 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1006 return r; 1007 } 1008 1009 memset(ring->mqd_ptr, 0, mqd_size); 1010 1011 /* prepare MQD backup */ 1012 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1013 if (!adev->mes.mqd_backup[pipe]) 1014 dev_warn(adev->dev, 1015 "no memory to create MQD backup for ring %s\n", 1016 ring->name); 1017 1018 return 0; 1019 } 1020 1021 static int mes_v11_0_sw_init(void *handle) 1022 { 1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1024 int pipe, r; 1025 1026 adev->mes.funcs = &mes_v11_0_funcs; 1027 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1028 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1029 1030 r = amdgpu_mes_init(adev); 1031 if (r) 1032 return r; 1033 1034 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1035 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1036 continue; 1037 1038 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1039 if (r) 1040 return r; 1041 1042 r = mes_v11_0_mqd_sw_init(adev, pipe); 1043 if (r) 1044 return r; 1045 } 1046 1047 if (adev->enable_mes_kiq) { 1048 r = mes_v11_0_kiq_ring_init(adev); 1049 if (r) 1050 return r; 1051 } 1052 1053 r = mes_v11_0_ring_init(adev); 1054 if (r) 1055 return r; 1056 1057 return 0; 1058 } 1059 1060 static int mes_v11_0_sw_fini(void *handle) 1061 { 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 int pipe; 1064 1065 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1066 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1067 1068 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1069 kfree(adev->mes.mqd_backup[pipe]); 1070 1071 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1072 &adev->mes.eop_gpu_addr[pipe], 1073 NULL); 1074 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1075 } 1076 1077 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1078 &adev->gfx.kiq.ring.mqd_gpu_addr, 1079 &adev->gfx.kiq.ring.mqd_ptr); 1080 1081 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1082 &adev->mes.ring.mqd_gpu_addr, 1083 &adev->mes.ring.mqd_ptr); 1084 1085 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1086 amdgpu_ring_fini(&adev->mes.ring); 1087 1088 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1089 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1090 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1091 } 1092 1093 amdgpu_mes_fini(adev); 1094 return 0; 1095 } 1096 1097 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1098 { 1099 uint32_t data; 1100 int i; 1101 struct amdgpu_device *adev = ring->adev; 1102 1103 mutex_lock(&adev->srbm_mutex); 1104 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1105 1106 /* disable the queue if it's active */ 1107 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1108 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1109 for (i = 0; i < adev->usec_timeout; i++) { 1110 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1111 break; 1112 udelay(1); 1113 } 1114 } 1115 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1116 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1117 DOORBELL_EN, 0); 1118 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1119 DOORBELL_HIT, 1); 1120 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1121 1122 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1123 1124 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1125 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1126 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1127 1128 soc21_grbm_select(adev, 0, 0, 0, 0); 1129 mutex_unlock(&adev->srbm_mutex); 1130 } 1131 1132 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1133 { 1134 uint32_t tmp; 1135 struct amdgpu_device *adev = ring->adev; 1136 1137 /* tell RLC which is KIQ queue */ 1138 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1139 tmp &= 0xffffff00; 1140 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1141 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1142 tmp |= 0x80; 1143 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1144 } 1145 1146 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1147 { 1148 uint32_t tmp; 1149 1150 /* tell RLC which is KIQ dequeue */ 1151 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1152 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1153 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1154 } 1155 1156 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1157 { 1158 int r = 0; 1159 1160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1161 1162 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1163 if (r) { 1164 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1165 return r; 1166 } 1167 1168 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1169 if (r) { 1170 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1171 return r; 1172 } 1173 1174 } 1175 1176 mes_v11_0_enable(adev, true); 1177 1178 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1179 1180 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1181 if (r) 1182 goto failure; 1183 1184 return r; 1185 1186 failure: 1187 mes_v11_0_hw_fini(adev); 1188 return r; 1189 } 1190 1191 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1192 { 1193 if (adev->mes.ring.sched.ready) { 1194 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1195 adev->mes.ring.sched.ready = false; 1196 } 1197 1198 if (amdgpu_sriov_vf(adev)) { 1199 mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring); 1200 mes_v11_0_kiq_clear(adev); 1201 } 1202 1203 mes_v11_0_enable(adev, false); 1204 1205 return 0; 1206 } 1207 1208 static int mes_v11_0_hw_init(void *handle) 1209 { 1210 int r; 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 1213 if (!adev->enable_mes_kiq) { 1214 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1215 r = mes_v11_0_load_microcode(adev, 1216 AMDGPU_MES_SCHED_PIPE, true); 1217 if (r) { 1218 DRM_ERROR("failed to MES fw, r=%d\n", r); 1219 return r; 1220 } 1221 } 1222 1223 mes_v11_0_enable(adev, true); 1224 } 1225 1226 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1227 if (r) 1228 goto failure; 1229 1230 r = mes_v11_0_set_hw_resources(&adev->mes); 1231 if (r) 1232 goto failure; 1233 1234 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1235 1236 r = mes_v11_0_query_sched_status(&adev->mes); 1237 if (r) { 1238 DRM_ERROR("MES is busy\n"); 1239 goto failure; 1240 } 1241 1242 /* 1243 * Disable KIQ ring usage from the driver once MES is enabled. 1244 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1245 * with MES enabled. 1246 */ 1247 adev->gfx.kiq.ring.sched.ready = false; 1248 adev->mes.ring.sched.ready = true; 1249 1250 return 0; 1251 1252 failure: 1253 mes_v11_0_hw_fini(adev); 1254 return r; 1255 } 1256 1257 static int mes_v11_0_hw_fini(void *handle) 1258 { 1259 return 0; 1260 } 1261 1262 static int mes_v11_0_suspend(void *handle) 1263 { 1264 int r; 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 r = amdgpu_mes_suspend(adev); 1268 if (r) 1269 return r; 1270 1271 return mes_v11_0_hw_fini(adev); 1272 } 1273 1274 static int mes_v11_0_resume(void *handle) 1275 { 1276 int r; 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 1279 r = mes_v11_0_hw_init(adev); 1280 if (r) 1281 return r; 1282 1283 return amdgpu_mes_resume(adev); 1284 } 1285 1286 static int mes_v11_0_early_init(void *handle) 1287 { 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 int pipe, r; 1290 1291 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1292 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1293 continue; 1294 r = amdgpu_mes_init_microcode(adev, pipe); 1295 if (r) 1296 return r; 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int mes_v11_0_late_init(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1307 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1308 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1309 amdgpu_mes_self_test(adev); 1310 1311 return 0; 1312 } 1313 1314 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1315 .name = "mes_v11_0", 1316 .early_init = mes_v11_0_early_init, 1317 .late_init = mes_v11_0_late_init, 1318 .sw_init = mes_v11_0_sw_init, 1319 .sw_fini = mes_v11_0_sw_fini, 1320 .hw_init = mes_v11_0_hw_init, 1321 .hw_fini = mes_v11_0_hw_fini, 1322 .suspend = mes_v11_0_suspend, 1323 .resume = mes_v11_0_resume, 1324 }; 1325 1326 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1327 .type = AMD_IP_BLOCK_TYPE_MES, 1328 .major = 11, 1329 .minor = 0, 1330 .rev = 0, 1331 .funcs = &mes_v11_0_ip_funcs, 1332 }; 1333