1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v10_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 38 static int mes_v11_0_hw_fini(void *handle); 39 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 40 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 41 42 #define MES_EOP_SIZE 2048 43 44 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 45 { 46 struct amdgpu_device *adev = ring->adev; 47 48 if (ring->use_doorbell) { 49 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 50 ring->wptr); 51 WDOORBELL64(ring->doorbell_index, ring->wptr); 52 } else { 53 BUG(); 54 } 55 } 56 57 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 58 { 59 return *ring->rptr_cpu_addr; 60 } 61 62 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 63 { 64 u64 wptr; 65 66 if (ring->use_doorbell) 67 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 68 else 69 BUG(); 70 return wptr; 71 } 72 73 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 74 .type = AMDGPU_RING_TYPE_MES, 75 .align_mask = 1, 76 .nop = 0, 77 .support_64bit_ptrs = true, 78 .get_rptr = mes_v11_0_ring_get_rptr, 79 .get_wptr = mes_v11_0_ring_get_wptr, 80 .set_wptr = mes_v11_0_ring_set_wptr, 81 .insert_nop = amdgpu_ring_insert_nop, 82 }; 83 84 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 85 void *pkt, int size) 86 { 87 int ndw = size / 4; 88 signed long r; 89 union MESAPI__ADD_QUEUE *x_pkt = pkt; 90 struct amdgpu_device *adev = mes->adev; 91 struct amdgpu_ring *ring = &mes->ring; 92 93 BUG_ON(size % 4 != 0); 94 95 if (amdgpu_ring_alloc(ring, ndw)) 96 return -ENOMEM; 97 98 amdgpu_ring_write_multiple(ring, pkt, ndw); 99 amdgpu_ring_commit(ring); 100 101 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 102 103 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 104 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 105 if (r < 1) { 106 DRM_ERROR("MES failed to response msg=%d\n", 107 x_pkt->header.opcode); 108 return -ETIMEDOUT; 109 } 110 111 return 0; 112 } 113 114 static int convert_to_mes_queue_type(int queue_type) 115 { 116 if (queue_type == AMDGPU_RING_TYPE_GFX) 117 return MES_QUEUE_TYPE_GFX; 118 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 119 return MES_QUEUE_TYPE_COMPUTE; 120 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 121 return MES_QUEUE_TYPE_SDMA; 122 else 123 BUG(); 124 return -1; 125 } 126 127 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 128 struct mes_add_queue_input *input) 129 { 130 struct amdgpu_device *adev = mes->adev; 131 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 132 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 133 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 134 135 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 136 137 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 138 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 139 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 140 141 mes_add_queue_pkt.process_id = input->process_id; 142 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 143 mes_add_queue_pkt.process_va_start = input->process_va_start; 144 mes_add_queue_pkt.process_va_end = input->process_va_end; 145 mes_add_queue_pkt.process_quantum = input->process_quantum; 146 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 147 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 148 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 149 mes_add_queue_pkt.inprocess_gang_priority = 150 input->inprocess_gang_priority; 151 mes_add_queue_pkt.gang_global_priority_level = 152 input->gang_global_priority_level; 153 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 154 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 155 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 156 mes_add_queue_pkt.queue_type = 157 convert_to_mes_queue_type(input->queue_type); 158 mes_add_queue_pkt.paging = input->paging; 159 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 160 mes_add_queue_pkt.gws_base = input->gws_base; 161 mes_add_queue_pkt.gws_size = input->gws_size; 162 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 163 mes_add_queue_pkt.tma_addr = input->tma_addr; 164 165 mes_add_queue_pkt.api_status.api_completion_fence_addr = 166 mes->ring.fence_drv.gpu_addr; 167 mes_add_queue_pkt.api_status.api_completion_fence_value = 168 ++mes->ring.fence_drv.sync_seq; 169 170 return mes_v11_0_submit_pkt_and_poll_completion(mes, 171 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt)); 172 } 173 174 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 175 struct mes_remove_queue_input *input) 176 { 177 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 178 179 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 180 181 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 182 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 183 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 184 185 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 186 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 187 188 mes_remove_queue_pkt.api_status.api_completion_fence_addr = 189 mes->ring.fence_drv.gpu_addr; 190 mes_remove_queue_pkt.api_status.api_completion_fence_value = 191 ++mes->ring.fence_drv.sync_seq; 192 193 return mes_v11_0_submit_pkt_and_poll_completion(mes, 194 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt)); 195 } 196 197 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 198 struct mes_unmap_legacy_queue_input *input) 199 { 200 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 201 202 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 203 204 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 205 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 206 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 207 208 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset << 2; 209 mes_remove_queue_pkt.gang_context_addr = 0; 210 211 mes_remove_queue_pkt.pipe_id = input->pipe_id; 212 mes_remove_queue_pkt.queue_id = input->queue_id; 213 214 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 215 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 216 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 217 mes_remove_queue_pkt.tf_data = 218 lower_32_bits(input->trail_fence_data); 219 } else { 220 if (input->queue_type == AMDGPU_RING_TYPE_GFX) 221 mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1; 222 else 223 mes_remove_queue_pkt.unmap_kiq_utility_queue = 1; 224 } 225 226 mes_remove_queue_pkt.api_status.api_completion_fence_addr = 227 mes->ring.fence_drv.gpu_addr; 228 mes_remove_queue_pkt.api_status.api_completion_fence_value = 229 ++mes->ring.fence_drv.sync_seq; 230 231 return mes_v11_0_submit_pkt_and_poll_completion(mes, 232 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt)); 233 } 234 235 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 236 struct mes_suspend_gang_input *input) 237 { 238 return 0; 239 } 240 241 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 242 struct mes_resume_gang_input *input) 243 { 244 return 0; 245 } 246 247 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 248 { 249 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 250 251 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 252 253 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 254 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 255 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 256 257 mes_status_pkt.api_status.api_completion_fence_addr = 258 mes->ring.fence_drv.gpu_addr; 259 mes_status_pkt.api_status.api_completion_fence_value = 260 ++mes->ring.fence_drv.sync_seq; 261 262 return mes_v11_0_submit_pkt_and_poll_completion(mes, 263 &mes_status_pkt, sizeof(mes_status_pkt)); 264 } 265 266 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 267 { 268 int i; 269 struct amdgpu_device *adev = mes->adev; 270 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 271 272 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 273 274 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 275 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 276 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 277 278 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 279 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 280 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 281 mes_set_hw_res_pkt.paging_vmid = 0; 282 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 283 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 284 mes->query_status_fence_gpu_addr; 285 286 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 287 mes_set_hw_res_pkt.compute_hqd_mask[i] = 288 mes->compute_hqd_mask[i]; 289 290 for (i = 0; i < MAX_GFX_PIPES; i++) 291 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 292 293 for (i = 0; i < MAX_SDMA_PIPES; i++) 294 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 295 296 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 297 mes_set_hw_res_pkt.aggregated_doorbells[i] = 298 mes->agreegated_doorbells[i]; 299 300 for (i = 0; i < 5; i++) { 301 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 302 mes_set_hw_res_pkt.mmhub_base[i] = 303 adev->reg_offset[MMHUB_HWIP][0][i]; 304 mes_set_hw_res_pkt.osssys_base[i] = 305 adev->reg_offset[OSSSYS_HWIP][0][i]; 306 } 307 308 mes_set_hw_res_pkt.disable_reset = 1; 309 mes_set_hw_res_pkt.disable_mes_log = 1; 310 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 311 312 mes_set_hw_res_pkt.api_status.api_completion_fence_addr = 313 mes->ring.fence_drv.gpu_addr; 314 mes_set_hw_res_pkt.api_status.api_completion_fence_value = 315 ++mes->ring.fence_drv.sync_seq; 316 317 return mes_v11_0_submit_pkt_and_poll_completion(mes, 318 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt)); 319 } 320 321 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 322 .add_hw_queue = mes_v11_0_add_hw_queue, 323 .remove_hw_queue = mes_v11_0_remove_hw_queue, 324 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 325 .suspend_gang = mes_v11_0_suspend_gang, 326 .resume_gang = mes_v11_0_resume_gang, 327 }; 328 329 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 330 enum admgpu_mes_pipe pipe) 331 { 332 char fw_name[30]; 333 char ucode_prefix[30]; 334 int err; 335 const struct mes_firmware_header_v1_0 *mes_hdr; 336 struct amdgpu_firmware_info *info; 337 338 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 339 340 if (pipe == AMDGPU_MES_SCHED_PIPE) 341 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 342 ucode_prefix); 343 else 344 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 345 ucode_prefix); 346 347 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 348 if (err) 349 return err; 350 351 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 352 if (err) { 353 release_firmware(adev->mes.fw[pipe]); 354 adev->mes.fw[pipe] = NULL; 355 return err; 356 } 357 358 mes_hdr = (const struct mes_firmware_header_v1_0 *) 359 adev->mes.fw[pipe]->data; 360 adev->mes.ucode_fw_version[pipe] = 361 le32_to_cpu(mes_hdr->mes_ucode_version); 362 adev->mes.ucode_fw_version[pipe] = 363 le32_to_cpu(mes_hdr->mes_ucode_data_version); 364 adev->mes.uc_start_addr[pipe] = 365 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 366 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 367 adev->mes.data_start_addr[pipe] = 368 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 369 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 370 371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 372 int ucode, ucode_data; 373 374 if (pipe == AMDGPU_MES_SCHED_PIPE) { 375 ucode = AMDGPU_UCODE_ID_CP_MES; 376 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 377 } else { 378 ucode = AMDGPU_UCODE_ID_CP_MES1; 379 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 380 } 381 382 info = &adev->firmware.ucode[ucode]; 383 info->ucode_id = ucode; 384 info->fw = adev->mes.fw[pipe]; 385 adev->firmware.fw_size += 386 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 387 PAGE_SIZE); 388 389 info = &adev->firmware.ucode[ucode_data]; 390 info->ucode_id = ucode_data; 391 info->fw = adev->mes.fw[pipe]; 392 adev->firmware.fw_size += 393 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 394 PAGE_SIZE); 395 } 396 397 return 0; 398 } 399 400 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 401 enum admgpu_mes_pipe pipe) 402 { 403 release_firmware(adev->mes.fw[pipe]); 404 adev->mes.fw[pipe] = NULL; 405 } 406 407 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 408 enum admgpu_mes_pipe pipe) 409 { 410 int r; 411 const struct mes_firmware_header_v1_0 *mes_hdr; 412 const __le32 *fw_data; 413 unsigned fw_size; 414 415 mes_hdr = (const struct mes_firmware_header_v1_0 *) 416 adev->mes.fw[pipe]->data; 417 418 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 419 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 420 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 421 422 r = amdgpu_bo_create_reserved(adev, fw_size, 423 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 424 &adev->mes.ucode_fw_obj[pipe], 425 &adev->mes.ucode_fw_gpu_addr[pipe], 426 (void **)&adev->mes.ucode_fw_ptr[pipe]); 427 if (r) { 428 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 429 return r; 430 } 431 432 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 433 434 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 435 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 436 437 return 0; 438 } 439 440 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 441 enum admgpu_mes_pipe pipe) 442 { 443 int r; 444 const struct mes_firmware_header_v1_0 *mes_hdr; 445 const __le32 *fw_data; 446 unsigned fw_size; 447 448 mes_hdr = (const struct mes_firmware_header_v1_0 *) 449 adev->mes.fw[pipe]->data; 450 451 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 452 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 453 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 454 455 r = amdgpu_bo_create_reserved(adev, fw_size, 456 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 457 &adev->mes.data_fw_obj[pipe], 458 &adev->mes.data_fw_gpu_addr[pipe], 459 (void **)&adev->mes.data_fw_ptr[pipe]); 460 if (r) { 461 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 462 return r; 463 } 464 465 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 466 467 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 468 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 469 470 return 0; 471 } 472 473 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 474 enum admgpu_mes_pipe pipe) 475 { 476 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 477 &adev->mes.data_fw_gpu_addr[pipe], 478 (void **)&adev->mes.data_fw_ptr[pipe]); 479 480 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 481 &adev->mes.ucode_fw_gpu_addr[pipe], 482 (void **)&adev->mes.ucode_fw_ptr[pipe]); 483 } 484 485 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 486 { 487 uint64_t ucode_addr; 488 uint32_t pipe, data = 0; 489 490 if (enable) { 491 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 492 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 493 data = REG_SET_FIELD(data, CP_MES_CNTL, 494 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 495 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 496 497 mutex_lock(&adev->srbm_mutex); 498 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 499 if (!adev->enable_mes_kiq && 500 pipe == AMDGPU_MES_KIQ_PIPE) 501 continue; 502 503 soc21_grbm_select(adev, 3, pipe, 0, 0); 504 505 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 506 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 507 lower_32_bits(ucode_addr)); 508 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 509 upper_32_bits(ucode_addr)); 510 } 511 soc21_grbm_select(adev, 0, 0, 0, 0); 512 mutex_unlock(&adev->srbm_mutex); 513 514 /* unhalt MES and activate pipe0 */ 515 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 516 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 517 adev->enable_mes_kiq ? 1 : 0); 518 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 519 520 if (amdgpu_emu_mode) 521 msleep(100); 522 else 523 udelay(50); 524 } else { 525 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 526 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 527 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 528 data = REG_SET_FIELD(data, CP_MES_CNTL, 529 MES_INVALIDATE_ICACHE, 1); 530 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 531 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 532 adev->enable_mes_kiq ? 1 : 0); 533 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 534 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 535 } 536 } 537 538 /* This function is for backdoor MES firmware */ 539 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 540 enum admgpu_mes_pipe pipe) 541 { 542 int r; 543 uint32_t data; 544 uint64_t ucode_addr; 545 546 mes_v11_0_enable(adev, false); 547 548 if (!adev->mes.fw[pipe]) 549 return -EINVAL; 550 551 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 552 if (r) 553 return r; 554 555 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 556 if (r) { 557 mes_v11_0_free_ucode_buffers(adev, pipe); 558 return r; 559 } 560 561 mutex_lock(&adev->srbm_mutex); 562 /* me=3, pipe=0, queue=0 */ 563 soc21_grbm_select(adev, 3, pipe, 0, 0); 564 565 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 566 567 /* set ucode start address */ 568 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 569 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 570 lower_32_bits(ucode_addr)); 571 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 572 upper_32_bits(ucode_addr)); 573 574 /* set ucode fimrware address */ 575 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 576 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 577 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 578 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 579 580 /* set ucode instruction cache boundary to 2M-1 */ 581 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 582 583 /* set ucode data firmware address */ 584 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 585 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 586 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 587 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 588 589 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 590 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 591 592 /* invalidate ICACHE */ 593 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 594 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 595 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 596 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 597 598 /* prime the ICACHE. */ 599 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 600 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 601 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 602 603 soc21_grbm_select(adev, 0, 0, 0, 0); 604 mutex_unlock(&adev->srbm_mutex); 605 606 return 0; 607 } 608 609 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 610 enum admgpu_mes_pipe pipe) 611 { 612 int r; 613 u32 *eop; 614 615 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 616 AMDGPU_GEM_DOMAIN_GTT, 617 &adev->mes.eop_gpu_obj[pipe], 618 &adev->mes.eop_gpu_addr[pipe], 619 (void **)&eop); 620 if (r) { 621 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 622 return r; 623 } 624 625 memset(eop, 0, 626 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 627 628 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 629 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 630 631 return 0; 632 } 633 634 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 635 { 636 struct v10_compute_mqd *mqd = ring->mqd_ptr; 637 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 638 uint32_t tmp; 639 640 mqd->header = 0xC0310800; 641 mqd->compute_pipelinestat_enable = 0x00000001; 642 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 643 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 644 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 645 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 646 mqd->compute_misc_reserved = 0x00000007; 647 648 eop_base_addr = ring->eop_gpu_addr >> 8; 649 650 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 651 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 652 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 653 (order_base_2(MES_EOP_SIZE / 4) - 1)); 654 655 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 656 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 657 mqd->cp_hqd_eop_control = tmp; 658 659 /* disable the queue if it's active */ 660 ring->wptr = 0; 661 mqd->cp_hqd_pq_rptr = 0; 662 mqd->cp_hqd_pq_wptr_lo = 0; 663 mqd->cp_hqd_pq_wptr_hi = 0; 664 665 /* set the pointer to the MQD */ 666 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 667 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 668 669 /* set MQD vmid to 0 */ 670 tmp = regCP_MQD_CONTROL_DEFAULT; 671 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 672 mqd->cp_mqd_control = tmp; 673 674 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 675 hqd_gpu_addr = ring->gpu_addr >> 8; 676 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 677 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 678 679 /* set the wb address whether it's enabled or not */ 680 wb_gpu_addr = ring->rptr_gpu_addr; 681 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 682 mqd->cp_hqd_pq_rptr_report_addr_hi = 683 upper_32_bits(wb_gpu_addr) & 0xffff; 684 685 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 686 wb_gpu_addr = ring->wptr_gpu_addr; 687 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 688 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 689 690 /* set up the HQD, this is similar to CP_RB0_CNTL */ 691 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 692 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 693 (order_base_2(ring->ring_size / 4) - 1)); 694 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 695 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 696 #ifdef __BIG_ENDIAN 697 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 698 #endif 699 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 701 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 703 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 704 mqd->cp_hqd_pq_control = tmp; 705 706 /* enable doorbell */ 707 tmp = 0; 708 if (ring->use_doorbell) { 709 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 710 DOORBELL_OFFSET, ring->doorbell_index); 711 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 712 DOORBELL_EN, 1); 713 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 714 DOORBELL_SOURCE, 0); 715 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 716 DOORBELL_HIT, 0); 717 } 718 else 719 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 720 DOORBELL_EN, 0); 721 mqd->cp_hqd_pq_doorbell_control = tmp; 722 723 mqd->cp_hqd_vmid = 0; 724 /* activate the queue */ 725 mqd->cp_hqd_active = 1; 726 mqd->cp_hqd_persistent_state = regCP_HQD_PERSISTENT_STATE_DEFAULT; 727 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 728 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 729 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 730 731 tmp = regCP_HQD_GFX_CONTROL_DEFAULT; 732 tmp = REG_SET_FIELD(tmp, CP_HQD_GFX_CONTROL, DB_UPDATED_MSG_EN, 1); 733 /* offset: 184 - this is used for CP_HQD_GFX_CONTROL */ 734 mqd->cp_hqd_suspend_cntl_stack_offset = tmp; 735 736 return 0; 737 } 738 739 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 740 { 741 struct v10_compute_mqd *mqd = ring->mqd_ptr; 742 struct amdgpu_device *adev = ring->adev; 743 uint32_t data = 0; 744 745 mutex_lock(&adev->srbm_mutex); 746 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 747 748 /* set CP_HQD_VMID.VMID = 0. */ 749 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 750 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 751 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 752 753 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 754 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 755 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 756 DOORBELL_EN, 0); 757 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 758 759 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 760 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 761 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 762 763 /* set CP_MQD_CONTROL.VMID=0 */ 764 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 765 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 766 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 767 768 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 769 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 770 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 771 772 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 773 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 774 mqd->cp_hqd_pq_rptr_report_addr_lo); 775 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 776 mqd->cp_hqd_pq_rptr_report_addr_hi); 777 778 /* set CP_HQD_PQ_CONTROL */ 779 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 780 781 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 782 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 783 mqd->cp_hqd_pq_wptr_poll_addr_lo); 784 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 785 mqd->cp_hqd_pq_wptr_poll_addr_hi); 786 787 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 788 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 789 mqd->cp_hqd_pq_doorbell_control); 790 791 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 792 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 793 794 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 795 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 796 797 soc21_grbm_select(adev, 0, 0, 0, 0); 798 mutex_unlock(&adev->srbm_mutex); 799 } 800 801 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 802 { 803 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 804 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 805 int r; 806 807 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 808 return -EINVAL; 809 810 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 811 if (r) { 812 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 813 return r; 814 } 815 816 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 817 818 r = amdgpu_ring_test_ring(kiq_ring); 819 if (r) { 820 DRM_ERROR("kfq enable failed\n"); 821 kiq_ring->sched.ready = false; 822 } 823 return r; 824 } 825 826 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 827 enum admgpu_mes_pipe pipe) 828 { 829 struct amdgpu_ring *ring; 830 int r; 831 832 if (pipe == AMDGPU_MES_KIQ_PIPE) 833 ring = &adev->gfx.kiq.ring; 834 else if (pipe == AMDGPU_MES_SCHED_PIPE) 835 ring = &adev->mes.ring; 836 else 837 BUG(); 838 839 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 840 (amdgpu_in_reset(adev) || adev->in_suspend)) { 841 *(ring->wptr_cpu_addr) = 0; 842 *(ring->rptr_cpu_addr) = 0; 843 amdgpu_ring_clear_ring(ring); 844 } 845 846 r = mes_v11_0_mqd_init(ring); 847 if (r) 848 return r; 849 850 if (pipe == AMDGPU_MES_SCHED_PIPE) { 851 r = mes_v11_0_kiq_enable_queue(adev); 852 if (r) 853 return r; 854 } else { 855 mes_v11_0_queue_init_register(ring); 856 } 857 858 return 0; 859 } 860 861 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 862 { 863 struct amdgpu_ring *ring; 864 865 ring = &adev->mes.ring; 866 867 ring->funcs = &mes_v11_0_ring_funcs; 868 869 ring->me = 3; 870 ring->pipe = 0; 871 ring->queue = 0; 872 873 ring->ring_obj = NULL; 874 ring->use_doorbell = true; 875 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 876 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 877 ring->no_scheduler = true; 878 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 879 880 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 881 AMDGPU_RING_PRIO_DEFAULT, NULL); 882 } 883 884 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 885 { 886 struct amdgpu_ring *ring; 887 888 spin_lock_init(&adev->gfx.kiq.ring_lock); 889 890 ring = &adev->gfx.kiq.ring; 891 892 ring->me = 3; 893 ring->pipe = 1; 894 ring->queue = 0; 895 896 ring->adev = NULL; 897 ring->ring_obj = NULL; 898 ring->use_doorbell = true; 899 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 900 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 901 ring->no_scheduler = true; 902 sprintf(ring->name, "mes_kiq_%d.%d.%d", 903 ring->me, ring->pipe, ring->queue); 904 905 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 906 AMDGPU_RING_PRIO_DEFAULT, NULL); 907 } 908 909 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 910 enum admgpu_mes_pipe pipe) 911 { 912 int r, mqd_size = sizeof(struct v10_compute_mqd); 913 struct amdgpu_ring *ring; 914 915 if (pipe == AMDGPU_MES_KIQ_PIPE) 916 ring = &adev->gfx.kiq.ring; 917 else if (pipe == AMDGPU_MES_SCHED_PIPE) 918 ring = &adev->mes.ring; 919 else 920 BUG(); 921 922 if (ring->mqd_obj) 923 return 0; 924 925 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 926 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 927 &ring->mqd_gpu_addr, &ring->mqd_ptr); 928 if (r) { 929 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 930 return r; 931 } 932 933 memset(ring->mqd_ptr, 0, mqd_size); 934 935 /* prepare MQD backup */ 936 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 937 if (!adev->mes.mqd_backup[pipe]) 938 dev_warn(adev->dev, 939 "no memory to create MQD backup for ring %s\n", 940 ring->name); 941 942 return 0; 943 } 944 945 static int mes_v11_0_sw_init(void *handle) 946 { 947 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 948 int pipe, r; 949 950 adev->mes.adev = adev; 951 adev->mes.funcs = &mes_v11_0_funcs; 952 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 953 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 954 955 r = amdgpu_mes_init(adev); 956 if (r) 957 return r; 958 959 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 960 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 961 continue; 962 963 r = mes_v11_0_init_microcode(adev, pipe); 964 if (r) 965 return r; 966 967 r = mes_v11_0_allocate_eop_buf(adev, pipe); 968 if (r) 969 return r; 970 971 r = mes_v11_0_mqd_sw_init(adev, pipe); 972 if (r) 973 return r; 974 } 975 976 if (adev->enable_mes_kiq) { 977 r = mes_v11_0_kiq_ring_init(adev); 978 if (r) 979 return r; 980 } 981 982 r = mes_v11_0_ring_init(adev); 983 if (r) 984 return r; 985 986 return 0; 987 } 988 989 static int mes_v11_0_sw_fini(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 int pipe; 993 994 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 995 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 996 997 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 998 kfree(adev->mes.mqd_backup[pipe]); 999 1000 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1001 &adev->mes.eop_gpu_addr[pipe], 1002 NULL); 1003 1004 mes_v11_0_free_microcode(adev, pipe); 1005 } 1006 1007 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1008 &adev->gfx.kiq.ring.mqd_gpu_addr, 1009 &adev->gfx.kiq.ring.mqd_ptr); 1010 1011 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1012 &adev->mes.ring.mqd_gpu_addr, 1013 &adev->mes.ring.mqd_ptr); 1014 1015 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1016 amdgpu_ring_fini(&adev->mes.ring); 1017 1018 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1019 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1020 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1021 } 1022 1023 amdgpu_mes_fini(adev); 1024 return 0; 1025 } 1026 1027 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1028 { 1029 uint32_t tmp; 1030 struct amdgpu_device *adev = ring->adev; 1031 1032 /* tell RLC which is KIQ queue */ 1033 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1034 tmp &= 0xffffff00; 1035 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1036 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1037 tmp |= 0x80; 1038 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1039 } 1040 1041 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1042 { 1043 int r = 0; 1044 1045 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1046 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE); 1047 if (r) { 1048 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1049 return r; 1050 } 1051 1052 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1053 if (r) { 1054 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1055 return r; 1056 } 1057 } 1058 1059 mes_v11_0_enable(adev, true); 1060 1061 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1062 1063 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1064 if (r) 1065 goto failure; 1066 1067 return r; 1068 1069 failure: 1070 mes_v11_0_hw_fini(adev); 1071 return r; 1072 } 1073 1074 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1075 { 1076 mes_v11_0_enable(adev, false); 1077 return 0; 1078 } 1079 1080 static int mes_v11_0_hw_init(void *handle) 1081 { 1082 int r; 1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1084 1085 if (!adev->enable_mes_kiq) { 1086 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1087 r = mes_v11_0_load_microcode(adev, 1088 AMDGPU_MES_SCHED_PIPE); 1089 if (r) { 1090 DRM_ERROR("failed to MES fw, r=%d\n", r); 1091 return r; 1092 } 1093 } 1094 1095 mes_v11_0_enable(adev, true); 1096 } 1097 1098 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1099 if (r) 1100 goto failure; 1101 1102 r = mes_v11_0_set_hw_resources(&adev->mes); 1103 if (r) 1104 goto failure; 1105 1106 r = mes_v11_0_query_sched_status(&adev->mes); 1107 if (r) { 1108 DRM_ERROR("MES is busy\n"); 1109 goto failure; 1110 } 1111 1112 /* 1113 * Disable KIQ ring usage from the driver once MES is enabled. 1114 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1115 * with MES enabled. 1116 */ 1117 adev->gfx.kiq.ring.sched.ready = false; 1118 1119 return 0; 1120 1121 failure: 1122 mes_v11_0_hw_fini(adev); 1123 return r; 1124 } 1125 1126 static int mes_v11_0_hw_fini(void *handle) 1127 { 1128 return 0; 1129 } 1130 1131 static int mes_v11_0_suspend(void *handle) 1132 { 1133 int r; 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 r = amdgpu_mes_suspend(adev); 1137 if (r) 1138 return r; 1139 1140 return mes_v11_0_hw_fini(adev); 1141 } 1142 1143 static int mes_v11_0_resume(void *handle) 1144 { 1145 int r; 1146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1147 1148 r = mes_v11_0_hw_init(adev); 1149 if (r) 1150 return r; 1151 1152 return amdgpu_mes_resume(adev); 1153 } 1154 1155 static int mes_v11_0_late_init(void *handle) 1156 { 1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1158 1159 amdgpu_mes_self_test(adev); 1160 1161 return 0; 1162 } 1163 1164 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1165 .name = "mes_v11_0", 1166 .late_init = mes_v11_0_late_init, 1167 .sw_init = mes_v11_0_sw_init, 1168 .sw_fini = mes_v11_0_sw_fini, 1169 .hw_init = mes_v11_0_hw_init, 1170 .hw_fini = mes_v11_0_hw_fini, 1171 .suspend = mes_v11_0_suspend, 1172 .resume = mes_v11_0_resume, 1173 }; 1174 1175 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1176 .type = AMD_IP_BLOCK_TYPE_MES, 1177 .major = 11, 1178 .minor = 0, 1179 .rev = 0, 1180 .funcs = &mes_v11_0_ip_funcs, 1181 }; 1182