1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 42 static int mes_v11_0_hw_fini(void *handle); 43 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 44 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 45 46 #define MES_EOP_SIZE 2048 47 48 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 49 { 50 struct amdgpu_device *adev = ring->adev; 51 52 if (ring->use_doorbell) { 53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 54 ring->wptr); 55 WDOORBELL64(ring->doorbell_index, ring->wptr); 56 } else { 57 BUG(); 58 } 59 } 60 61 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 return *ring->rptr_cpu_addr; 64 } 65 66 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 67 { 68 u64 wptr; 69 70 if (ring->use_doorbell) 71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 72 else 73 BUG(); 74 return wptr; 75 } 76 77 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 78 .type = AMDGPU_RING_TYPE_MES, 79 .align_mask = 1, 80 .nop = 0, 81 .support_64bit_ptrs = true, 82 .get_rptr = mes_v11_0_ring_get_rptr, 83 .get_wptr = mes_v11_0_ring_get_wptr, 84 .set_wptr = mes_v11_0_ring_set_wptr, 85 .insert_nop = amdgpu_ring_insert_nop, 86 }; 87 88 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 89 void *pkt, int size, 90 int api_status_off) 91 { 92 int ndw = size / 4; 93 signed long r; 94 union MESAPI__ADD_QUEUE *x_pkt = pkt; 95 struct MES_API_STATUS *api_status; 96 struct amdgpu_device *adev = mes->adev; 97 struct amdgpu_ring *ring = &mes->ring; 98 unsigned long flags; 99 100 BUG_ON(size % 4 != 0); 101 102 spin_lock_irqsave(&mes->ring_lock, flags); 103 if (amdgpu_ring_alloc(ring, ndw)) { 104 spin_unlock_irqrestore(&mes->ring_lock, flags); 105 return -ENOMEM; 106 } 107 108 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 109 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 110 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 111 112 amdgpu_ring_write_multiple(ring, pkt, ndw); 113 amdgpu_ring_commit(ring); 114 spin_unlock_irqrestore(&mes->ring_lock, flags); 115 116 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 117 118 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 119 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 120 if (r < 1) { 121 DRM_ERROR("MES failed to response msg=%d\n", 122 x_pkt->header.opcode); 123 return -ETIMEDOUT; 124 } 125 126 return 0; 127 } 128 129 static int convert_to_mes_queue_type(int queue_type) 130 { 131 if (queue_type == AMDGPU_RING_TYPE_GFX) 132 return MES_QUEUE_TYPE_GFX; 133 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 134 return MES_QUEUE_TYPE_COMPUTE; 135 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 136 return MES_QUEUE_TYPE_SDMA; 137 else 138 BUG(); 139 return -1; 140 } 141 142 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 143 struct mes_add_queue_input *input) 144 { 145 struct amdgpu_device *adev = mes->adev; 146 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 147 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 148 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 149 150 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 151 152 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 153 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 154 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 155 156 mes_add_queue_pkt.process_id = input->process_id; 157 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 158 mes_add_queue_pkt.process_va_start = input->process_va_start; 159 mes_add_queue_pkt.process_va_end = input->process_va_end; 160 mes_add_queue_pkt.process_quantum = input->process_quantum; 161 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 162 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 163 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 164 mes_add_queue_pkt.inprocess_gang_priority = 165 input->inprocess_gang_priority; 166 mes_add_queue_pkt.gang_global_priority_level = 167 input->gang_global_priority_level; 168 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 169 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 170 171 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 172 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 173 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 174 else 175 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 176 177 mes_add_queue_pkt.queue_type = 178 convert_to_mes_queue_type(input->queue_type); 179 mes_add_queue_pkt.paging = input->paging; 180 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 181 mes_add_queue_pkt.gws_base = input->gws_base; 182 mes_add_queue_pkt.gws_size = input->gws_size; 183 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 184 mes_add_queue_pkt.tma_addr = input->tma_addr; 185 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 186 187 return mes_v11_0_submit_pkt_and_poll_completion(mes, 188 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 189 offsetof(union MESAPI__ADD_QUEUE, api_status)); 190 } 191 192 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 193 struct mes_remove_queue_input *input) 194 { 195 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 196 197 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 198 199 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 200 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 201 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 202 203 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 204 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 205 206 return mes_v11_0_submit_pkt_and_poll_completion(mes, 207 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 208 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 209 } 210 211 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 212 struct mes_unmap_legacy_queue_input *input) 213 { 214 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 215 216 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 217 218 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 219 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 220 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 221 222 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 223 mes_remove_queue_pkt.gang_context_addr = 0; 224 225 mes_remove_queue_pkt.pipe_id = input->pipe_id; 226 mes_remove_queue_pkt.queue_id = input->queue_id; 227 228 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 229 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 230 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 231 mes_remove_queue_pkt.tf_data = 232 lower_32_bits(input->trail_fence_data); 233 } else { 234 mes_remove_queue_pkt.unmap_legacy_queue = 1; 235 mes_remove_queue_pkt.queue_type = 236 convert_to_mes_queue_type(input->queue_type); 237 } 238 239 return mes_v11_0_submit_pkt_and_poll_completion(mes, 240 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 241 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 242 } 243 244 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 245 struct mes_suspend_gang_input *input) 246 { 247 return 0; 248 } 249 250 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 251 struct mes_resume_gang_input *input) 252 { 253 return 0; 254 } 255 256 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 257 { 258 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 259 260 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 261 262 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 263 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 264 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 265 266 return mes_v11_0_submit_pkt_and_poll_completion(mes, 267 &mes_status_pkt, sizeof(mes_status_pkt), 268 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 269 } 270 271 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 272 struct mes_misc_op_input *input) 273 { 274 union MESAPI__MISC misc_pkt; 275 276 memset(&misc_pkt, 0, sizeof(misc_pkt)); 277 278 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 279 misc_pkt.header.opcode = MES_SCH_API_MISC; 280 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 281 282 switch (input->op) { 283 case MES_MISC_OP_READ_REG: 284 misc_pkt.opcode = MESAPI_MISC__READ_REG; 285 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 286 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 287 break; 288 case MES_MISC_OP_WRITE_REG: 289 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 290 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 291 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 292 break; 293 case MES_MISC_OP_WRM_REG_WAIT: 294 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 295 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 296 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 297 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 298 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 299 misc_pkt.wait_reg_mem.reg_offset2 = 0; 300 break; 301 case MES_MISC_OP_WRM_REG_WR_WAIT: 302 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 303 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 304 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 305 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 306 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 307 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 308 break; 309 default: 310 DRM_ERROR("unsupported misc op (%d) \n", input->op); 311 return -EINVAL; 312 } 313 314 return mes_v11_0_submit_pkt_and_poll_completion(mes, 315 &misc_pkt, sizeof(misc_pkt), 316 offsetof(union MESAPI__MISC, api_status)); 317 } 318 319 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 320 { 321 int i; 322 struct amdgpu_device *adev = mes->adev; 323 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 324 325 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 326 327 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 328 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 329 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 330 331 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 332 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 333 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 334 mes_set_hw_res_pkt.paging_vmid = 0; 335 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 336 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 337 mes->query_status_fence_gpu_addr; 338 339 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 340 mes_set_hw_res_pkt.compute_hqd_mask[i] = 341 mes->compute_hqd_mask[i]; 342 343 for (i = 0; i < MAX_GFX_PIPES; i++) 344 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 345 346 for (i = 0; i < MAX_SDMA_PIPES; i++) 347 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 348 349 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 350 mes_set_hw_res_pkt.aggregated_doorbells[i] = 351 mes->agreegated_doorbells[i]; 352 353 for (i = 0; i < 5; i++) { 354 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 355 mes_set_hw_res_pkt.mmhub_base[i] = 356 adev->reg_offset[MMHUB_HWIP][0][i]; 357 mes_set_hw_res_pkt.osssys_base[i] = 358 adev->reg_offset[OSSSYS_HWIP][0][i]; 359 } 360 361 mes_set_hw_res_pkt.disable_reset = 1; 362 mes_set_hw_res_pkt.disable_mes_log = 1; 363 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 364 mes_set_hw_res_pkt.oversubscription_timer = 50; 365 366 return mes_v11_0_submit_pkt_and_poll_completion(mes, 367 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 368 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 369 } 370 371 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 372 .add_hw_queue = mes_v11_0_add_hw_queue, 373 .remove_hw_queue = mes_v11_0_remove_hw_queue, 374 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 375 .suspend_gang = mes_v11_0_suspend_gang, 376 .resume_gang = mes_v11_0_resume_gang, 377 .misc_op = mes_v11_0_misc_op, 378 }; 379 380 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 381 enum admgpu_mes_pipe pipe) 382 { 383 char fw_name[30]; 384 char ucode_prefix[30]; 385 int err; 386 const struct mes_firmware_header_v1_0 *mes_hdr; 387 struct amdgpu_firmware_info *info; 388 389 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 390 391 if (pipe == AMDGPU_MES_SCHED_PIPE) 392 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 393 ucode_prefix); 394 else 395 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 396 ucode_prefix); 397 398 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 399 if (err) 400 return err; 401 402 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 403 if (err) { 404 release_firmware(adev->mes.fw[pipe]); 405 adev->mes.fw[pipe] = NULL; 406 return err; 407 } 408 409 mes_hdr = (const struct mes_firmware_header_v1_0 *) 410 adev->mes.fw[pipe]->data; 411 adev->mes.ucode_fw_version[pipe] = 412 le32_to_cpu(mes_hdr->mes_ucode_version); 413 adev->mes.ucode_fw_version[pipe] = 414 le32_to_cpu(mes_hdr->mes_ucode_data_version); 415 adev->mes.uc_start_addr[pipe] = 416 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 417 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 418 adev->mes.data_start_addr[pipe] = 419 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 420 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 421 422 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 423 int ucode, ucode_data; 424 425 if (pipe == AMDGPU_MES_SCHED_PIPE) { 426 ucode = AMDGPU_UCODE_ID_CP_MES; 427 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 428 } else { 429 ucode = AMDGPU_UCODE_ID_CP_MES1; 430 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 431 } 432 433 info = &adev->firmware.ucode[ucode]; 434 info->ucode_id = ucode; 435 info->fw = adev->mes.fw[pipe]; 436 adev->firmware.fw_size += 437 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 438 PAGE_SIZE); 439 440 info = &adev->firmware.ucode[ucode_data]; 441 info->ucode_id = ucode_data; 442 info->fw = adev->mes.fw[pipe]; 443 adev->firmware.fw_size += 444 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 445 PAGE_SIZE); 446 } 447 448 return 0; 449 } 450 451 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 452 enum admgpu_mes_pipe pipe) 453 { 454 release_firmware(adev->mes.fw[pipe]); 455 adev->mes.fw[pipe] = NULL; 456 } 457 458 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 459 enum admgpu_mes_pipe pipe) 460 { 461 int r; 462 const struct mes_firmware_header_v1_0 *mes_hdr; 463 const __le32 *fw_data; 464 unsigned fw_size; 465 466 mes_hdr = (const struct mes_firmware_header_v1_0 *) 467 adev->mes.fw[pipe]->data; 468 469 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 470 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 471 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 472 473 r = amdgpu_bo_create_reserved(adev, fw_size, 474 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 475 &adev->mes.ucode_fw_obj[pipe], 476 &adev->mes.ucode_fw_gpu_addr[pipe], 477 (void **)&adev->mes.ucode_fw_ptr[pipe]); 478 if (r) { 479 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 480 return r; 481 } 482 483 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 484 485 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 486 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 487 488 return 0; 489 } 490 491 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 492 enum admgpu_mes_pipe pipe) 493 { 494 int r; 495 const struct mes_firmware_header_v1_0 *mes_hdr; 496 const __le32 *fw_data; 497 unsigned fw_size; 498 499 mes_hdr = (const struct mes_firmware_header_v1_0 *) 500 adev->mes.fw[pipe]->data; 501 502 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 503 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 504 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 505 506 r = amdgpu_bo_create_reserved(adev, fw_size, 507 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 508 &adev->mes.data_fw_obj[pipe], 509 &adev->mes.data_fw_gpu_addr[pipe], 510 (void **)&adev->mes.data_fw_ptr[pipe]); 511 if (r) { 512 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 513 return r; 514 } 515 516 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 517 518 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 519 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 520 521 return 0; 522 } 523 524 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 525 enum admgpu_mes_pipe pipe) 526 { 527 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 528 &adev->mes.data_fw_gpu_addr[pipe], 529 (void **)&adev->mes.data_fw_ptr[pipe]); 530 531 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 532 &adev->mes.ucode_fw_gpu_addr[pipe], 533 (void **)&adev->mes.ucode_fw_ptr[pipe]); 534 } 535 536 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 537 { 538 uint64_t ucode_addr; 539 uint32_t pipe, data = 0; 540 541 if (enable) { 542 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 543 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 544 data = REG_SET_FIELD(data, CP_MES_CNTL, 545 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 546 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 547 548 mutex_lock(&adev->srbm_mutex); 549 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 550 if (!adev->enable_mes_kiq && 551 pipe == AMDGPU_MES_KIQ_PIPE) 552 continue; 553 554 soc21_grbm_select(adev, 3, pipe, 0, 0); 555 556 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 557 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 558 lower_32_bits(ucode_addr)); 559 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 560 upper_32_bits(ucode_addr)); 561 } 562 soc21_grbm_select(adev, 0, 0, 0, 0); 563 mutex_unlock(&adev->srbm_mutex); 564 565 /* unhalt MES and activate pipe0 */ 566 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 567 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 568 adev->enable_mes_kiq ? 1 : 0); 569 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 570 571 if (amdgpu_emu_mode) 572 msleep(100); 573 else 574 udelay(50); 575 } else { 576 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 577 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 578 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 579 data = REG_SET_FIELD(data, CP_MES_CNTL, 580 MES_INVALIDATE_ICACHE, 1); 581 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 582 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 583 adev->enable_mes_kiq ? 1 : 0); 584 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 585 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 586 } 587 } 588 589 /* This function is for backdoor MES firmware */ 590 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 591 enum admgpu_mes_pipe pipe, bool prime_icache) 592 { 593 int r; 594 uint32_t data; 595 uint64_t ucode_addr; 596 597 mes_v11_0_enable(adev, false); 598 599 if (!adev->mes.fw[pipe]) 600 return -EINVAL; 601 602 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 603 if (r) 604 return r; 605 606 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 607 if (r) { 608 mes_v11_0_free_ucode_buffers(adev, pipe); 609 return r; 610 } 611 612 mutex_lock(&adev->srbm_mutex); 613 /* me=3, pipe=0, queue=0 */ 614 soc21_grbm_select(adev, 3, pipe, 0, 0); 615 616 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 617 618 /* set ucode start address */ 619 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 620 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 621 lower_32_bits(ucode_addr)); 622 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 623 upper_32_bits(ucode_addr)); 624 625 /* set ucode fimrware address */ 626 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 627 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 628 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 629 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 630 631 /* set ucode instruction cache boundary to 2M-1 */ 632 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 633 634 /* set ucode data firmware address */ 635 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 636 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 637 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 638 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 639 640 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 641 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 642 643 if (prime_icache) { 644 /* invalidate ICACHE */ 645 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 646 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 647 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 648 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 649 650 /* prime the ICACHE. */ 651 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 652 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 653 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 654 } 655 656 soc21_grbm_select(adev, 0, 0, 0, 0); 657 mutex_unlock(&adev->srbm_mutex); 658 659 return 0; 660 } 661 662 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 663 enum admgpu_mes_pipe pipe) 664 { 665 int r; 666 u32 *eop; 667 668 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 669 AMDGPU_GEM_DOMAIN_GTT, 670 &adev->mes.eop_gpu_obj[pipe], 671 &adev->mes.eop_gpu_addr[pipe], 672 (void **)&eop); 673 if (r) { 674 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 675 return r; 676 } 677 678 memset(eop, 0, 679 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 680 681 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 682 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 683 684 return 0; 685 } 686 687 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 688 { 689 struct v11_compute_mqd *mqd = ring->mqd_ptr; 690 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 691 uint32_t tmp; 692 693 mqd->header = 0xC0310800; 694 mqd->compute_pipelinestat_enable = 0x00000001; 695 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 696 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 697 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 698 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 699 mqd->compute_misc_reserved = 0x00000007; 700 701 eop_base_addr = ring->eop_gpu_addr >> 8; 702 703 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 704 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 705 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 706 (order_base_2(MES_EOP_SIZE / 4) - 1)); 707 708 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 709 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 710 mqd->cp_hqd_eop_control = tmp; 711 712 /* disable the queue if it's active */ 713 ring->wptr = 0; 714 mqd->cp_hqd_pq_rptr = 0; 715 mqd->cp_hqd_pq_wptr_lo = 0; 716 mqd->cp_hqd_pq_wptr_hi = 0; 717 718 /* set the pointer to the MQD */ 719 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 720 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 721 722 /* set MQD vmid to 0 */ 723 tmp = regCP_MQD_CONTROL_DEFAULT; 724 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 725 mqd->cp_mqd_control = tmp; 726 727 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 728 hqd_gpu_addr = ring->gpu_addr >> 8; 729 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 730 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 731 732 /* set the wb address whether it's enabled or not */ 733 wb_gpu_addr = ring->rptr_gpu_addr; 734 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 735 mqd->cp_hqd_pq_rptr_report_addr_hi = 736 upper_32_bits(wb_gpu_addr) & 0xffff; 737 738 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 739 wb_gpu_addr = ring->wptr_gpu_addr; 740 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 741 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 742 743 /* set up the HQD, this is similar to CP_RB0_CNTL */ 744 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 745 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 746 (order_base_2(ring->ring_size / 4) - 1)); 747 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 748 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 749 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 750 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 751 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 752 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 753 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 754 mqd->cp_hqd_pq_control = tmp; 755 756 /* enable doorbell */ 757 tmp = 0; 758 if (ring->use_doorbell) { 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 760 DOORBELL_OFFSET, ring->doorbell_index); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 762 DOORBELL_EN, 1); 763 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 764 DOORBELL_SOURCE, 0); 765 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 766 DOORBELL_HIT, 0); 767 } 768 else 769 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 770 DOORBELL_EN, 0); 771 mqd->cp_hqd_pq_doorbell_control = tmp; 772 773 mqd->cp_hqd_vmid = 0; 774 /* activate the queue */ 775 mqd->cp_hqd_active = 1; 776 777 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 778 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 779 PRELOAD_SIZE, 0x55); 780 mqd->cp_hqd_persistent_state = tmp; 781 782 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 783 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 784 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 785 786 return 0; 787 } 788 789 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 790 { 791 struct v11_compute_mqd *mqd = ring->mqd_ptr; 792 struct amdgpu_device *adev = ring->adev; 793 uint32_t data = 0; 794 795 mutex_lock(&adev->srbm_mutex); 796 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 797 798 /* set CP_HQD_VMID.VMID = 0. */ 799 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 800 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 801 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 802 803 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 804 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 805 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 806 DOORBELL_EN, 0); 807 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 808 809 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 810 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 811 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 812 813 /* set CP_MQD_CONTROL.VMID=0 */ 814 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 815 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 816 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 817 818 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 819 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 820 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 821 822 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 823 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 824 mqd->cp_hqd_pq_rptr_report_addr_lo); 825 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 826 mqd->cp_hqd_pq_rptr_report_addr_hi); 827 828 /* set CP_HQD_PQ_CONTROL */ 829 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 830 831 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 832 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 833 mqd->cp_hqd_pq_wptr_poll_addr_lo); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 835 mqd->cp_hqd_pq_wptr_poll_addr_hi); 836 837 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 839 mqd->cp_hqd_pq_doorbell_control); 840 841 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 842 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 843 844 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 845 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 846 847 soc21_grbm_select(adev, 0, 0, 0, 0); 848 mutex_unlock(&adev->srbm_mutex); 849 } 850 851 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 852 { 853 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 854 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 855 int r; 856 857 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 858 return -EINVAL; 859 860 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 861 if (r) { 862 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 863 return r; 864 } 865 866 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 867 868 r = amdgpu_ring_test_ring(kiq_ring); 869 if (r) { 870 DRM_ERROR("kfq enable failed\n"); 871 kiq_ring->sched.ready = false; 872 } 873 return r; 874 } 875 876 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 877 enum admgpu_mes_pipe pipe) 878 { 879 struct amdgpu_ring *ring; 880 int r; 881 882 if (pipe == AMDGPU_MES_KIQ_PIPE) 883 ring = &adev->gfx.kiq.ring; 884 else if (pipe == AMDGPU_MES_SCHED_PIPE) 885 ring = &adev->mes.ring; 886 else 887 BUG(); 888 889 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 890 (amdgpu_in_reset(adev) || adev->in_suspend)) { 891 *(ring->wptr_cpu_addr) = 0; 892 *(ring->rptr_cpu_addr) = 0; 893 amdgpu_ring_clear_ring(ring); 894 } 895 896 r = mes_v11_0_mqd_init(ring); 897 if (r) 898 return r; 899 900 if (pipe == AMDGPU_MES_SCHED_PIPE) { 901 r = mes_v11_0_kiq_enable_queue(adev); 902 if (r) 903 return r; 904 } else { 905 mes_v11_0_queue_init_register(ring); 906 } 907 908 /* get MES scheduler/KIQ versions */ 909 mutex_lock(&adev->srbm_mutex); 910 soc21_grbm_select(adev, 3, pipe, 0, 0); 911 912 if (pipe == AMDGPU_MES_SCHED_PIPE) 913 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 914 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 915 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 916 917 soc21_grbm_select(adev, 0, 0, 0, 0); 918 mutex_unlock(&adev->srbm_mutex); 919 920 return 0; 921 } 922 923 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 924 { 925 struct amdgpu_ring *ring; 926 927 ring = &adev->mes.ring; 928 929 ring->funcs = &mes_v11_0_ring_funcs; 930 931 ring->me = 3; 932 ring->pipe = 0; 933 ring->queue = 0; 934 935 ring->ring_obj = NULL; 936 ring->use_doorbell = true; 937 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 938 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 939 ring->no_scheduler = true; 940 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 941 942 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 943 AMDGPU_RING_PRIO_DEFAULT, NULL); 944 } 945 946 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 947 { 948 struct amdgpu_ring *ring; 949 950 spin_lock_init(&adev->gfx.kiq.ring_lock); 951 952 ring = &adev->gfx.kiq.ring; 953 954 ring->me = 3; 955 ring->pipe = 1; 956 ring->queue = 0; 957 958 ring->adev = NULL; 959 ring->ring_obj = NULL; 960 ring->use_doorbell = true; 961 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 962 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 963 ring->no_scheduler = true; 964 sprintf(ring->name, "mes_kiq_%d.%d.%d", 965 ring->me, ring->pipe, ring->queue); 966 967 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 968 AMDGPU_RING_PRIO_DEFAULT, NULL); 969 } 970 971 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 972 enum admgpu_mes_pipe pipe) 973 { 974 int r, mqd_size = sizeof(struct v11_compute_mqd); 975 struct amdgpu_ring *ring; 976 977 if (pipe == AMDGPU_MES_KIQ_PIPE) 978 ring = &adev->gfx.kiq.ring; 979 else if (pipe == AMDGPU_MES_SCHED_PIPE) 980 ring = &adev->mes.ring; 981 else 982 BUG(); 983 984 if (ring->mqd_obj) 985 return 0; 986 987 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 988 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 989 &ring->mqd_gpu_addr, &ring->mqd_ptr); 990 if (r) { 991 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 992 return r; 993 } 994 995 memset(ring->mqd_ptr, 0, mqd_size); 996 997 /* prepare MQD backup */ 998 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 999 if (!adev->mes.mqd_backup[pipe]) 1000 dev_warn(adev->dev, 1001 "no memory to create MQD backup for ring %s\n", 1002 ring->name); 1003 1004 return 0; 1005 } 1006 1007 static int mes_v11_0_sw_init(void *handle) 1008 { 1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1010 int pipe, r; 1011 1012 adev->mes.adev = adev; 1013 adev->mes.funcs = &mes_v11_0_funcs; 1014 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1015 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1016 1017 r = amdgpu_mes_init(adev); 1018 if (r) 1019 return r; 1020 1021 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1022 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1023 continue; 1024 1025 r = mes_v11_0_init_microcode(adev, pipe); 1026 if (r) 1027 return r; 1028 1029 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1030 if (r) 1031 return r; 1032 1033 r = mes_v11_0_mqd_sw_init(adev, pipe); 1034 if (r) 1035 return r; 1036 } 1037 1038 if (adev->enable_mes_kiq) { 1039 r = mes_v11_0_kiq_ring_init(adev); 1040 if (r) 1041 return r; 1042 } 1043 1044 r = mes_v11_0_ring_init(adev); 1045 if (r) 1046 return r; 1047 1048 return 0; 1049 } 1050 1051 static int mes_v11_0_sw_fini(void *handle) 1052 { 1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1054 int pipe; 1055 1056 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1057 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1058 1059 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1060 kfree(adev->mes.mqd_backup[pipe]); 1061 1062 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1063 &adev->mes.eop_gpu_addr[pipe], 1064 NULL); 1065 1066 mes_v11_0_free_microcode(adev, pipe); 1067 } 1068 1069 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1070 &adev->gfx.kiq.ring.mqd_gpu_addr, 1071 &adev->gfx.kiq.ring.mqd_ptr); 1072 1073 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1074 &adev->mes.ring.mqd_gpu_addr, 1075 &adev->mes.ring.mqd_ptr); 1076 1077 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1078 amdgpu_ring_fini(&adev->mes.ring); 1079 1080 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1081 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1082 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1083 } 1084 1085 amdgpu_mes_fini(adev); 1086 return 0; 1087 } 1088 1089 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1090 { 1091 uint32_t tmp; 1092 struct amdgpu_device *adev = ring->adev; 1093 1094 /* tell RLC which is KIQ queue */ 1095 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1096 tmp &= 0xffffff00; 1097 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1098 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1099 tmp |= 0x80; 1100 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1101 } 1102 1103 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1104 { 1105 int r = 0; 1106 1107 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1108 1109 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1110 if (r) { 1111 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1112 return r; 1113 } 1114 1115 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1116 if (r) { 1117 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1118 return r; 1119 } 1120 1121 } 1122 1123 mes_v11_0_enable(adev, true); 1124 1125 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1126 1127 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1128 if (r) 1129 goto failure; 1130 1131 return r; 1132 1133 failure: 1134 mes_v11_0_hw_fini(adev); 1135 return r; 1136 } 1137 1138 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1139 { 1140 mes_v11_0_enable(adev, false); 1141 return 0; 1142 } 1143 1144 static int mes_v11_0_hw_init(void *handle) 1145 { 1146 int r; 1147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1148 1149 if (!adev->enable_mes_kiq) { 1150 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1151 r = mes_v11_0_load_microcode(adev, 1152 AMDGPU_MES_SCHED_PIPE, true); 1153 if (r) { 1154 DRM_ERROR("failed to MES fw, r=%d\n", r); 1155 return r; 1156 } 1157 } 1158 1159 mes_v11_0_enable(adev, true); 1160 } 1161 1162 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1163 if (r) 1164 goto failure; 1165 1166 r = mes_v11_0_set_hw_resources(&adev->mes); 1167 if (r) 1168 goto failure; 1169 1170 r = mes_v11_0_query_sched_status(&adev->mes); 1171 if (r) { 1172 DRM_ERROR("MES is busy\n"); 1173 goto failure; 1174 } 1175 1176 /* 1177 * Disable KIQ ring usage from the driver once MES is enabled. 1178 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1179 * with MES enabled. 1180 */ 1181 adev->gfx.kiq.ring.sched.ready = false; 1182 adev->mes.ring.sched.ready = true; 1183 1184 return 0; 1185 1186 failure: 1187 mes_v11_0_hw_fini(adev); 1188 return r; 1189 } 1190 1191 static int mes_v11_0_hw_fini(void *handle) 1192 { 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1194 1195 adev->mes.ring.sched.ready = false; 1196 return 0; 1197 } 1198 1199 static int mes_v11_0_suspend(void *handle) 1200 { 1201 int r; 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 1204 r = amdgpu_mes_suspend(adev); 1205 if (r) 1206 return r; 1207 1208 return mes_v11_0_hw_fini(adev); 1209 } 1210 1211 static int mes_v11_0_resume(void *handle) 1212 { 1213 int r; 1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1215 1216 r = mes_v11_0_hw_init(adev); 1217 if (r) 1218 return r; 1219 1220 return amdgpu_mes_resume(adev); 1221 } 1222 1223 static int mes_v11_0_late_init(void *handle) 1224 { 1225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1226 1227 amdgpu_mes_self_test(adev); 1228 1229 return 0; 1230 } 1231 1232 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1233 .name = "mes_v11_0", 1234 .late_init = mes_v11_0_late_init, 1235 .sw_init = mes_v11_0_sw_init, 1236 .sw_fini = mes_v11_0_sw_fini, 1237 .hw_init = mes_v11_0_hw_init, 1238 .hw_fini = mes_v11_0_hw_fini, 1239 .suspend = mes_v11_0_suspend, 1240 .resume = mes_v11_0_resume, 1241 }; 1242 1243 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1244 .type = AMD_IP_BLOCK_TYPE_MES, 1245 .major = 11, 1246 .minor = 0, 1247 .rev = 0, 1248 .funcs = &mes_v11_0_ip_funcs, 1249 }; 1250