1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 42 static int mes_v11_0_hw_fini(void *handle); 43 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 44 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 45 46 #define MES_EOP_SIZE 2048 47 48 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 49 { 50 struct amdgpu_device *adev = ring->adev; 51 52 if (ring->use_doorbell) { 53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 54 ring->wptr); 55 WDOORBELL64(ring->doorbell_index, ring->wptr); 56 } else { 57 BUG(); 58 } 59 } 60 61 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 return *ring->rptr_cpu_addr; 64 } 65 66 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 67 { 68 u64 wptr; 69 70 if (ring->use_doorbell) 71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 72 else 73 BUG(); 74 return wptr; 75 } 76 77 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 78 .type = AMDGPU_RING_TYPE_MES, 79 .align_mask = 1, 80 .nop = 0, 81 .support_64bit_ptrs = true, 82 .get_rptr = mes_v11_0_ring_get_rptr, 83 .get_wptr = mes_v11_0_ring_get_wptr, 84 .set_wptr = mes_v11_0_ring_set_wptr, 85 .insert_nop = amdgpu_ring_insert_nop, 86 }; 87 88 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 89 void *pkt, int size, 90 int api_status_off) 91 { 92 int ndw = size / 4; 93 signed long r; 94 union MESAPI__ADD_QUEUE *x_pkt = pkt; 95 struct MES_API_STATUS *api_status; 96 struct amdgpu_device *adev = mes->adev; 97 struct amdgpu_ring *ring = &mes->ring; 98 unsigned long flags; 99 100 BUG_ON(size % 4 != 0); 101 102 spin_lock_irqsave(&mes->ring_lock, flags); 103 if (amdgpu_ring_alloc(ring, ndw)) { 104 spin_unlock_irqrestore(&mes->ring_lock, flags); 105 return -ENOMEM; 106 } 107 108 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 109 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 110 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 111 112 amdgpu_ring_write_multiple(ring, pkt, ndw); 113 amdgpu_ring_commit(ring); 114 spin_unlock_irqrestore(&mes->ring_lock, flags); 115 116 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 117 118 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 119 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1)); 120 if (r < 1) { 121 DRM_ERROR("MES failed to response msg=%d\n", 122 x_pkt->header.opcode); 123 return -ETIMEDOUT; 124 } 125 126 return 0; 127 } 128 129 static int convert_to_mes_queue_type(int queue_type) 130 { 131 if (queue_type == AMDGPU_RING_TYPE_GFX) 132 return MES_QUEUE_TYPE_GFX; 133 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 134 return MES_QUEUE_TYPE_COMPUTE; 135 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 136 return MES_QUEUE_TYPE_SDMA; 137 else 138 BUG(); 139 return -1; 140 } 141 142 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 143 struct mes_add_queue_input *input) 144 { 145 struct amdgpu_device *adev = mes->adev; 146 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 147 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 148 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 149 150 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 151 152 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 153 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 154 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 155 156 mes_add_queue_pkt.process_id = input->process_id; 157 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 158 mes_add_queue_pkt.process_va_start = input->process_va_start; 159 mes_add_queue_pkt.process_va_end = input->process_va_end; 160 mes_add_queue_pkt.process_quantum = input->process_quantum; 161 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 162 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 163 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 164 mes_add_queue_pkt.inprocess_gang_priority = 165 input->inprocess_gang_priority; 166 mes_add_queue_pkt.gang_global_priority_level = 167 input->gang_global_priority_level; 168 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 169 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 170 171 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 172 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 173 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 174 else 175 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 176 177 mes_add_queue_pkt.queue_type = 178 convert_to_mes_queue_type(input->queue_type); 179 mes_add_queue_pkt.paging = input->paging; 180 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 181 mes_add_queue_pkt.gws_base = input->gws_base; 182 mes_add_queue_pkt.gws_size = input->gws_size; 183 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 184 mes_add_queue_pkt.tma_addr = input->tma_addr; 185 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 186 187 return mes_v11_0_submit_pkt_and_poll_completion(mes, 188 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 189 offsetof(union MESAPI__ADD_QUEUE, api_status)); 190 } 191 192 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 193 struct mes_remove_queue_input *input) 194 { 195 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 196 197 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 198 199 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 200 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 201 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 202 203 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 204 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 205 206 return mes_v11_0_submit_pkt_and_poll_completion(mes, 207 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 208 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 209 } 210 211 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 212 struct mes_unmap_legacy_queue_input *input) 213 { 214 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 215 216 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 217 218 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 219 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 220 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 221 222 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 223 mes_remove_queue_pkt.gang_context_addr = 0; 224 225 mes_remove_queue_pkt.pipe_id = input->pipe_id; 226 mes_remove_queue_pkt.queue_id = input->queue_id; 227 228 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 229 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 230 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 231 mes_remove_queue_pkt.tf_data = 232 lower_32_bits(input->trail_fence_data); 233 } else { 234 mes_remove_queue_pkt.unmap_legacy_queue = 1; 235 mes_remove_queue_pkt.queue_type = 236 convert_to_mes_queue_type(input->queue_type); 237 } 238 239 return mes_v11_0_submit_pkt_and_poll_completion(mes, 240 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 241 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 242 } 243 244 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 245 struct mes_suspend_gang_input *input) 246 { 247 return 0; 248 } 249 250 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 251 struct mes_resume_gang_input *input) 252 { 253 return 0; 254 } 255 256 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 257 { 258 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 259 260 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 261 262 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 263 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 264 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 265 266 return mes_v11_0_submit_pkt_and_poll_completion(mes, 267 &mes_status_pkt, sizeof(mes_status_pkt), 268 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 269 } 270 271 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 272 struct mes_misc_op_input *input) 273 { 274 union MESAPI__MISC misc_pkt; 275 276 memset(&misc_pkt, 0, sizeof(misc_pkt)); 277 278 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 279 misc_pkt.header.opcode = MES_SCH_API_MISC; 280 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 281 282 switch (input->op) { 283 case MES_MISC_OP_READ_REG: 284 misc_pkt.opcode = MESAPI_MISC__READ_REG; 285 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 286 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 287 break; 288 case MES_MISC_OP_WRITE_REG: 289 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 290 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 291 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 292 break; 293 case MES_MISC_OP_WRM_REG_WAIT: 294 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 295 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 296 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 297 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 298 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 299 misc_pkt.wait_reg_mem.reg_offset2 = 0; 300 break; 301 case MES_MISC_OP_WRM_REG_WR_WAIT: 302 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 303 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 304 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 305 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 306 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 307 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 308 break; 309 default: 310 DRM_ERROR("unsupported misc op (%d) \n", input->op); 311 return -EINVAL; 312 } 313 314 return mes_v11_0_submit_pkt_and_poll_completion(mes, 315 &misc_pkt, sizeof(misc_pkt), 316 offsetof(union MESAPI__MISC, api_status)); 317 } 318 319 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 320 { 321 int i; 322 struct amdgpu_device *adev = mes->adev; 323 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 324 325 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 326 327 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 328 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 329 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 330 331 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 332 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 333 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 334 mes_set_hw_res_pkt.paging_vmid = 0; 335 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 336 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 337 mes->query_status_fence_gpu_addr; 338 339 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 340 mes_set_hw_res_pkt.compute_hqd_mask[i] = 341 mes->compute_hqd_mask[i]; 342 343 for (i = 0; i < MAX_GFX_PIPES; i++) 344 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 345 346 for (i = 0; i < MAX_SDMA_PIPES; i++) 347 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 348 349 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 350 mes_set_hw_res_pkt.aggregated_doorbells[i] = 351 mes->aggregated_doorbells[i]; 352 353 for (i = 0; i < 5; i++) { 354 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 355 mes_set_hw_res_pkt.mmhub_base[i] = 356 adev->reg_offset[MMHUB_HWIP][0][i]; 357 mes_set_hw_res_pkt.osssys_base[i] = 358 adev->reg_offset[OSSSYS_HWIP][0][i]; 359 } 360 361 mes_set_hw_res_pkt.disable_reset = 1; 362 mes_set_hw_res_pkt.disable_mes_log = 1; 363 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 364 mes_set_hw_res_pkt.oversubscription_timer = 50; 365 366 return mes_v11_0_submit_pkt_and_poll_completion(mes, 367 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 368 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 369 } 370 371 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 372 { 373 struct amdgpu_device *adev = mes->adev; 374 uint32_t data; 375 376 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 377 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 378 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 379 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 380 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 381 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 382 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 383 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 384 385 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 386 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 387 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 388 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 389 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 390 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 391 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 392 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 393 394 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 395 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 396 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 397 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 398 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 399 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 400 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 401 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 402 403 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 404 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 405 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 406 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 407 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 408 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 409 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 410 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 411 412 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 413 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 414 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 415 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 416 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 417 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 418 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 419 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 420 421 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 422 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 423 } 424 425 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 426 .add_hw_queue = mes_v11_0_add_hw_queue, 427 .remove_hw_queue = mes_v11_0_remove_hw_queue, 428 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 429 .suspend_gang = mes_v11_0_suspend_gang, 430 .resume_gang = mes_v11_0_resume_gang, 431 .misc_op = mes_v11_0_misc_op, 432 }; 433 434 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 435 enum admgpu_mes_pipe pipe) 436 { 437 char fw_name[30]; 438 char ucode_prefix[30]; 439 int err; 440 const struct mes_firmware_header_v1_0 *mes_hdr; 441 struct amdgpu_firmware_info *info; 442 443 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 444 445 if (pipe == AMDGPU_MES_SCHED_PIPE) 446 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 447 ucode_prefix); 448 else 449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 450 ucode_prefix); 451 452 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 453 if (err) 454 return err; 455 456 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 457 if (err) { 458 release_firmware(adev->mes.fw[pipe]); 459 adev->mes.fw[pipe] = NULL; 460 return err; 461 } 462 463 mes_hdr = (const struct mes_firmware_header_v1_0 *) 464 adev->mes.fw[pipe]->data; 465 adev->mes.ucode_fw_version[pipe] = 466 le32_to_cpu(mes_hdr->mes_ucode_version); 467 adev->mes.ucode_fw_version[pipe] = 468 le32_to_cpu(mes_hdr->mes_ucode_data_version); 469 adev->mes.uc_start_addr[pipe] = 470 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 471 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 472 adev->mes.data_start_addr[pipe] = 473 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 474 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 475 476 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 477 int ucode, ucode_data; 478 479 if (pipe == AMDGPU_MES_SCHED_PIPE) { 480 ucode = AMDGPU_UCODE_ID_CP_MES; 481 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 482 } else { 483 ucode = AMDGPU_UCODE_ID_CP_MES1; 484 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 485 } 486 487 info = &adev->firmware.ucode[ucode]; 488 info->ucode_id = ucode; 489 info->fw = adev->mes.fw[pipe]; 490 adev->firmware.fw_size += 491 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 492 PAGE_SIZE); 493 494 info = &adev->firmware.ucode[ucode_data]; 495 info->ucode_id = ucode_data; 496 info->fw = adev->mes.fw[pipe]; 497 adev->firmware.fw_size += 498 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 499 PAGE_SIZE); 500 } 501 502 return 0; 503 } 504 505 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 506 enum admgpu_mes_pipe pipe) 507 { 508 release_firmware(adev->mes.fw[pipe]); 509 adev->mes.fw[pipe] = NULL; 510 } 511 512 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 513 enum admgpu_mes_pipe pipe) 514 { 515 int r; 516 const struct mes_firmware_header_v1_0 *mes_hdr; 517 const __le32 *fw_data; 518 unsigned fw_size; 519 520 mes_hdr = (const struct mes_firmware_header_v1_0 *) 521 adev->mes.fw[pipe]->data; 522 523 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 524 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 525 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 526 527 r = amdgpu_bo_create_reserved(adev, fw_size, 528 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 529 &adev->mes.ucode_fw_obj[pipe], 530 &adev->mes.ucode_fw_gpu_addr[pipe], 531 (void **)&adev->mes.ucode_fw_ptr[pipe]); 532 if (r) { 533 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 534 return r; 535 } 536 537 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 538 539 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 540 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 541 542 return 0; 543 } 544 545 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 546 enum admgpu_mes_pipe pipe) 547 { 548 int r; 549 const struct mes_firmware_header_v1_0 *mes_hdr; 550 const __le32 *fw_data; 551 unsigned fw_size; 552 553 mes_hdr = (const struct mes_firmware_header_v1_0 *) 554 adev->mes.fw[pipe]->data; 555 556 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 557 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 558 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 559 560 r = amdgpu_bo_create_reserved(adev, fw_size, 561 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 562 &adev->mes.data_fw_obj[pipe], 563 &adev->mes.data_fw_gpu_addr[pipe], 564 (void **)&adev->mes.data_fw_ptr[pipe]); 565 if (r) { 566 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 567 return r; 568 } 569 570 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 571 572 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 573 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 574 575 return 0; 576 } 577 578 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 579 enum admgpu_mes_pipe pipe) 580 { 581 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 582 &adev->mes.data_fw_gpu_addr[pipe], 583 (void **)&adev->mes.data_fw_ptr[pipe]); 584 585 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 586 &adev->mes.ucode_fw_gpu_addr[pipe], 587 (void **)&adev->mes.ucode_fw_ptr[pipe]); 588 } 589 590 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 591 { 592 uint64_t ucode_addr; 593 uint32_t pipe, data = 0; 594 595 if (enable) { 596 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 597 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 598 data = REG_SET_FIELD(data, CP_MES_CNTL, 599 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 600 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 601 602 mutex_lock(&adev->srbm_mutex); 603 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 604 if (!adev->enable_mes_kiq && 605 pipe == AMDGPU_MES_KIQ_PIPE) 606 continue; 607 608 soc21_grbm_select(adev, 3, pipe, 0, 0); 609 610 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 611 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 612 lower_32_bits(ucode_addr)); 613 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 614 upper_32_bits(ucode_addr)); 615 } 616 soc21_grbm_select(adev, 0, 0, 0, 0); 617 mutex_unlock(&adev->srbm_mutex); 618 619 /* unhalt MES and activate pipe0 */ 620 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 621 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 622 adev->enable_mes_kiq ? 1 : 0); 623 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 624 625 if (amdgpu_emu_mode) 626 msleep(100); 627 else 628 udelay(50); 629 } else { 630 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 631 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 632 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 633 data = REG_SET_FIELD(data, CP_MES_CNTL, 634 MES_INVALIDATE_ICACHE, 1); 635 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 636 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 637 adev->enable_mes_kiq ? 1 : 0); 638 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 639 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 640 } 641 } 642 643 /* This function is for backdoor MES firmware */ 644 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 645 enum admgpu_mes_pipe pipe, bool prime_icache) 646 { 647 int r; 648 uint32_t data; 649 uint64_t ucode_addr; 650 651 mes_v11_0_enable(adev, false); 652 653 if (!adev->mes.fw[pipe]) 654 return -EINVAL; 655 656 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 657 if (r) 658 return r; 659 660 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 661 if (r) { 662 mes_v11_0_free_ucode_buffers(adev, pipe); 663 return r; 664 } 665 666 mutex_lock(&adev->srbm_mutex); 667 /* me=3, pipe=0, queue=0 */ 668 soc21_grbm_select(adev, 3, pipe, 0, 0); 669 670 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 671 672 /* set ucode start address */ 673 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 674 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 675 lower_32_bits(ucode_addr)); 676 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 677 upper_32_bits(ucode_addr)); 678 679 /* set ucode fimrware address */ 680 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 681 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 682 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 683 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 684 685 /* set ucode instruction cache boundary to 2M-1 */ 686 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 687 688 /* set ucode data firmware address */ 689 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 690 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 691 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 692 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 693 694 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 695 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 696 697 if (prime_icache) { 698 /* invalidate ICACHE */ 699 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 700 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 701 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 702 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 703 704 /* prime the ICACHE. */ 705 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 706 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 707 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 708 } 709 710 soc21_grbm_select(adev, 0, 0, 0, 0); 711 mutex_unlock(&adev->srbm_mutex); 712 713 return 0; 714 } 715 716 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 717 enum admgpu_mes_pipe pipe) 718 { 719 int r; 720 u32 *eop; 721 722 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 723 AMDGPU_GEM_DOMAIN_GTT, 724 &adev->mes.eop_gpu_obj[pipe], 725 &adev->mes.eop_gpu_addr[pipe], 726 (void **)&eop); 727 if (r) { 728 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 729 return r; 730 } 731 732 memset(eop, 0, 733 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 734 735 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 736 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 737 738 return 0; 739 } 740 741 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 742 { 743 struct v11_compute_mqd *mqd = ring->mqd_ptr; 744 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 745 uint32_t tmp; 746 747 mqd->header = 0xC0310800; 748 mqd->compute_pipelinestat_enable = 0x00000001; 749 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 750 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 751 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 752 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 753 mqd->compute_misc_reserved = 0x00000007; 754 755 eop_base_addr = ring->eop_gpu_addr >> 8; 756 757 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 758 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 759 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 760 (order_base_2(MES_EOP_SIZE / 4) - 1)); 761 762 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 763 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 764 mqd->cp_hqd_eop_control = tmp; 765 766 /* disable the queue if it's active */ 767 ring->wptr = 0; 768 mqd->cp_hqd_pq_rptr = 0; 769 mqd->cp_hqd_pq_wptr_lo = 0; 770 mqd->cp_hqd_pq_wptr_hi = 0; 771 772 /* set the pointer to the MQD */ 773 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 774 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 775 776 /* set MQD vmid to 0 */ 777 tmp = regCP_MQD_CONTROL_DEFAULT; 778 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 779 mqd->cp_mqd_control = tmp; 780 781 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 782 hqd_gpu_addr = ring->gpu_addr >> 8; 783 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 784 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 785 786 /* set the wb address whether it's enabled or not */ 787 wb_gpu_addr = ring->rptr_gpu_addr; 788 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 789 mqd->cp_hqd_pq_rptr_report_addr_hi = 790 upper_32_bits(wb_gpu_addr) & 0xffff; 791 792 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 793 wb_gpu_addr = ring->wptr_gpu_addr; 794 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 795 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 796 797 /* set up the HQD, this is similar to CP_RB0_CNTL */ 798 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 800 (order_base_2(ring->ring_size / 4) - 1)); 801 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 802 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 803 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 805 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 806 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 807 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 808 mqd->cp_hqd_pq_control = tmp; 809 810 /* enable doorbell */ 811 tmp = 0; 812 if (ring->use_doorbell) { 813 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 814 DOORBELL_OFFSET, ring->doorbell_index); 815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 816 DOORBELL_EN, 1); 817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 818 DOORBELL_SOURCE, 0); 819 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 820 DOORBELL_HIT, 0); 821 } 822 else 823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 824 DOORBELL_EN, 0); 825 mqd->cp_hqd_pq_doorbell_control = tmp; 826 827 mqd->cp_hqd_vmid = 0; 828 /* activate the queue */ 829 mqd->cp_hqd_active = 1; 830 831 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 832 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 833 PRELOAD_SIZE, 0x55); 834 mqd->cp_hqd_persistent_state = tmp; 835 836 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 837 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 838 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 839 840 return 0; 841 } 842 843 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 844 { 845 struct v11_compute_mqd *mqd = ring->mqd_ptr; 846 struct amdgpu_device *adev = ring->adev; 847 uint32_t data = 0; 848 849 mutex_lock(&adev->srbm_mutex); 850 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 851 852 /* set CP_HQD_VMID.VMID = 0. */ 853 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 854 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 855 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 856 857 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 858 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 859 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 860 DOORBELL_EN, 0); 861 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 862 863 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 864 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 865 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 866 867 /* set CP_MQD_CONTROL.VMID=0 */ 868 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 869 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 870 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 871 872 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 873 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 874 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 875 876 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 877 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 878 mqd->cp_hqd_pq_rptr_report_addr_lo); 879 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 880 mqd->cp_hqd_pq_rptr_report_addr_hi); 881 882 /* set CP_HQD_PQ_CONTROL */ 883 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 884 885 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 886 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 887 mqd->cp_hqd_pq_wptr_poll_addr_lo); 888 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 889 mqd->cp_hqd_pq_wptr_poll_addr_hi); 890 891 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 892 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 893 mqd->cp_hqd_pq_doorbell_control); 894 895 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 896 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 897 898 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 899 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 900 901 soc21_grbm_select(adev, 0, 0, 0, 0); 902 mutex_unlock(&adev->srbm_mutex); 903 } 904 905 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 906 { 907 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 908 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 909 int r; 910 911 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 912 return -EINVAL; 913 914 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 915 if (r) { 916 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 917 return r; 918 } 919 920 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 921 922 r = amdgpu_ring_test_ring(kiq_ring); 923 if (r) { 924 DRM_ERROR("kfq enable failed\n"); 925 kiq_ring->sched.ready = false; 926 } 927 return r; 928 } 929 930 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 931 enum admgpu_mes_pipe pipe) 932 { 933 struct amdgpu_ring *ring; 934 int r; 935 936 if (pipe == AMDGPU_MES_KIQ_PIPE) 937 ring = &adev->gfx.kiq.ring; 938 else if (pipe == AMDGPU_MES_SCHED_PIPE) 939 ring = &adev->mes.ring; 940 else 941 BUG(); 942 943 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 944 (amdgpu_in_reset(adev) || adev->in_suspend)) { 945 *(ring->wptr_cpu_addr) = 0; 946 *(ring->rptr_cpu_addr) = 0; 947 amdgpu_ring_clear_ring(ring); 948 } 949 950 r = mes_v11_0_mqd_init(ring); 951 if (r) 952 return r; 953 954 if (pipe == AMDGPU_MES_SCHED_PIPE) { 955 r = mes_v11_0_kiq_enable_queue(adev); 956 if (r) 957 return r; 958 } else { 959 mes_v11_0_queue_init_register(ring); 960 } 961 962 /* get MES scheduler/KIQ versions */ 963 mutex_lock(&adev->srbm_mutex); 964 soc21_grbm_select(adev, 3, pipe, 0, 0); 965 966 if (pipe == AMDGPU_MES_SCHED_PIPE) 967 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 968 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 969 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 970 971 soc21_grbm_select(adev, 0, 0, 0, 0); 972 mutex_unlock(&adev->srbm_mutex); 973 974 return 0; 975 } 976 977 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 978 { 979 struct amdgpu_ring *ring; 980 981 ring = &adev->mes.ring; 982 983 ring->funcs = &mes_v11_0_ring_funcs; 984 985 ring->me = 3; 986 ring->pipe = 0; 987 ring->queue = 0; 988 989 ring->ring_obj = NULL; 990 ring->use_doorbell = true; 991 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 992 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 993 ring->no_scheduler = true; 994 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 995 996 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 997 AMDGPU_RING_PRIO_DEFAULT, NULL); 998 } 999 1000 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1001 { 1002 struct amdgpu_ring *ring; 1003 1004 spin_lock_init(&adev->gfx.kiq.ring_lock); 1005 1006 ring = &adev->gfx.kiq.ring; 1007 1008 ring->me = 3; 1009 ring->pipe = 1; 1010 ring->queue = 0; 1011 1012 ring->adev = NULL; 1013 ring->ring_obj = NULL; 1014 ring->use_doorbell = true; 1015 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1016 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1017 ring->no_scheduler = true; 1018 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1019 ring->me, ring->pipe, ring->queue); 1020 1021 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1022 AMDGPU_RING_PRIO_DEFAULT, NULL); 1023 } 1024 1025 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1026 enum admgpu_mes_pipe pipe) 1027 { 1028 int r, mqd_size = sizeof(struct v11_compute_mqd); 1029 struct amdgpu_ring *ring; 1030 1031 if (pipe == AMDGPU_MES_KIQ_PIPE) 1032 ring = &adev->gfx.kiq.ring; 1033 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1034 ring = &adev->mes.ring; 1035 else 1036 BUG(); 1037 1038 if (ring->mqd_obj) 1039 return 0; 1040 1041 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1042 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1043 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1044 if (r) { 1045 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1046 return r; 1047 } 1048 1049 memset(ring->mqd_ptr, 0, mqd_size); 1050 1051 /* prepare MQD backup */ 1052 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1053 if (!adev->mes.mqd_backup[pipe]) 1054 dev_warn(adev->dev, 1055 "no memory to create MQD backup for ring %s\n", 1056 ring->name); 1057 1058 return 0; 1059 } 1060 1061 static int mes_v11_0_sw_init(void *handle) 1062 { 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 int pipe, r; 1065 1066 adev->mes.adev = adev; 1067 adev->mes.funcs = &mes_v11_0_funcs; 1068 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1069 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1070 1071 r = amdgpu_mes_init(adev); 1072 if (r) 1073 return r; 1074 1075 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1076 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1077 continue; 1078 1079 r = mes_v11_0_init_microcode(adev, pipe); 1080 if (r) 1081 return r; 1082 1083 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1084 if (r) 1085 return r; 1086 1087 r = mes_v11_0_mqd_sw_init(adev, pipe); 1088 if (r) 1089 return r; 1090 } 1091 1092 if (adev->enable_mes_kiq) { 1093 r = mes_v11_0_kiq_ring_init(adev); 1094 if (r) 1095 return r; 1096 } 1097 1098 r = mes_v11_0_ring_init(adev); 1099 if (r) 1100 return r; 1101 1102 return 0; 1103 } 1104 1105 static int mes_v11_0_sw_fini(void *handle) 1106 { 1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1108 int pipe; 1109 1110 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1111 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1112 1113 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1114 kfree(adev->mes.mqd_backup[pipe]); 1115 1116 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1117 &adev->mes.eop_gpu_addr[pipe], 1118 NULL); 1119 1120 mes_v11_0_free_microcode(adev, pipe); 1121 } 1122 1123 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1124 &adev->gfx.kiq.ring.mqd_gpu_addr, 1125 &adev->gfx.kiq.ring.mqd_ptr); 1126 1127 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1128 &adev->mes.ring.mqd_gpu_addr, 1129 &adev->mes.ring.mqd_ptr); 1130 1131 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1132 amdgpu_ring_fini(&adev->mes.ring); 1133 1134 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1135 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1136 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1137 } 1138 1139 amdgpu_mes_fini(adev); 1140 return 0; 1141 } 1142 1143 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1144 { 1145 uint32_t tmp; 1146 struct amdgpu_device *adev = ring->adev; 1147 1148 /* tell RLC which is KIQ queue */ 1149 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1150 tmp &= 0xffffff00; 1151 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1152 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1153 tmp |= 0x80; 1154 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1155 } 1156 1157 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1158 { 1159 int r = 0; 1160 1161 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1162 1163 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1164 if (r) { 1165 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1166 return r; 1167 } 1168 1169 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1170 if (r) { 1171 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1172 return r; 1173 } 1174 1175 } 1176 1177 mes_v11_0_enable(adev, true); 1178 1179 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1180 1181 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1182 if (r) 1183 goto failure; 1184 1185 return r; 1186 1187 failure: 1188 mes_v11_0_hw_fini(adev); 1189 return r; 1190 } 1191 1192 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1193 { 1194 mes_v11_0_enable(adev, false); 1195 return 0; 1196 } 1197 1198 static int mes_v11_0_hw_init(void *handle) 1199 { 1200 int r; 1201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1202 1203 if (!adev->enable_mes_kiq) { 1204 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1205 r = mes_v11_0_load_microcode(adev, 1206 AMDGPU_MES_SCHED_PIPE, true); 1207 if (r) { 1208 DRM_ERROR("failed to MES fw, r=%d\n", r); 1209 return r; 1210 } 1211 } 1212 1213 mes_v11_0_enable(adev, true); 1214 } 1215 1216 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1217 if (r) 1218 goto failure; 1219 1220 r = mes_v11_0_set_hw_resources(&adev->mes); 1221 if (r) 1222 goto failure; 1223 1224 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1225 1226 r = mes_v11_0_query_sched_status(&adev->mes); 1227 if (r) { 1228 DRM_ERROR("MES is busy\n"); 1229 goto failure; 1230 } 1231 1232 /* 1233 * Disable KIQ ring usage from the driver once MES is enabled. 1234 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1235 * with MES enabled. 1236 */ 1237 adev->gfx.kiq.ring.sched.ready = false; 1238 adev->mes.ring.sched.ready = true; 1239 1240 return 0; 1241 1242 failure: 1243 mes_v11_0_hw_fini(adev); 1244 return r; 1245 } 1246 1247 static int mes_v11_0_hw_fini(void *handle) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 adev->mes.ring.sched.ready = false; 1252 return 0; 1253 } 1254 1255 static int mes_v11_0_suspend(void *handle) 1256 { 1257 int r; 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 r = amdgpu_mes_suspend(adev); 1261 if (r) 1262 return r; 1263 1264 return mes_v11_0_hw_fini(adev); 1265 } 1266 1267 static int mes_v11_0_resume(void *handle) 1268 { 1269 int r; 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 1272 r = mes_v11_0_hw_init(adev); 1273 if (r) 1274 return r; 1275 1276 return amdgpu_mes_resume(adev); 1277 } 1278 1279 static int mes_v11_0_late_init(void *handle) 1280 { 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 1283 if (!amdgpu_in_reset(adev)) 1284 amdgpu_mes_self_test(adev); 1285 1286 return 0; 1287 } 1288 1289 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1290 .name = "mes_v11_0", 1291 .late_init = mes_v11_0_late_init, 1292 .sw_init = mes_v11_0_sw_init, 1293 .sw_fini = mes_v11_0_sw_fini, 1294 .hw_init = mes_v11_0_hw_init, 1295 .hw_fini = mes_v11_0_hw_fini, 1296 .suspend = mes_v11_0_suspend, 1297 .resume = mes_v11_0_resume, 1298 }; 1299 1300 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1301 .type = AMD_IP_BLOCK_TYPE_MES, 1302 .major = 11, 1303 .minor = 0, 1304 .rev = 0, 1305 .funcs = &mes_v11_0_ip_funcs, 1306 }; 1307