1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "nv.h" 29 #include "gc/gc_10_1_0_offset.h" 30 #include "gc/gc_10_1_0_sh_mask.h" 31 #include "gc/gc_10_1_0_default.h" 32 #include "v10_structs.h" 33 #include "mes_api_def.h" 34 35 #define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid 0x2820 36 #define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX 1 37 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 38 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 39 40 MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); 41 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); 43 44 static int mes_v10_1_hw_fini(void *handle); 45 static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v10_1_ring_get_rptr, 84 .get_wptr = mes_v10_1_ring_get_wptr, 85 .set_wptr = mes_v10_1_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 90 void *pkt, int size, 91 int api_status_off) 92 { 93 int ndw = size / 4; 94 signed long r; 95 union MESAPI__ADD_QUEUE *x_pkt = pkt; 96 struct MES_API_STATUS *api_status; 97 struct amdgpu_device *adev = mes->adev; 98 struct amdgpu_ring *ring = &mes->ring; 99 unsigned long flags; 100 101 BUG_ON(size % 4 != 0); 102 103 spin_lock_irqsave(&mes->ring_lock, flags); 104 if (amdgpu_ring_alloc(ring, ndw)) { 105 spin_unlock_irqrestore(&mes->ring_lock, flags); 106 return -ENOMEM; 107 } 108 109 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 112 113 amdgpu_ring_write_multiple(ring, pkt, ndw); 114 amdgpu_ring_commit(ring); 115 spin_unlock_irqrestore(&mes->ring_lock, flags); 116 117 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 118 119 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 120 adev->usec_timeout); 121 if (r < 1) { 122 DRM_ERROR("MES failed to response msg=%d\n", 123 x_pkt->header.opcode); 124 return -ETIMEDOUT; 125 } 126 127 return 0; 128 } 129 130 static int convert_to_mes_queue_type(int queue_type) 131 { 132 if (queue_type == AMDGPU_RING_TYPE_GFX) 133 return MES_QUEUE_TYPE_GFX; 134 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 135 return MES_QUEUE_TYPE_COMPUTE; 136 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 137 return MES_QUEUE_TYPE_SDMA; 138 else 139 BUG(); 140 return -1; 141 } 142 143 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, 144 struct mes_add_queue_input *input) 145 { 146 struct amdgpu_device *adev = mes->adev; 147 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 148 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 149 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 150 151 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 152 153 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 154 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 155 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 156 157 mes_add_queue_pkt.process_id = input->process_id; 158 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 159 mes_add_queue_pkt.process_va_start = input->process_va_start; 160 mes_add_queue_pkt.process_va_end = input->process_va_end; 161 mes_add_queue_pkt.process_quantum = input->process_quantum; 162 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 163 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 164 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 165 mes_add_queue_pkt.inprocess_gang_priority = 166 input->inprocess_gang_priority; 167 mes_add_queue_pkt.gang_global_priority_level = 168 input->gang_global_priority_level; 169 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 170 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 171 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 172 mes_add_queue_pkt.queue_type = 173 convert_to_mes_queue_type(input->queue_type); 174 mes_add_queue_pkt.paging = input->paging; 175 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 176 mes_add_queue_pkt.gws_base = input->gws_base; 177 mes_add_queue_pkt.gws_size = input->gws_size; 178 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 179 180 return mes_v10_1_submit_pkt_and_poll_completion(mes, 181 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 182 offsetof(union MESAPI__ADD_QUEUE, api_status)); 183 } 184 185 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes, 186 struct mes_remove_queue_input *input) 187 { 188 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 189 190 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 191 192 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 193 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 194 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 195 196 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 197 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 198 199 return mes_v10_1_submit_pkt_and_poll_completion(mes, 200 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 201 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 202 } 203 204 static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes, 205 struct mes_unmap_legacy_queue_input *input) 206 { 207 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 208 209 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 210 211 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 212 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 213 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 214 215 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 216 mes_remove_queue_pkt.gang_context_addr = 0; 217 218 mes_remove_queue_pkt.pipe_id = input->pipe_id; 219 mes_remove_queue_pkt.queue_id = input->queue_id; 220 221 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 222 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 223 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 224 mes_remove_queue_pkt.tf_data = 225 lower_32_bits(input->trail_fence_data); 226 } else { 227 if (input->queue_type == AMDGPU_RING_TYPE_GFX) 228 mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1; 229 else 230 mes_remove_queue_pkt.unmap_kiq_utility_queue = 1; 231 } 232 233 return mes_v10_1_submit_pkt_and_poll_completion(mes, 234 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 235 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 236 } 237 238 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes, 239 struct mes_suspend_gang_input *input) 240 { 241 return 0; 242 } 243 244 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes, 245 struct mes_resume_gang_input *input) 246 { 247 return 0; 248 } 249 250 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) 251 { 252 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 253 254 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 255 256 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 257 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 258 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 259 260 return mes_v10_1_submit_pkt_and_poll_completion(mes, 261 &mes_status_pkt, sizeof(mes_status_pkt), 262 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 263 } 264 265 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) 266 { 267 int i; 268 struct amdgpu_device *adev = mes->adev; 269 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 270 271 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 272 273 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 274 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 275 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 276 277 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 278 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 279 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 280 mes_set_hw_res_pkt.paging_vmid = 0; 281 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 282 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 283 mes->query_status_fence_gpu_addr; 284 285 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 286 mes_set_hw_res_pkt.compute_hqd_mask[i] = 287 mes->compute_hqd_mask[i]; 288 289 for (i = 0; i < MAX_GFX_PIPES; i++) 290 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 291 292 for (i = 0; i < MAX_SDMA_PIPES; i++) 293 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 294 295 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 296 mes_set_hw_res_pkt.aggregated_doorbells[i] = 297 mes->aggregated_doorbells[i]; 298 299 for (i = 0; i < 5; i++) { 300 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 301 mes_set_hw_res_pkt.mmhub_base[i] = 302 adev->reg_offset[MMHUB_HWIP][0][i]; 303 mes_set_hw_res_pkt.osssys_base[i] = 304 adev->reg_offset[OSSSYS_HWIP][0][i]; 305 } 306 307 mes_set_hw_res_pkt.disable_reset = 1; 308 mes_set_hw_res_pkt.disable_mes_log = 1; 309 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 310 311 return mes_v10_1_submit_pkt_and_poll_completion(mes, 312 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 313 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 314 } 315 316 static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes) 317 { 318 struct amdgpu_device *adev = mes->adev; 319 uint32_t data; 320 321 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1); 322 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 323 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 324 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 325 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 326 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 327 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 328 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1, data); 329 330 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2); 331 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 332 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 333 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 334 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 335 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 336 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 337 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2, data); 338 339 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3); 340 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 341 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 342 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 343 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 344 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 345 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 346 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3, data); 347 348 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4); 349 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 350 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 351 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 352 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 353 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 354 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 355 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4, data); 356 357 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5); 358 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 359 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 360 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 361 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 362 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 363 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 364 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5, data); 365 366 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 367 WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data); 368 } 369 370 static const struct amdgpu_mes_funcs mes_v10_1_funcs = { 371 .add_hw_queue = mes_v10_1_add_hw_queue, 372 .remove_hw_queue = mes_v10_1_remove_hw_queue, 373 .unmap_legacy_queue = mes_v10_1_unmap_legacy_queue, 374 .suspend_gang = mes_v10_1_suspend_gang, 375 .resume_gang = mes_v10_1_resume_gang, 376 }; 377 378 static int mes_v10_1_init_microcode(struct amdgpu_device *adev, 379 enum admgpu_mes_pipe pipe) 380 { 381 const char *chip_name; 382 char fw_name[30]; 383 int err; 384 const struct mes_firmware_header_v1_0 *mes_hdr; 385 struct amdgpu_firmware_info *info; 386 387 switch (adev->ip_versions[GC_HWIP][0]) { 388 case IP_VERSION(10, 1, 10): 389 chip_name = "navi10"; 390 break; 391 case IP_VERSION(10, 3, 0): 392 chip_name = "sienna_cichlid"; 393 break; 394 default: 395 BUG(); 396 } 397 398 if (pipe == AMDGPU_MES_SCHED_PIPE) 399 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 400 chip_name); 401 else 402 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 403 chip_name); 404 405 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 406 if (err) 407 return err; 408 409 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 410 if (err) { 411 release_firmware(adev->mes.fw[pipe]); 412 adev->mes.fw[pipe] = NULL; 413 return err; 414 } 415 416 mes_hdr = (const struct mes_firmware_header_v1_0 *) 417 adev->mes.fw[pipe]->data; 418 adev->mes.uc_start_addr[pipe] = 419 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 420 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 421 adev->mes.data_start_addr[pipe] = 422 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 423 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 424 425 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 426 int ucode, ucode_data; 427 428 if (pipe == AMDGPU_MES_SCHED_PIPE) { 429 ucode = AMDGPU_UCODE_ID_CP_MES; 430 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 431 } else { 432 ucode = AMDGPU_UCODE_ID_CP_MES1; 433 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 434 } 435 436 info = &adev->firmware.ucode[ucode]; 437 info->ucode_id = ucode; 438 info->fw = adev->mes.fw[pipe]; 439 adev->firmware.fw_size += 440 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 441 PAGE_SIZE); 442 443 info = &adev->firmware.ucode[ucode_data]; 444 info->ucode_id = ucode_data; 445 info->fw = adev->mes.fw[pipe]; 446 adev->firmware.fw_size += 447 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 448 PAGE_SIZE); 449 } 450 451 return 0; 452 } 453 454 static void mes_v10_1_free_microcode(struct amdgpu_device *adev, 455 enum admgpu_mes_pipe pipe) 456 { 457 release_firmware(adev->mes.fw[pipe]); 458 adev->mes.fw[pipe] = NULL; 459 } 460 461 static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev, 462 enum admgpu_mes_pipe pipe) 463 { 464 int r; 465 const struct mes_firmware_header_v1_0 *mes_hdr; 466 const __le32 *fw_data; 467 unsigned fw_size; 468 469 mes_hdr = (const struct mes_firmware_header_v1_0 *) 470 adev->mes.fw[pipe]->data; 471 472 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 473 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 474 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 475 476 r = amdgpu_bo_create_reserved(adev, fw_size, 477 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 478 &adev->mes.ucode_fw_obj[pipe], 479 &adev->mes.ucode_fw_gpu_addr[pipe], 480 (void **)&adev->mes.ucode_fw_ptr[pipe]); 481 if (r) { 482 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 483 return r; 484 } 485 486 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 487 488 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 489 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 490 491 return 0; 492 } 493 494 static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 495 enum admgpu_mes_pipe pipe) 496 { 497 int r; 498 const struct mes_firmware_header_v1_0 *mes_hdr; 499 const __le32 *fw_data; 500 unsigned fw_size; 501 502 mes_hdr = (const struct mes_firmware_header_v1_0 *) 503 adev->mes.fw[pipe]->data; 504 505 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 506 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 507 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 508 509 r = amdgpu_bo_create_reserved(adev, fw_size, 510 64 * 1024, AMDGPU_GEM_DOMAIN_GTT, 511 &adev->mes.data_fw_obj[pipe], 512 &adev->mes.data_fw_gpu_addr[pipe], 513 (void **)&adev->mes.data_fw_ptr[pipe]); 514 if (r) { 515 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 516 return r; 517 } 518 519 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 520 521 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 522 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 523 524 return 0; 525 } 526 527 static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev, 528 enum admgpu_mes_pipe pipe) 529 { 530 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 531 &adev->mes.data_fw_gpu_addr[pipe], 532 (void **)&adev->mes.data_fw_ptr[pipe]); 533 534 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 535 &adev->mes.ucode_fw_gpu_addr[pipe], 536 (void **)&adev->mes.ucode_fw_ptr[pipe]); 537 } 538 539 static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable) 540 { 541 uint32_t pipe, data = 0; 542 543 if (enable) { 544 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); 545 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 546 data = REG_SET_FIELD(data, CP_MES_CNTL, 547 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 548 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 549 550 mutex_lock(&adev->srbm_mutex); 551 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 552 if (!adev->enable_mes_kiq && 553 pipe == AMDGPU_MES_KIQ_PIPE) 554 continue; 555 556 nv_grbm_select(adev, 3, pipe, 0, 0); 557 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, 558 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); 559 } 560 nv_grbm_select(adev, 0, 0, 0, 0); 561 mutex_unlock(&adev->srbm_mutex); 562 563 /* clear BYPASS_UNCACHED to avoid hangs after interrupt. */ 564 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); 565 data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL, 566 BYPASS_UNCACHED, 0); 567 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); 568 569 /* unhalt MES and activate pipe0 */ 570 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 571 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 572 adev->enable_mes_kiq ? 1 : 0); 573 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 574 udelay(100); 575 } else { 576 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); 577 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 578 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 579 data = REG_SET_FIELD(data, CP_MES_CNTL, 580 MES_INVALIDATE_ICACHE, 1); 581 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 582 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 583 adev->enable_mes_kiq ? 1 : 0); 584 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 585 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 586 } 587 } 588 589 /* This function is for backdoor MES firmware */ 590 static int mes_v10_1_load_microcode(struct amdgpu_device *adev, 591 enum admgpu_mes_pipe pipe) 592 { 593 int r; 594 uint32_t data; 595 596 mes_v10_1_enable(adev, false); 597 598 if (!adev->mes.fw[pipe]) 599 return -EINVAL; 600 601 r = mes_v10_1_allocate_ucode_buffer(adev, pipe); 602 if (r) 603 return r; 604 605 r = mes_v10_1_allocate_ucode_data_buffer(adev, pipe); 606 if (r) { 607 mes_v10_1_free_ucode_buffers(adev, pipe); 608 return r; 609 } 610 611 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); 612 613 mutex_lock(&adev->srbm_mutex); 614 /* me=3, pipe=0, queue=0 */ 615 nv_grbm_select(adev, 3, pipe, 0, 0); 616 617 /* set ucode start address */ 618 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, 619 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); 620 621 /* set ucode fimrware address */ 622 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, 623 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 624 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, 625 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 626 627 /* set ucode instruction cache boundary to 2M-1 */ 628 WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF); 629 630 /* set ucode data firmware address */ 631 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO, 632 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 633 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI, 634 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 635 636 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 637 WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF); 638 639 /* invalidate ICACHE */ 640 switch (adev->ip_versions[GC_HWIP][0]) { 641 case IP_VERSION(10, 3, 0): 642 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); 643 break; 644 default: 645 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); 646 break; 647 } 648 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 649 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 650 switch (adev->ip_versions[GC_HWIP][0]) { 651 case IP_VERSION(10, 3, 0): 652 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data); 653 break; 654 default: 655 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); 656 break; 657 } 658 659 /* prime the ICACHE. */ 660 switch (adev->ip_versions[GC_HWIP][0]) { 661 case IP_VERSION(10, 3, 0): 662 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); 663 break; 664 default: 665 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); 666 break; 667 } 668 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 669 switch (adev->ip_versions[GC_HWIP][0]) { 670 case IP_VERSION(10, 3, 0): 671 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data); 672 break; 673 default: 674 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); 675 break; 676 } 677 678 nv_grbm_select(adev, 0, 0, 0, 0); 679 mutex_unlock(&adev->srbm_mutex); 680 681 return 0; 682 } 683 684 static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev, 685 enum admgpu_mes_pipe pipe) 686 { 687 int r; 688 u32 *eop; 689 690 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 691 AMDGPU_GEM_DOMAIN_GTT, 692 &adev->mes.eop_gpu_obj[pipe], 693 &adev->mes.eop_gpu_addr[pipe], 694 (void **)&eop); 695 if (r) { 696 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 697 return r; 698 } 699 700 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 701 702 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 703 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 704 705 return 0; 706 } 707 708 static int mes_v10_1_mqd_init(struct amdgpu_ring *ring) 709 { 710 struct v10_compute_mqd *mqd = ring->mqd_ptr; 711 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 712 uint32_t tmp; 713 714 mqd->header = 0xC0310800; 715 mqd->compute_pipelinestat_enable = 0x00000001; 716 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 717 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 718 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 719 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 720 mqd->compute_misc_reserved = 0x00000003; 721 722 eop_base_addr = ring->eop_gpu_addr >> 8; 723 724 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 725 tmp = mmCP_HQD_EOP_CONTROL_DEFAULT; 726 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 727 (order_base_2(MES_EOP_SIZE / 4) - 1)); 728 729 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 730 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 731 mqd->cp_hqd_eop_control = tmp; 732 733 /* disable the queue if it's active */ 734 ring->wptr = 0; 735 mqd->cp_hqd_pq_rptr = 0; 736 mqd->cp_hqd_pq_wptr_lo = 0; 737 mqd->cp_hqd_pq_wptr_hi = 0; 738 739 /* set the pointer to the MQD */ 740 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 741 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 742 743 /* set MQD vmid to 0 */ 744 tmp = mmCP_MQD_CONTROL_DEFAULT; 745 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 746 mqd->cp_mqd_control = tmp; 747 748 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 749 hqd_gpu_addr = ring->gpu_addr >> 8; 750 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 751 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 752 753 /* set the wb address whether it's enabled or not */ 754 wb_gpu_addr = ring->rptr_gpu_addr; 755 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 756 mqd->cp_hqd_pq_rptr_report_addr_hi = 757 upper_32_bits(wb_gpu_addr) & 0xffff; 758 759 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 760 wb_gpu_addr = ring->wptr_gpu_addr; 761 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 762 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 763 764 /* set up the HQD, this is similar to CP_RB0_CNTL */ 765 tmp = mmCP_HQD_PQ_CONTROL_DEFAULT; 766 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 767 (order_base_2(ring->ring_size / 4) - 1)); 768 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 769 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 770 #ifdef __BIG_ENDIAN 771 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 772 #endif 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 774 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 778 mqd->cp_hqd_pq_control = tmp; 779 780 /* enable doorbell? */ 781 tmp = 0; 782 if (ring->use_doorbell) { 783 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 784 DOORBELL_OFFSET, ring->doorbell_index); 785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 786 DOORBELL_EN, 1); 787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 788 DOORBELL_SOURCE, 0); 789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 790 DOORBELL_HIT, 0); 791 } 792 else 793 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 794 DOORBELL_EN, 0); 795 mqd->cp_hqd_pq_doorbell_control = tmp; 796 797 mqd->cp_hqd_vmid = 0; 798 /* activate the queue */ 799 mqd->cp_hqd_active = 1; 800 mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT; 801 mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT; 802 mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT; 803 mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT; 804 805 tmp = mmCP_HQD_GFX_CONTROL_DEFAULT; 806 tmp = REG_SET_FIELD(tmp, CP_HQD_GFX_CONTROL, DB_UPDATED_MSG_EN, 1); 807 /* offset: 184 - this is used for CP_HQD_GFX_CONTROL */ 808 mqd->cp_hqd_suspend_cntl_stack_offset = tmp; 809 810 return 0; 811 } 812 813 #if 0 814 static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring) 815 { 816 struct v10_compute_mqd *mqd = ring->mqd_ptr; 817 struct amdgpu_device *adev = ring->adev; 818 uint32_t data = 0; 819 820 mutex_lock(&adev->srbm_mutex); 821 nv_grbm_select(adev, 3, ring->pipe, 0, 0); 822 823 /* set CP_HQD_VMID.VMID = 0. */ 824 data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID); 825 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 826 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data); 827 828 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 829 data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 830 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 831 DOORBELL_EN, 0); 832 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); 833 834 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 835 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 836 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 837 838 /* set CP_MQD_CONTROL.VMID=0 */ 839 data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 840 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 841 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0); 842 843 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 844 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 845 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 846 847 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 848 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 849 mqd->cp_hqd_pq_rptr_report_addr_lo); 850 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 851 mqd->cp_hqd_pq_rptr_report_addr_hi); 852 853 /* set CP_HQD_PQ_CONTROL */ 854 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 855 856 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 857 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 858 mqd->cp_hqd_pq_wptr_poll_addr_lo); 859 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 860 mqd->cp_hqd_pq_wptr_poll_addr_hi); 861 862 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 863 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 864 mqd->cp_hqd_pq_doorbell_control); 865 866 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 867 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 868 869 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 870 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 871 872 nv_grbm_select(adev, 0, 0, 0, 0); 873 mutex_unlock(&adev->srbm_mutex); 874 } 875 #endif 876 877 static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev) 878 { 879 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 880 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 881 int r; 882 883 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 884 return -EINVAL; 885 886 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 887 if (r) { 888 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 889 return r; 890 } 891 892 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 893 894 r = amdgpu_ring_test_ring(kiq_ring); 895 if (r) { 896 DRM_ERROR("kfq enable failed\n"); 897 kiq_ring->sched.ready = false; 898 } 899 900 return r; 901 } 902 903 static int mes_v10_1_queue_init(struct amdgpu_device *adev) 904 { 905 int r; 906 907 r = mes_v10_1_mqd_init(&adev->mes.ring); 908 if (r) 909 return r; 910 911 r = mes_v10_1_kiq_enable_queue(adev); 912 if (r) 913 return r; 914 915 return 0; 916 } 917 918 static int mes_v10_1_ring_init(struct amdgpu_device *adev) 919 { 920 struct amdgpu_ring *ring; 921 922 ring = &adev->mes.ring; 923 924 ring->funcs = &mes_v10_1_ring_funcs; 925 926 ring->me = 3; 927 ring->pipe = 0; 928 ring->queue = 0; 929 930 ring->ring_obj = NULL; 931 ring->use_doorbell = true; 932 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 933 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 934 ring->no_scheduler = true; 935 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 936 937 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 938 AMDGPU_RING_PRIO_DEFAULT, NULL); 939 } 940 941 static int mes_v10_1_kiq_ring_init(struct amdgpu_device *adev) 942 { 943 struct amdgpu_ring *ring; 944 945 spin_lock_init(&adev->gfx.kiq.ring_lock); 946 947 ring = &adev->gfx.kiq.ring; 948 949 ring->me = 3; 950 ring->pipe = 1; 951 ring->queue = 0; 952 953 ring->adev = NULL; 954 ring->ring_obj = NULL; 955 ring->use_doorbell = true; 956 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 957 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 958 ring->no_scheduler = true; 959 sprintf(ring->name, "mes_kiq_%d.%d.%d", 960 ring->me, ring->pipe, ring->queue); 961 962 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 963 AMDGPU_RING_PRIO_DEFAULT, NULL); 964 } 965 966 static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev, 967 enum admgpu_mes_pipe pipe) 968 { 969 int r, mqd_size = sizeof(struct v10_compute_mqd); 970 struct amdgpu_ring *ring; 971 972 if (pipe == AMDGPU_MES_KIQ_PIPE) 973 ring = &adev->gfx.kiq.ring; 974 else if (pipe == AMDGPU_MES_SCHED_PIPE) 975 ring = &adev->mes.ring; 976 else 977 BUG(); 978 979 if (ring->mqd_obj) 980 return 0; 981 982 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 983 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 984 &ring->mqd_gpu_addr, &ring->mqd_ptr); 985 if (r) { 986 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 987 return r; 988 } 989 memset(ring->mqd_ptr, 0, mqd_size); 990 991 /* prepare MQD backup */ 992 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 993 if (!adev->mes.mqd_backup[pipe]) 994 dev_warn(adev->dev, 995 "no memory to create MQD backup for ring %s\n", 996 ring->name); 997 998 return 0; 999 } 1000 1001 static int mes_v10_1_sw_init(void *handle) 1002 { 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004 int pipe, r; 1005 1006 adev->mes.adev = adev; 1007 adev->mes.funcs = &mes_v10_1_funcs; 1008 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; 1009 1010 r = amdgpu_mes_init(adev); 1011 if (r) 1012 return r; 1013 1014 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1015 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1016 continue; 1017 1018 r = mes_v10_1_init_microcode(adev, pipe); 1019 if (r) 1020 return r; 1021 1022 r = mes_v10_1_allocate_eop_buf(adev, pipe); 1023 if (r) 1024 return r; 1025 1026 r = mes_v10_1_mqd_sw_init(adev, pipe); 1027 if (r) 1028 return r; 1029 } 1030 1031 if (adev->enable_mes_kiq) { 1032 r = mes_v10_1_kiq_ring_init(adev); 1033 if (r) 1034 return r; 1035 } 1036 1037 r = mes_v10_1_ring_init(adev); 1038 if (r) 1039 return r; 1040 1041 return 0; 1042 } 1043 1044 static int mes_v10_1_sw_fini(void *handle) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 int pipe; 1048 1049 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1050 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1051 1052 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1053 kfree(adev->mes.mqd_backup[pipe]); 1054 1055 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1056 &adev->mes.eop_gpu_addr[pipe], 1057 NULL); 1058 1059 mes_v10_1_free_microcode(adev, pipe); 1060 } 1061 1062 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1063 &adev->gfx.kiq.ring.mqd_gpu_addr, 1064 &adev->gfx.kiq.ring.mqd_ptr); 1065 1066 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1067 &adev->mes.ring.mqd_gpu_addr, 1068 &adev->mes.ring.mqd_ptr); 1069 1070 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1071 amdgpu_ring_fini(&adev->mes.ring); 1072 1073 amdgpu_mes_fini(adev); 1074 return 0; 1075 } 1076 1077 static void mes_v10_1_kiq_setting(struct amdgpu_ring *ring) 1078 { 1079 uint32_t tmp; 1080 struct amdgpu_device *adev = ring->adev; 1081 1082 /* tell RLC which is KIQ queue */ 1083 switch (adev->ip_versions[GC_HWIP][0]) { 1084 case IP_VERSION(10, 3, 0): 1085 case IP_VERSION(10, 3, 2): 1086 case IP_VERSION(10, 3, 1): 1087 case IP_VERSION(10, 3, 4): 1088 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 1089 tmp &= 0xffffff00; 1090 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1091 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 1092 tmp |= 0x80; 1093 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 1094 break; 1095 default: 1096 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 1097 tmp &= 0xffffff00; 1098 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1099 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 1100 tmp |= 0x80; 1101 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 1102 break; 1103 } 1104 } 1105 1106 static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev) 1107 { 1108 int r = 0; 1109 1110 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1111 r = mes_v10_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE); 1112 if (r) { 1113 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1114 return r; 1115 } 1116 1117 r = mes_v10_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1118 if (r) { 1119 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1120 return r; 1121 } 1122 } 1123 1124 mes_v10_1_enable(adev, true); 1125 1126 mes_v10_1_kiq_setting(&adev->gfx.kiq.ring); 1127 1128 r = mes_v10_1_queue_init(adev); 1129 if (r) 1130 goto failure; 1131 1132 return r; 1133 1134 failure: 1135 mes_v10_1_hw_fini(adev); 1136 return r; 1137 } 1138 1139 static int mes_v10_1_hw_init(void *handle) 1140 { 1141 int r; 1142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1143 1144 if (!adev->enable_mes_kiq) { 1145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1146 r = mes_v10_1_load_microcode(adev, 1147 AMDGPU_MES_SCHED_PIPE); 1148 if (r) { 1149 DRM_ERROR("failed to MES fw, r=%d\n", r); 1150 return r; 1151 } 1152 } 1153 1154 mes_v10_1_enable(adev, true); 1155 } 1156 1157 r = mes_v10_1_queue_init(adev); 1158 if (r) 1159 goto failure; 1160 1161 r = mes_v10_1_set_hw_resources(&adev->mes); 1162 if (r) 1163 goto failure; 1164 1165 mes_v10_1_init_aggregated_doorbell(&adev->mes); 1166 1167 r = mes_v10_1_query_sched_status(&adev->mes); 1168 if (r) { 1169 DRM_ERROR("MES is busy\n"); 1170 goto failure; 1171 } 1172 1173 /* 1174 * Disable KIQ ring usage from the driver once MES is enabled. 1175 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1176 * with MES enabled. 1177 */ 1178 adev->gfx.kiq.ring.sched.ready = false; 1179 adev->mes.ring.sched.ready = true; 1180 1181 return 0; 1182 1183 failure: 1184 mes_v10_1_hw_fini(adev); 1185 return r; 1186 } 1187 1188 static int mes_v10_1_hw_fini(void *handle) 1189 { 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 1192 adev->mes.ring.sched.ready = false; 1193 1194 mes_v10_1_enable(adev, false); 1195 1196 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1197 mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1198 mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1199 } 1200 1201 return 0; 1202 } 1203 1204 static int mes_v10_1_suspend(void *handle) 1205 { 1206 int r; 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 1209 r = amdgpu_mes_suspend(adev); 1210 if (r) 1211 return r; 1212 1213 return mes_v10_1_hw_fini(adev); 1214 } 1215 1216 static int mes_v10_1_resume(void *handle) 1217 { 1218 int r; 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1221 r = mes_v10_1_hw_init(adev); 1222 if (r) 1223 return r; 1224 1225 return amdgpu_mes_resume(adev); 1226 } 1227 1228 static int mes_v10_0_late_init(void *handle) 1229 { 1230 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1231 1232 if (!amdgpu_in_reset(adev)) 1233 amdgpu_mes_self_test(adev); 1234 1235 return 0; 1236 } 1237 1238 static const struct amd_ip_funcs mes_v10_1_ip_funcs = { 1239 .name = "mes_v10_1", 1240 .late_init = mes_v10_0_late_init, 1241 .sw_init = mes_v10_1_sw_init, 1242 .sw_fini = mes_v10_1_sw_fini, 1243 .hw_init = mes_v10_1_hw_init, 1244 .hw_fini = mes_v10_1_hw_fini, 1245 .suspend = mes_v10_1_suspend, 1246 .resume = mes_v10_1_resume, 1247 }; 1248 1249 const struct amdgpu_ip_block_version mes_v10_1_ip_block = { 1250 .type = AMD_IP_BLOCK_TYPE_MES, 1251 .major = 10, 1252 .minor = 1, 1253 .rev = 0, 1254 .funcs = &mes_v10_1_ip_funcs, 1255 }; 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