1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev) 41 { 42 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0); 43 } 44 45 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev) 46 { 47 amdgpu_mca_ras_fini(adev, &adev->mca.mp0); 48 } 49 50 const struct amdgpu_mca_ras_funcs mca_v3_0_mp0_ras_funcs = { 51 .ras_late_init = mca_v3_0_mp0_ras_late_init, 52 .ras_fini = mca_v3_0_mp0_ras_fini, 53 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 54 .query_ras_error_address = NULL, 55 .ras_block = AMDGPU_RAS_BLOCK__MCA, 56 .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP0, 57 .sysfs_name = "mp0_err_count", 58 }; 59 60 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 61 void *ras_error_status) 62 { 63 amdgpu_mca_query_ras_error_count(adev, 64 smnMCMP1_STATUST0, 65 ras_error_status); 66 } 67 68 static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev) 69 { 70 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1); 71 } 72 73 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev) 74 { 75 amdgpu_mca_ras_fini(adev, &adev->mca.mp1); 76 } 77 78 const struct amdgpu_mca_ras_funcs mca_v3_0_mp1_ras_funcs = { 79 .ras_late_init = mca_v3_0_mp1_ras_late_init, 80 .ras_fini = mca_v3_0_mp1_ras_fini, 81 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 82 .query_ras_error_address = NULL, 83 .ras_block = AMDGPU_RAS_BLOCK__MCA, 84 .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP1, 85 .sysfs_name = "mp1_err_count", 86 }; 87 88 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 89 void *ras_error_status) 90 { 91 amdgpu_mca_query_ras_error_count(adev, 92 smnMCMPIO_STATUST0, 93 ras_error_status); 94 } 95 96 static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev) 97 { 98 return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio); 99 } 100 101 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev) 102 { 103 amdgpu_mca_ras_fini(adev, &adev->mca.mpio); 104 } 105 106 const struct amdgpu_mca_ras_funcs mca_v3_0_mpio_ras_funcs = { 107 .ras_late_init = mca_v3_0_mpio_ras_late_init, 108 .ras_fini = mca_v3_0_mpio_ras_fini, 109 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 110 .query_ras_error_address = NULL, 111 .ras_block = AMDGPU_RAS_BLOCK__MCA, 112 .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MPIO, 113 .sysfs_name = "mpio_err_count", 114 }; 115 116 117 static void mca_v3_0_init(struct amdgpu_device *adev) 118 { 119 struct amdgpu_mca *mca = &adev->mca; 120 121 mca->mp0.ras_funcs = &mca_v3_0_mp0_ras_funcs; 122 mca->mp1.ras_funcs = &mca_v3_0_mp1_ras_funcs; 123 mca->mpio.ras_funcs = &mca_v3_0_mpio_ras_funcs; 124 } 125 126 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 127 .init = mca_v3_0_init, 128 };