1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev, void *ras_info) 41 { 42 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0); 43 } 44 45 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev) 46 { 47 amdgpu_mca_ras_fini(adev, &adev->mca.mp0); 48 } 49 50 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object* block_obj, enum amdgpu_ras_block block, uint32_t sub_block_index) 51 { 52 if(!block_obj) 53 return -EINVAL; 54 55 if( (block_obj->block == block) && 56 (block_obj->sub_block_index == sub_block_index)) { 57 return 0; 58 } 59 60 return -EINVAL; 61 } 62 63 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = { 64 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 65 .query_ras_error_address = NULL, 66 }; 67 68 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { 69 .ras_block = { 70 .block = AMDGPU_RAS_BLOCK__MCA, 71 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0, 72 .name = "mp0", 73 .hw_ops = &mca_v3_0_mp0_hw_ops, 74 .ras_block_match = mca_v3_0_ras_block_match, 75 .ras_late_init = mca_v3_0_mp0_ras_late_init, 76 .ras_fini = mca_v3_0_mp0_ras_fini, 77 }, 78 }; 79 80 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 81 void *ras_error_status) 82 { 83 amdgpu_mca_query_ras_error_count(adev, 84 smnMCMP1_STATUST0, 85 ras_error_status); 86 } 87 88 static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev, void *ras_info) 89 { 90 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1); 91 } 92 93 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev) 94 { 95 amdgpu_mca_ras_fini(adev, &adev->mca.mp1); 96 } 97 98 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { 99 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 100 .query_ras_error_address = NULL, 101 }; 102 103 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { 104 .ras_block = { 105 .block = AMDGPU_RAS_BLOCK__MCA, 106 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1, 107 .name = "mp1", 108 .hw_ops = &mca_v3_0_mp1_hw_ops, 109 .ras_block_match = mca_v3_0_ras_block_match, 110 .ras_late_init = mca_v3_0_mp1_ras_late_init, 111 .ras_fini = mca_v3_0_mp1_ras_fini, 112 }, 113 }; 114 115 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 116 void *ras_error_status) 117 { 118 amdgpu_mca_query_ras_error_count(adev, 119 smnMCMPIO_STATUST0, 120 ras_error_status); 121 } 122 123 static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev, void *ras_info) 124 { 125 return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio); 126 } 127 128 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev) 129 { 130 amdgpu_mca_ras_fini(adev, &adev->mca.mpio); 131 } 132 133 const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { 134 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 135 .query_ras_error_address = NULL, 136 }; 137 138 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { 139 .ras_block = { 140 .block = AMDGPU_RAS_BLOCK__MCA, 141 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO, 142 .name = "mpio", 143 .hw_ops = &mca_v3_0_mpio_hw_ops, 144 .ras_block_match = mca_v3_0_ras_block_match, 145 .ras_late_init = mca_v3_0_mpio_ras_late_init, 146 .ras_fini = mca_v3_0_mpio_ras_fini, 147 }, 148 }; 149 150 151 static void mca_v3_0_init(struct amdgpu_device *adev) 152 { 153 struct amdgpu_mca *mca = &adev->mca; 154 155 mca->mp0.ras = &mca_v3_0_mp0_ras; 156 mca->mp1.ras = &mca_v3_0_mp1_ras; 157 mca->mpio.ras = &mca_v3_0_mpio_ras; 158 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); 159 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); 160 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); 161 } 162 163 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 164 .init = mca_v3_0_init, 165 };