1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev, void *ras_info) 41 { 42 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0); 43 } 44 45 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev) 46 { 47 amdgpu_mca_ras_fini(adev, &adev->mca.mp0); 48 } 49 50 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj, 51 enum amdgpu_ras_block block, uint32_t sub_block_index) 52 { 53 if (!block_obj) 54 return -EINVAL; 55 56 if ((block_obj->ras_comm.block == block) && 57 (block_obj->ras_comm.sub_block_index == sub_block_index)) { 58 return 0; 59 } 60 61 return -EINVAL; 62 } 63 64 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = { 65 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 66 .query_ras_error_address = NULL, 67 }; 68 69 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { 70 .ras_block = { 71 .ras_comm = { 72 .block = AMDGPU_RAS_BLOCK__MCA, 73 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0, 74 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 75 .name = "mp0", 76 }, 77 .hw_ops = &mca_v3_0_mp0_hw_ops, 78 .ras_block_match = mca_v3_0_ras_block_match, 79 .ras_late_init = mca_v3_0_mp0_ras_late_init, 80 .ras_fini = mca_v3_0_mp0_ras_fini, 81 }, 82 }; 83 84 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 85 void *ras_error_status) 86 { 87 amdgpu_mca_query_ras_error_count(adev, 88 smnMCMP1_STATUST0, 89 ras_error_status); 90 } 91 92 static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev, void *ras_info) 93 { 94 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1); 95 } 96 97 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev) 98 { 99 amdgpu_mca_ras_fini(adev, &adev->mca.mp1); 100 } 101 102 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { 103 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 104 .query_ras_error_address = NULL, 105 }; 106 107 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { 108 .ras_block = { 109 .ras_comm = { 110 .block = AMDGPU_RAS_BLOCK__MCA, 111 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1, 112 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 113 .name = "mp1", 114 }, 115 .hw_ops = &mca_v3_0_mp1_hw_ops, 116 .ras_block_match = mca_v3_0_ras_block_match, 117 .ras_late_init = mca_v3_0_mp1_ras_late_init, 118 .ras_fini = mca_v3_0_mp1_ras_fini, 119 }, 120 }; 121 122 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 123 void *ras_error_status) 124 { 125 amdgpu_mca_query_ras_error_count(adev, 126 smnMCMPIO_STATUST0, 127 ras_error_status); 128 } 129 130 static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev, void *ras_info) 131 { 132 return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio); 133 } 134 135 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev) 136 { 137 amdgpu_mca_ras_fini(adev, &adev->mca.mpio); 138 } 139 140 const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { 141 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 142 .query_ras_error_address = NULL, 143 }; 144 145 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { 146 .ras_block = { 147 .ras_comm = { 148 .block = AMDGPU_RAS_BLOCK__MCA, 149 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO, 150 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 151 .name = "mpio", 152 }, 153 .hw_ops = &mca_v3_0_mpio_hw_ops, 154 .ras_block_match = mca_v3_0_ras_block_match, 155 .ras_late_init = mca_v3_0_mpio_ras_late_init, 156 .ras_fini = mca_v3_0_mpio_ras_fini, 157 }, 158 }; 159 160 161 static void mca_v3_0_init(struct amdgpu_device *adev) 162 { 163 struct amdgpu_mca *mca = &adev->mca; 164 165 mca->mp0.ras = &mca_v3_0_mp0_ras; 166 mca->mp1.ras = &mca_v3_0_mp1_ras; 167 mca->mpio.ras = &mca_v3_0_mpio_ras; 168 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); 169 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); 170 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); 171 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm; 172 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm; 173 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm; 174 } 175 176 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 177 .init = mca_v3_0_init, 178 };