1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj, 41 enum amdgpu_ras_block block, uint32_t sub_block_index) 42 { 43 if (!block_obj) 44 return -EINVAL; 45 46 if ((block_obj->ras_comm.block == block) && 47 (block_obj->ras_comm.sub_block_index == sub_block_index)) { 48 return 0; 49 } 50 51 return -EINVAL; 52 } 53 54 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = { 55 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 56 .query_ras_error_address = NULL, 57 }; 58 59 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { 60 .ras_block = { 61 .ras_comm = { 62 .block = AMDGPU_RAS_BLOCK__MCA, 63 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0, 64 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 65 .name = "mp0", 66 }, 67 .hw_ops = &mca_v3_0_mp0_hw_ops, 68 .ras_block_match = mca_v3_0_ras_block_match, 69 .ras_fini = amdgpu_ras_block_late_fini, 70 }, 71 }; 72 73 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 74 void *ras_error_status) 75 { 76 amdgpu_mca_query_ras_error_count(adev, 77 smnMCMP1_STATUST0, 78 ras_error_status); 79 } 80 81 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { 82 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 83 .query_ras_error_address = NULL, 84 }; 85 86 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { 87 .ras_block = { 88 .ras_comm = { 89 .block = AMDGPU_RAS_BLOCK__MCA, 90 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1, 91 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 92 .name = "mp1", 93 }, 94 .hw_ops = &mca_v3_0_mp1_hw_ops, 95 .ras_block_match = mca_v3_0_ras_block_match, 96 .ras_fini = amdgpu_ras_block_late_fini, 97 }, 98 }; 99 100 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 101 void *ras_error_status) 102 { 103 amdgpu_mca_query_ras_error_count(adev, 104 smnMCMPIO_STATUST0, 105 ras_error_status); 106 } 107 108 const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { 109 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 110 .query_ras_error_address = NULL, 111 }; 112 113 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { 114 .ras_block = { 115 .ras_comm = { 116 .block = AMDGPU_RAS_BLOCK__MCA, 117 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO, 118 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 119 .name = "mpio", 120 }, 121 .hw_ops = &mca_v3_0_mpio_hw_ops, 122 .ras_block_match = mca_v3_0_ras_block_match, 123 .ras_fini = amdgpu_ras_block_late_fini, 124 }, 125 }; 126 127 128 static void mca_v3_0_init(struct amdgpu_device *adev) 129 { 130 struct amdgpu_mca *mca = &adev->mca; 131 132 mca->mp0.ras = &mca_v3_0_mp0_ras; 133 mca->mp1.ras = &mca_v3_0_mp1_ras; 134 mca->mpio.ras = &mca_v3_0_mpio_ras; 135 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); 136 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); 137 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); 138 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm; 139 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm; 140 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm; 141 } 142 143 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 144 .init = mca_v3_0_init, 145 };