1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block) 41 { 42 amdgpu_mca_ras_fini(adev, &adev->mca.mp0); 43 } 44 45 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj, 46 enum amdgpu_ras_block block, uint32_t sub_block_index) 47 { 48 if (!block_obj) 49 return -EINVAL; 50 51 if ((block_obj->ras_comm.block == block) && 52 (block_obj->ras_comm.sub_block_index == sub_block_index)) { 53 return 0; 54 } 55 56 return -EINVAL; 57 } 58 59 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = { 60 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 61 .query_ras_error_address = NULL, 62 }; 63 64 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { 65 .ras_block = { 66 .ras_comm = { 67 .block = AMDGPU_RAS_BLOCK__MCA, 68 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0, 69 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 70 .name = "mp0", 71 }, 72 .hw_ops = &mca_v3_0_mp0_hw_ops, 73 .ras_block_match = mca_v3_0_ras_block_match, 74 .ras_fini = mca_v3_0_mp0_ras_fini, 75 }, 76 }; 77 78 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 79 void *ras_error_status) 80 { 81 amdgpu_mca_query_ras_error_count(adev, 82 smnMCMP1_STATUST0, 83 ras_error_status); 84 } 85 86 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block) 87 { 88 amdgpu_mca_ras_fini(adev, &adev->mca.mp1); 89 } 90 91 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { 92 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 93 .query_ras_error_address = NULL, 94 }; 95 96 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { 97 .ras_block = { 98 .ras_comm = { 99 .block = AMDGPU_RAS_BLOCK__MCA, 100 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1, 101 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 102 .name = "mp1", 103 }, 104 .hw_ops = &mca_v3_0_mp1_hw_ops, 105 .ras_block_match = mca_v3_0_ras_block_match, 106 .ras_fini = mca_v3_0_mp1_ras_fini, 107 }, 108 }; 109 110 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 111 void *ras_error_status) 112 { 113 amdgpu_mca_query_ras_error_count(adev, 114 smnMCMPIO_STATUST0, 115 ras_error_status); 116 } 117 118 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block) 119 { 120 amdgpu_mca_ras_fini(adev, &adev->mca.mpio); 121 } 122 123 const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { 124 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 125 .query_ras_error_address = NULL, 126 }; 127 128 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { 129 .ras_block = { 130 .ras_comm = { 131 .block = AMDGPU_RAS_BLOCK__MCA, 132 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO, 133 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 134 .name = "mpio", 135 }, 136 .hw_ops = &mca_v3_0_mpio_hw_ops, 137 .ras_block_match = mca_v3_0_ras_block_match, 138 .ras_fini = mca_v3_0_mpio_ras_fini, 139 }, 140 }; 141 142 143 static void mca_v3_0_init(struct amdgpu_device *adev) 144 { 145 struct amdgpu_mca *mca = &adev->mca; 146 147 mca->mp0.ras = &mca_v3_0_mp0_ras; 148 mca->mp1.ras = &mca_v3_0_mp1_ras; 149 mca->mpio.ras = &mca_v3_0_mpio_ras; 150 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); 151 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); 152 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); 153 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm; 154 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm; 155 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm; 156 } 157 158 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 159 .init = mca_v3_0_init, 160 };