1e684e654SJames Zhu /* 2e684e654SJames Zhu * Copyright 2022 Advanced Micro Devices, Inc. 3e684e654SJames Zhu * 4e684e654SJames Zhu * Permission is hereby granted, free of charge, to any person obtaining a 5e684e654SJames Zhu * copy of this software and associated documentation files (the "Software"), 6e684e654SJames Zhu * to deal in the Software without restriction, including without limitation 7e684e654SJames Zhu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e684e654SJames Zhu * and/or sell copies of the Software, and to permit persons to whom the 9e684e654SJames Zhu * Software is furnished to do so, subject to the following conditions: 10e684e654SJames Zhu * 11e684e654SJames Zhu * The above copyright notice and this permission notice shall be included in 12e684e654SJames Zhu * all copies or substantial portions of the Software. 13e684e654SJames Zhu * 14e684e654SJames Zhu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e684e654SJames Zhu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e684e654SJames Zhu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e684e654SJames Zhu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e684e654SJames Zhu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e684e654SJames Zhu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e684e654SJames Zhu * OTHER DEALINGS IN THE SOFTWARE. 21e684e654SJames Zhu * 22e684e654SJames Zhu */ 23e684e654SJames Zhu 24e684e654SJames Zhu #ifndef __JPEG_V4_0_3_H__ 25e684e654SJames Zhu #define __JPEG_V4_0_3_H__ 26e684e654SJames Zhu 27e684e654SJames Zhu #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 28e684e654SJames Zhu #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d 29e684e654SJames Zhu #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e 30e684e654SJames Zhu #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f 31e684e654SJames Zhu #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab 32e684e654SJames Zhu #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac 33e684e654SJames Zhu #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4 34e684e654SJames Zhu #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6 35e684e654SJames Zhu #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6 36e684e654SJames Zhu #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7 37e684e654SJames Zhu #define regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 38e684e654SJames Zhu #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x42d4 39e684e654SJames Zhu #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x42d5 40e684e654SJames Zhu #define regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 41e684e654SJames Zhu #define regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 42e684e654SJames Zhu #define regUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 43e684e654SJames Zhu #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x4043 44db77081fSJames Zhu #define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094 45*2e10ced4SJames Zhu #define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe 46e684e654SJames Zhu 47e684e654SJames Zhu #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 48e684e654SJames Zhu 49e684e654SJames Zhu extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block; 50e684e654SJames Zhu 51e684e654SJames Zhu #endif /* __JPEG_V4_0_3_H__ */ 52