1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v4_0_3.h" 29 #include "mmsch_v4_0_3.h" 30 31 #include "vcn/vcn_4_0_3_offset.h" 32 #include "vcn/vcn_4_0_3_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 34 35 enum jpeg_engin_status { 36 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 37 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 38 }; 39 40 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 41 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 42 static int jpeg_v4_0_3_set_powergating_state(void *handle, 43 enum amd_powergating_state state); 44 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 46 47 static int amdgpu_ih_srcid_jpeg[] = { 48 VCN_4_0__SRCID__JPEG_DECODE, 49 VCN_4_0__SRCID__JPEG1_DECODE, 50 VCN_4_0__SRCID__JPEG2_DECODE, 51 VCN_4_0__SRCID__JPEG3_DECODE, 52 VCN_4_0__SRCID__JPEG4_DECODE, 53 VCN_4_0__SRCID__JPEG5_DECODE, 54 VCN_4_0__SRCID__JPEG6_DECODE, 55 VCN_4_0__SRCID__JPEG7_DECODE 56 }; 57 58 /** 59 * jpeg_v4_0_3_early_init - set function pointers 60 * 61 * @handle: amdgpu_device pointer 62 * 63 * Set ring and irq function pointers 64 */ 65 static int jpeg_v4_0_3_early_init(void *handle) 66 { 67 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 68 69 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 70 71 jpeg_v4_0_3_set_dec_ring_funcs(adev); 72 jpeg_v4_0_3_set_irq_funcs(adev); 73 jpeg_v4_0_3_set_ras_funcs(adev); 74 75 return 0; 76 } 77 78 /** 79 * jpeg_v4_0_3_sw_init - sw init for JPEG block 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Load firmware and sw initialization 84 */ 85 static int jpeg_v4_0_3_sw_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 struct amdgpu_ring *ring; 89 int i, j, r, jpeg_inst; 90 91 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 92 /* JPEG TRAP */ 93 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 94 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 95 if (r) 96 return r; 97 } 98 99 r = amdgpu_jpeg_sw_init(adev); 100 if (r) 101 return r; 102 103 r = amdgpu_jpeg_resume(adev); 104 if (r) 105 return r; 106 107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 108 jpeg_inst = GET_INST(JPEG, i); 109 110 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 111 ring = &adev->jpeg.inst[i].ring_dec[j]; 112 ring->use_doorbell = true; 113 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 114 if (!amdgpu_sriov_vf(adev)) { 115 ring->doorbell_index = 116 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 117 1 + j + 9 * jpeg_inst; 118 } else { 119 if (j < 4) 120 ring->doorbell_index = 121 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 122 4 + j + 32 * jpeg_inst; 123 else 124 ring->doorbell_index = 125 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 126 8 + j + 32 * jpeg_inst; 127 } 128 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 129 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 130 AMDGPU_RING_PRIO_DEFAULT, NULL); 131 if (r) 132 return r; 133 134 adev->jpeg.internal.jpeg_pitch[j] = 135 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 136 adev->jpeg.inst[i].external.jpeg_pitch[j] = 137 SOC15_REG_OFFSET1( 138 JPEG, jpeg_inst, 139 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 140 (j ? (0x40 * j - 0xc80) : 0)); 141 } 142 } 143 144 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 145 r = amdgpu_jpeg_ras_sw_init(adev); 146 if (r) { 147 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 148 return r; 149 } 150 } 151 152 return 0; 153 } 154 155 /** 156 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 157 * 158 * @handle: amdgpu_device pointer 159 * 160 * JPEG suspend and free up sw allocation 161 */ 162 static int jpeg_v4_0_3_sw_fini(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 int r; 166 167 r = amdgpu_jpeg_suspend(adev); 168 if (r) 169 return r; 170 171 r = amdgpu_jpeg_sw_fini(adev); 172 173 return r; 174 } 175 176 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 177 { 178 struct amdgpu_ring *ring; 179 uint64_t ctx_addr; 180 uint32_t param, resp, expected; 181 uint32_t tmp, timeout; 182 183 struct amdgpu_mm_table *table = &adev->virt.mm_table; 184 uint32_t *table_loc; 185 uint32_t table_size; 186 uint32_t size, size_dw, item_offset; 187 uint32_t init_status; 188 int i, j, jpeg_inst; 189 190 struct mmsch_v4_0_cmd_direct_write 191 direct_wt = { {0} }; 192 struct mmsch_v4_0_cmd_end end = { {0} }; 193 struct mmsch_v4_0_3_init_header header; 194 195 direct_wt.cmd_header.command_type = 196 MMSCH_COMMAND__DIRECT_REG_WRITE; 197 end.cmd_header.command_type = 198 MMSCH_COMMAND__END; 199 200 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 201 jpeg_inst = GET_INST(JPEG, i); 202 203 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 204 header.version = MMSCH_VERSION; 205 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 206 207 table_loc = (uint32_t *)table->cpu_addr; 208 table_loc += header.total_size; 209 210 item_offset = header.total_size; 211 212 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 213 ring = &adev->jpeg.inst[i].ring_dec[j]; 214 table_size = 0; 215 216 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 217 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 218 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 219 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 220 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 221 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 222 223 if (j <= 3) { 224 header.mjpegdec0[j].table_offset = item_offset; 225 header.mjpegdec0[j].init_status = 0; 226 header.mjpegdec0[j].table_size = table_size; 227 } else { 228 header.mjpegdec1[j - 4].table_offset = item_offset; 229 header.mjpegdec1[j - 4].init_status = 0; 230 header.mjpegdec1[j - 4].table_size = table_size; 231 } 232 header.total_size += table_size; 233 item_offset += table_size; 234 } 235 236 MMSCH_V4_0_INSERT_END(); 237 238 /* send init table to MMSCH */ 239 size = sizeof(struct mmsch_v4_0_3_init_header); 240 table_loc = (uint32_t *)table->cpu_addr; 241 memcpy((void *)table_loc, &header, size); 242 243 ctx_addr = table->gpu_addr; 244 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 245 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 246 247 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 248 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 249 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 250 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 251 252 size = header.total_size; 253 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 254 255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 256 257 param = 0x00000001; 258 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 259 tmp = 0; 260 timeout = 1000; 261 resp = 0; 262 expected = MMSCH_VF_MAILBOX_RESP__OK; 263 init_status = 264 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 265 while (resp != expected) { 266 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 267 268 if (resp != 0) 269 break; 270 udelay(10); 271 tmp = tmp + 10; 272 if (tmp >= timeout) { 273 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 274 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 275 "(expected=0x%08x, readback=0x%08x)\n", 276 tmp, expected, resp); 277 return -EBUSY; 278 } 279 } 280 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 281 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 282 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 283 resp, init_status); 284 285 } 286 return 0; 287 } 288 289 /** 290 * jpeg_v4_0_3_hw_init - start and test JPEG block 291 * 292 * @handle: amdgpu_device pointer 293 * 294 */ 295 static int jpeg_v4_0_3_hw_init(void *handle) 296 { 297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 298 struct amdgpu_ring *ring; 299 int i, j, r, jpeg_inst; 300 301 if (amdgpu_sriov_vf(adev)) { 302 r = jpeg_v4_0_3_start_sriov(adev); 303 if (r) 304 return r; 305 306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 307 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 308 ring = &adev->jpeg.inst[i].ring_dec[j]; 309 ring->wptr = 0; 310 ring->wptr_old = 0; 311 jpeg_v4_0_3_dec_ring_set_wptr(ring); 312 ring->sched.ready = true; 313 } 314 } 315 } else { 316 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 317 jpeg_inst = GET_INST(JPEG, i); 318 319 ring = adev->jpeg.inst[i].ring_dec; 320 321 if (ring->use_doorbell) 322 adev->nbio.funcs->vcn_doorbell_range( 323 adev, ring->use_doorbell, 324 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 325 9 * jpeg_inst, 326 adev->jpeg.inst[i].aid_id); 327 328 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 329 ring = &adev->jpeg.inst[i].ring_dec[j]; 330 if (ring->use_doorbell) 331 WREG32_SOC15_OFFSET( 332 VCN, GET_INST(VCN, i), 333 regVCN_JPEG_DB_CTRL, 334 (ring->pipe ? (ring->pipe - 0x15) : 0), 335 ring->doorbell_index 336 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 337 VCN_JPEG_DB_CTRL__EN_MASK); 338 r = amdgpu_ring_test_helper(ring); 339 if (r) 340 return r; 341 } 342 } 343 } 344 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); 345 346 return 0; 347 } 348 349 /** 350 * jpeg_v4_0_3_hw_fini - stop the hardware block 351 * 352 * @handle: amdgpu_device pointer 353 * 354 * Stop the JPEG block, mark ring as not ready any more 355 */ 356 static int jpeg_v4_0_3_hw_fini(void *handle) 357 { 358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 359 int ret = 0; 360 361 cancel_delayed_work_sync(&adev->jpeg.idle_work); 362 363 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 364 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 365 366 return ret; 367 } 368 369 /** 370 * jpeg_v4_0_3_suspend - suspend JPEG block 371 * 372 * @handle: amdgpu_device pointer 373 * 374 * HW fini and suspend JPEG block 375 */ 376 static int jpeg_v4_0_3_suspend(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 int r; 380 381 r = jpeg_v4_0_3_hw_fini(adev); 382 if (r) 383 return r; 384 385 r = amdgpu_jpeg_suspend(adev); 386 387 return r; 388 } 389 390 /** 391 * jpeg_v4_0_3_resume - resume JPEG block 392 * 393 * @handle: amdgpu_device pointer 394 * 395 * Resume firmware and hw init JPEG block 396 */ 397 static int jpeg_v4_0_3_resume(void *handle) 398 { 399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 400 int r; 401 402 r = amdgpu_jpeg_resume(adev); 403 if (r) 404 return r; 405 406 r = jpeg_v4_0_3_hw_init(adev); 407 408 return r; 409 } 410 411 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 412 { 413 int i, jpeg_inst; 414 uint32_t data; 415 416 jpeg_inst = GET_INST(JPEG, inst_idx); 417 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 418 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 419 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 420 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 421 } else { 422 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 423 } 424 425 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 426 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 427 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 428 429 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 430 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 431 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 432 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 433 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 434 } 435 436 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 437 { 438 int i, jpeg_inst; 439 uint32_t data; 440 441 jpeg_inst = GET_INST(JPEG, inst_idx); 442 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 443 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 444 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 445 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 446 } else { 447 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 448 } 449 450 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 451 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 452 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 453 454 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 455 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 456 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 457 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 458 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 459 } 460 461 /** 462 * jpeg_v4_0_3_start - start JPEG block 463 * 464 * @adev: amdgpu_device pointer 465 * 466 * Setup and start the JPEG block 467 */ 468 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 469 { 470 struct amdgpu_ring *ring; 471 int i, j, jpeg_inst; 472 473 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 474 jpeg_inst = GET_INST(JPEG, i); 475 476 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 477 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 478 SOC15_WAIT_ON_RREG( 479 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 480 UVD_PGFSM_STATUS__UVDJ_PWR_ON 481 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 482 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 483 484 /* disable anti hang mechanism */ 485 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 486 regUVD_JPEG_POWER_STATUS), 487 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 488 489 /* JPEG disable CGC */ 490 jpeg_v4_0_3_disable_clock_gating(adev, i); 491 492 /* MJPEG global tiling registers */ 493 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 494 adev->gfx.config.gb_addr_config); 495 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 496 adev->gfx.config.gb_addr_config); 497 498 /* enable JMI channel */ 499 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 500 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 501 502 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 503 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 504 505 ring = &adev->jpeg.inst[i].ring_dec[j]; 506 507 /* enable System Interrupt for JRBC */ 508 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 509 regJPEG_SYS_INT_EN), 510 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 511 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 512 513 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 514 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 515 reg_offset, 0); 516 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 517 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 518 reg_offset, 519 (0x00000001L | 0x00000002L)); 520 WREG32_SOC15_OFFSET( 521 JPEG, jpeg_inst, 522 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 523 reg_offset, lower_32_bits(ring->gpu_addr)); 524 WREG32_SOC15_OFFSET( 525 JPEG, jpeg_inst, 526 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 527 reg_offset, upper_32_bits(ring->gpu_addr)); 528 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 529 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 530 reg_offset, 0); 531 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 532 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 533 reg_offset, 0); 534 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 535 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 536 reg_offset, 0x00000002L); 537 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 538 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 539 reg_offset, ring->ring_size / 4); 540 ring->wptr = RREG32_SOC15_OFFSET( 541 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 542 reg_offset); 543 } 544 } 545 546 return 0; 547 } 548 549 /** 550 * jpeg_v4_0_3_stop - stop JPEG block 551 * 552 * @adev: amdgpu_device pointer 553 * 554 * stop the JPEG block 555 */ 556 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 557 { 558 int i, jpeg_inst; 559 560 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 561 jpeg_inst = GET_INST(JPEG, i); 562 /* reset JMI */ 563 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 564 UVD_JMI_CNTL__SOFT_RESET_MASK, 565 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 566 567 jpeg_v4_0_3_enable_clock_gating(adev, i); 568 569 /* enable anti hang mechanism */ 570 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 571 regUVD_JPEG_POWER_STATUS), 572 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 573 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 574 575 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 576 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 577 SOC15_WAIT_ON_RREG( 578 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 579 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 580 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 581 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 582 } 583 584 return 0; 585 } 586 587 /** 588 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 589 * 590 * @ring: amdgpu_ring pointer 591 * 592 * Returns the current hardware read pointer 593 */ 594 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 595 { 596 struct amdgpu_device *adev = ring->adev; 597 598 return RREG32_SOC15_OFFSET( 599 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 600 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 601 } 602 603 /** 604 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 605 * 606 * @ring: amdgpu_ring pointer 607 * 608 * Returns the current hardware write pointer 609 */ 610 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 611 { 612 struct amdgpu_device *adev = ring->adev; 613 614 if (ring->use_doorbell) 615 return adev->wb.wb[ring->wptr_offs]; 616 else 617 return RREG32_SOC15_OFFSET( 618 JPEG, GET_INST(JPEG, ring->me), 619 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 620 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 621 } 622 623 /** 624 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 625 * 626 * @ring: amdgpu_ring pointer 627 * 628 * Commits the write pointer to the hardware 629 */ 630 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 631 { 632 struct amdgpu_device *adev = ring->adev; 633 634 if (ring->use_doorbell) { 635 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 636 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 637 } else { 638 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 639 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 640 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 641 0), 642 lower_32_bits(ring->wptr)); 643 } 644 } 645 646 /** 647 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 648 * 649 * @ring: amdgpu_ring pointer 650 * 651 * Write a start command to the ring. 652 */ 653 static void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 654 { 655 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 656 0, 0, PACKETJ_TYPE0)); 657 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 658 659 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 660 0, 0, PACKETJ_TYPE0)); 661 amdgpu_ring_write(ring, 0x80004000); 662 } 663 664 /** 665 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 666 * 667 * @ring: amdgpu_ring pointer 668 * 669 * Write a end command to the ring. 670 */ 671 static void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 672 { 673 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 674 0, 0, PACKETJ_TYPE0)); 675 amdgpu_ring_write(ring, 0x62a04); 676 677 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 678 0, 0, PACKETJ_TYPE0)); 679 amdgpu_ring_write(ring, 0x00004000); 680 } 681 682 /** 683 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 684 * 685 * @ring: amdgpu_ring pointer 686 * @addr: address 687 * @seq: sequence number 688 * @flags: fence related flags 689 * 690 * Write a fence and a trap command to the ring. 691 */ 692 static void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 693 unsigned int flags) 694 { 695 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 696 697 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 698 0, 0, PACKETJ_TYPE0)); 699 amdgpu_ring_write(ring, seq); 700 701 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 702 0, 0, PACKETJ_TYPE0)); 703 amdgpu_ring_write(ring, seq); 704 705 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 706 0, 0, PACKETJ_TYPE0)); 707 amdgpu_ring_write(ring, lower_32_bits(addr)); 708 709 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 710 0, 0, PACKETJ_TYPE0)); 711 amdgpu_ring_write(ring, upper_32_bits(addr)); 712 713 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 714 0, 0, PACKETJ_TYPE0)); 715 amdgpu_ring_write(ring, 0x8); 716 717 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 718 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 719 amdgpu_ring_write(ring, 0); 720 721 if (ring->adev->jpeg.inst[ring->me].aid_id) { 722 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 723 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 724 amdgpu_ring_write(ring, 0x4); 725 } else { 726 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 727 amdgpu_ring_write(ring, 0); 728 } 729 730 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 731 0, 0, PACKETJ_TYPE0)); 732 amdgpu_ring_write(ring, 0x3fbc); 733 734 if (ring->adev->jpeg.inst[ring->me].aid_id) { 735 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 736 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 737 amdgpu_ring_write(ring, 0x0); 738 } else { 739 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 740 amdgpu_ring_write(ring, 0); 741 } 742 743 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 744 0, 0, PACKETJ_TYPE0)); 745 amdgpu_ring_write(ring, 0x1); 746 747 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 748 amdgpu_ring_write(ring, 0); 749 } 750 751 /** 752 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 753 * 754 * @ring: amdgpu_ring pointer 755 * @job: job to retrieve vmid from 756 * @ib: indirect buffer to execute 757 * @flags: unused 758 * 759 * Write ring commands to execute the indirect buffer. 760 */ 761 static void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 762 struct amdgpu_job *job, 763 struct amdgpu_ib *ib, 764 uint32_t flags) 765 { 766 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 767 768 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 769 0, 0, PACKETJ_TYPE0)); 770 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 771 772 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 773 0, 0, PACKETJ_TYPE0)); 774 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 775 776 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 777 0, 0, PACKETJ_TYPE0)); 778 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 779 780 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 781 0, 0, PACKETJ_TYPE0)); 782 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 783 784 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 785 0, 0, PACKETJ_TYPE0)); 786 amdgpu_ring_write(ring, ib->length_dw); 787 788 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 789 0, 0, PACKETJ_TYPE0)); 790 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 791 792 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 793 0, 0, PACKETJ_TYPE0)); 794 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 795 796 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 797 amdgpu_ring_write(ring, 0); 798 799 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 800 0, 0, PACKETJ_TYPE0)); 801 amdgpu_ring_write(ring, 0x01400200); 802 803 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 804 0, 0, PACKETJ_TYPE0)); 805 amdgpu_ring_write(ring, 0x2); 806 807 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 808 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 809 amdgpu_ring_write(ring, 0x2); 810 } 811 812 static void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 813 uint32_t val, uint32_t mask) 814 { 815 uint32_t reg_offset = (reg << 2); 816 817 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 818 0, 0, PACKETJ_TYPE0)); 819 amdgpu_ring_write(ring, 0x01400200); 820 821 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 822 0, 0, PACKETJ_TYPE0)); 823 amdgpu_ring_write(ring, val); 824 825 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 826 0, 0, PACKETJ_TYPE0)); 827 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 828 amdgpu_ring_write(ring, 0); 829 amdgpu_ring_write(ring, 830 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 831 } else { 832 amdgpu_ring_write(ring, reg_offset); 833 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 834 0, 0, PACKETJ_TYPE3)); 835 } 836 amdgpu_ring_write(ring, mask); 837 } 838 839 static void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 840 unsigned int vmid, uint64_t pd_addr) 841 { 842 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 843 uint32_t data0, data1, mask; 844 845 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 846 847 /* wait for register write */ 848 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 849 data1 = lower_32_bits(pd_addr); 850 mask = 0xffffffff; 851 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 852 } 853 854 static void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 855 { 856 uint32_t reg_offset = (reg << 2); 857 858 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 859 0, 0, PACKETJ_TYPE0)); 860 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 861 amdgpu_ring_write(ring, 0); 862 amdgpu_ring_write(ring, 863 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 864 } else { 865 amdgpu_ring_write(ring, reg_offset); 866 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 867 0, 0, PACKETJ_TYPE0)); 868 } 869 amdgpu_ring_write(ring, val); 870 } 871 872 static void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 873 { 874 int i; 875 876 WARN_ON(ring->wptr % 2 || count % 2); 877 878 for (i = 0; i < count / 2; i++) { 879 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 880 amdgpu_ring_write(ring, 0); 881 } 882 } 883 884 static bool jpeg_v4_0_3_is_idle(void *handle) 885 { 886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 887 bool ret = false; 888 int i, j; 889 890 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 891 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 892 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 893 894 ret &= ((RREG32_SOC15_OFFSET( 895 JPEG, GET_INST(JPEG, i), 896 regUVD_JRBC0_UVD_JRBC_STATUS, 897 reg_offset) & 898 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 899 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 900 } 901 } 902 903 return ret; 904 } 905 906 static int jpeg_v4_0_3_wait_for_idle(void *handle) 907 { 908 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 909 int ret = 0; 910 int i, j; 911 912 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 913 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 914 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 915 916 ret &= SOC15_WAIT_ON_RREG_OFFSET( 917 JPEG, GET_INST(JPEG, i), 918 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 919 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 920 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 921 } 922 } 923 return ret; 924 } 925 926 static int jpeg_v4_0_3_set_clockgating_state(void *handle, 927 enum amd_clockgating_state state) 928 { 929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 930 bool enable = state == AMD_CG_STATE_GATE; 931 int i; 932 933 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 934 if (enable) { 935 if (!jpeg_v4_0_3_is_idle(handle)) 936 return -EBUSY; 937 jpeg_v4_0_3_enable_clock_gating(adev, i); 938 } else { 939 jpeg_v4_0_3_disable_clock_gating(adev, i); 940 } 941 } 942 return 0; 943 } 944 945 static int jpeg_v4_0_3_set_powergating_state(void *handle, 946 enum amd_powergating_state state) 947 { 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 int ret; 950 951 if (state == adev->jpeg.cur_state) 952 return 0; 953 954 if (state == AMD_PG_STATE_GATE) 955 ret = jpeg_v4_0_3_stop(adev); 956 else 957 ret = jpeg_v4_0_3_start(adev); 958 959 if (!ret) 960 adev->jpeg.cur_state = state; 961 962 return ret; 963 } 964 965 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 966 struct amdgpu_irq_src *source, 967 unsigned int type, 968 enum amdgpu_interrupt_state state) 969 { 970 return 0; 971 } 972 973 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 974 struct amdgpu_irq_src *source, 975 struct amdgpu_iv_entry *entry) 976 { 977 uint32_t i, inst; 978 979 i = node_id_to_phys_map[entry->node_id]; 980 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 981 982 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 983 if (adev->jpeg.inst[inst].aid_id == i) 984 break; 985 986 if (inst >= adev->jpeg.num_jpeg_inst) { 987 dev_WARN_ONCE(adev->dev, 1, 988 "Interrupt received for unknown JPEG instance %d", 989 entry->node_id); 990 return 0; 991 } 992 993 switch (entry->src_id) { 994 case VCN_4_0__SRCID__JPEG_DECODE: 995 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 996 break; 997 case VCN_4_0__SRCID__JPEG1_DECODE: 998 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 999 break; 1000 case VCN_4_0__SRCID__JPEG2_DECODE: 1001 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1002 break; 1003 case VCN_4_0__SRCID__JPEG3_DECODE: 1004 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1005 break; 1006 case VCN_4_0__SRCID__JPEG4_DECODE: 1007 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1008 break; 1009 case VCN_4_0__SRCID__JPEG5_DECODE: 1010 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1011 break; 1012 case VCN_4_0__SRCID__JPEG6_DECODE: 1013 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1014 break; 1015 case VCN_4_0__SRCID__JPEG7_DECODE: 1016 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1017 break; 1018 default: 1019 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1020 entry->src_id, entry->src_data[0]); 1021 break; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1028 .name = "jpeg_v4_0_3", 1029 .early_init = jpeg_v4_0_3_early_init, 1030 .late_init = NULL, 1031 .sw_init = jpeg_v4_0_3_sw_init, 1032 .sw_fini = jpeg_v4_0_3_sw_fini, 1033 .hw_init = jpeg_v4_0_3_hw_init, 1034 .hw_fini = jpeg_v4_0_3_hw_fini, 1035 .suspend = jpeg_v4_0_3_suspend, 1036 .resume = jpeg_v4_0_3_resume, 1037 .is_idle = jpeg_v4_0_3_is_idle, 1038 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1039 .check_soft_reset = NULL, 1040 .pre_soft_reset = NULL, 1041 .soft_reset = NULL, 1042 .post_soft_reset = NULL, 1043 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1044 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1045 }; 1046 1047 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1048 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1049 .align_mask = 0xf, 1050 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1051 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1052 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1053 .emit_frame_size = 1054 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1055 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1056 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1057 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1058 8 + 16, 1059 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1060 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1061 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1062 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1063 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1064 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1065 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1066 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1067 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1068 .pad_ib = amdgpu_ring_generic_pad_ib, 1069 .begin_use = amdgpu_jpeg_ring_begin_use, 1070 .end_use = amdgpu_jpeg_ring_end_use, 1071 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1072 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1073 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1074 }; 1075 1076 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1077 { 1078 int i, j, jpeg_inst; 1079 1080 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1081 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1082 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1083 adev->jpeg.inst[i].ring_dec[j].me = i; 1084 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1085 } 1086 jpeg_inst = GET_INST(JPEG, i); 1087 adev->jpeg.inst[i].aid_id = 1088 jpeg_inst / adev->jpeg.num_inst_per_aid; 1089 } 1090 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); 1091 } 1092 1093 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1094 .set = jpeg_v4_0_3_set_interrupt_state, 1095 .process = jpeg_v4_0_3_process_interrupt, 1096 }; 1097 1098 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1099 { 1100 int i; 1101 1102 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1103 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1104 } 1105 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1106 } 1107 1108 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1109 .type = AMD_IP_BLOCK_TYPE_JPEG, 1110 .major = 4, 1111 .minor = 0, 1112 .rev = 3, 1113 .funcs = &jpeg_v4_0_3_ip_funcs, 1114 }; 1115 1116 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1117 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1118 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1119 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1120 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1121 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1122 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1123 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1124 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1125 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1126 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1127 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1128 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1129 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1130 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1131 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1132 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1133 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1134 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1135 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1136 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1137 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1138 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1139 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1140 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1141 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1142 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1143 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1144 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1145 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1146 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1147 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1148 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1149 }; 1150 1151 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1152 uint32_t jpeg_inst, 1153 void *ras_err_status) 1154 { 1155 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1156 1157 /* jpeg v4_0_3 only support uncorrectable errors */ 1158 amdgpu_ras_inst_query_ras_error_count(adev, 1159 jpeg_v4_0_3_ue_reg_list, 1160 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1161 NULL, 0, GET_INST(VCN, jpeg_inst), 1162 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1163 &err_data->ue_count); 1164 } 1165 1166 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1167 void *ras_err_status) 1168 { 1169 uint32_t i; 1170 1171 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1172 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1173 return; 1174 } 1175 1176 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1177 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1178 } 1179 1180 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1181 uint32_t jpeg_inst) 1182 { 1183 amdgpu_ras_inst_reset_ras_error_count(adev, 1184 jpeg_v4_0_3_ue_reg_list, 1185 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1186 GET_INST(VCN, jpeg_inst)); 1187 } 1188 1189 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1190 { 1191 uint32_t i; 1192 1193 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1194 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1195 return; 1196 } 1197 1198 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1199 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1200 } 1201 1202 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1203 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1204 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1205 }; 1206 1207 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1208 .ras_block = { 1209 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1210 }, 1211 }; 1212 1213 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1214 { 1215 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1216 } 1217