1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 32 #include "vcn/vcn_4_0_0_offset.h" 33 #include "vcn/vcn_4_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 37 38 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v4_0_set_powergating_state(void *handle, 41 enum amd_powergating_state state); 42 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 43 44 /** 45 * jpeg_v4_0_early_init - set function pointers 46 * 47 * @handle: amdgpu_device pointer 48 * 49 * Set ring and irq function pointers 50 */ 51 static int jpeg_v4_0_early_init(void *handle) 52 { 53 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 54 55 56 adev->jpeg.num_jpeg_inst = 1; 57 58 jpeg_v4_0_set_dec_ring_funcs(adev); 59 jpeg_v4_0_set_irq_funcs(adev); 60 jpeg_v4_0_set_ras_funcs(adev); 61 62 return 0; 63 } 64 65 /** 66 * jpeg_v4_0_sw_init - sw init for JPEG block 67 * 68 * @handle: amdgpu_device pointer 69 * 70 * Load firmware and sw initialization 71 */ 72 static int jpeg_v4_0_sw_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct amdgpu_ring *ring; 76 int r; 77 78 /* JPEG TRAP */ 79 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 80 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 81 if (r) 82 return r; 83 84 /* JPEG DJPEG POISON EVENT */ 85 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 86 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq); 87 if (r) 88 return r; 89 90 /* JPEG EJPEG POISON EVENT */ 91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 92 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq); 93 if (r) 94 return r; 95 96 r = amdgpu_jpeg_sw_init(adev); 97 if (r) 98 return r; 99 100 r = amdgpu_jpeg_resume(adev); 101 if (r) 102 return r; 103 104 ring = &adev->jpeg.inst->ring_dec; 105 ring->use_doorbell = true; 106 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 107 sprintf(ring->name, "jpeg_dec"); 108 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 109 AMDGPU_RING_PRIO_DEFAULT, NULL); 110 if (r) 111 return r; 112 113 adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 114 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 115 116 r = amdgpu_jpeg_ras_sw_init(adev); 117 if (r) 118 return r; 119 120 return 0; 121 } 122 123 /** 124 * jpeg_v4_0_sw_fini - sw fini for JPEG block 125 * 126 * @handle: amdgpu_device pointer 127 * 128 * JPEG suspend and free up sw allocation 129 */ 130 static int jpeg_v4_0_sw_fini(void *handle) 131 { 132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 133 int r; 134 135 r = amdgpu_jpeg_suspend(adev); 136 if (r) 137 return r; 138 139 r = amdgpu_jpeg_sw_fini(adev); 140 141 return r; 142 } 143 144 /** 145 * jpeg_v4_0_hw_init - start and test JPEG block 146 * 147 * @handle: amdgpu_device pointer 148 * 149 */ 150 static int jpeg_v4_0_hw_init(void *handle) 151 { 152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 154 int r; 155 156 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 157 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 158 159 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 160 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 161 VCN_JPEG_DB_CTRL__EN_MASK); 162 163 r = amdgpu_ring_test_helper(ring); 164 if (r) 165 return r; 166 167 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); 168 169 return 0; 170 } 171 172 /** 173 * jpeg_v4_0_hw_fini - stop the hardware block 174 * 175 * @handle: amdgpu_device pointer 176 * 177 * Stop the JPEG block, mark ring as not ready any more 178 */ 179 static int jpeg_v4_0_hw_fini(void *handle) 180 { 181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 182 183 cancel_delayed_work_sync(&adev->vcn.idle_work); 184 185 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 186 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 187 jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 188 189 amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0); 190 191 return 0; 192 } 193 194 /** 195 * jpeg_v4_0_suspend - suspend JPEG block 196 * 197 * @handle: amdgpu_device pointer 198 * 199 * HW fini and suspend JPEG block 200 */ 201 static int jpeg_v4_0_suspend(void *handle) 202 { 203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 204 int r; 205 206 r = jpeg_v4_0_hw_fini(adev); 207 if (r) 208 return r; 209 210 r = amdgpu_jpeg_suspend(adev); 211 212 return r; 213 } 214 215 /** 216 * jpeg_v4_0_resume - resume JPEG block 217 * 218 * @handle: amdgpu_device pointer 219 * 220 * Resume firmware and hw init JPEG block 221 */ 222 static int jpeg_v4_0_resume(void *handle) 223 { 224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 int r; 226 227 r = amdgpu_jpeg_resume(adev); 228 if (r) 229 return r; 230 231 r = jpeg_v4_0_hw_init(adev); 232 233 return r; 234 } 235 236 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 237 { 238 uint32_t data = 0; 239 240 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 241 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 242 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 243 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 244 } else { 245 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 246 } 247 248 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 249 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 250 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 251 252 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 253 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 254 | JPEG_CGC_GATE__JPEG2_DEC_MASK 255 | JPEG_CGC_GATE__JMCIF_MASK 256 | JPEG_CGC_GATE__JRBBM_MASK); 257 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 258 } 259 260 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 261 { 262 uint32_t data = 0; 263 264 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 265 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 266 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 267 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 268 } else { 269 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 270 } 271 272 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 273 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 274 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 275 276 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 277 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 278 |JPEG_CGC_GATE__JPEG2_DEC_MASK 279 |JPEG_CGC_GATE__JMCIF_MASK 280 |JPEG_CGC_GATE__JRBBM_MASK); 281 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 282 } 283 284 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 285 { 286 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 287 uint32_t data = 0; 288 int r = 0; 289 290 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 291 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 292 293 r = SOC15_WAIT_ON_RREG(JPEG, 0, 294 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 295 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 296 297 if (r) { 298 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 299 return r; 300 } 301 } 302 303 /* disable anti hang mechanism */ 304 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 305 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 306 307 /* keep the JPEG in static PG mode */ 308 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 309 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 310 311 return 0; 312 } 313 314 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 315 { 316 /* enable anti hang mechanism */ 317 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 318 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 319 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 320 321 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 322 uint32_t data = 0; 323 int r = 0; 324 325 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 326 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 327 328 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 329 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 330 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 331 332 if (r) { 333 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 334 return r; 335 } 336 } 337 338 return 0; 339 } 340 341 /** 342 * jpeg_v4_0_start - start JPEG block 343 * 344 * @adev: amdgpu_device pointer 345 * 346 * Setup and start the JPEG block 347 */ 348 static int jpeg_v4_0_start(struct amdgpu_device *adev) 349 { 350 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 351 int r; 352 353 if (adev->pm.dpm_enabled) 354 amdgpu_dpm_enable_jpeg(adev, true); 355 356 /* disable power gating */ 357 r = jpeg_v4_0_disable_static_power_gating(adev); 358 if (r) 359 return r; 360 361 /* JPEG disable CGC */ 362 jpeg_v4_0_disable_clock_gating(adev); 363 364 /* MJPEG global tiling registers */ 365 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 366 adev->gfx.config.gb_addr_config); 367 368 369 /* enable JMI channel */ 370 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 371 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 372 373 /* enable System Interrupt for JRBC */ 374 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 375 JPEG_SYS_INT_EN__DJRBC_MASK, 376 ~JPEG_SYS_INT_EN__DJRBC_MASK); 377 378 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 379 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 380 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 381 lower_32_bits(ring->gpu_addr)); 382 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 383 upper_32_bits(ring->gpu_addr)); 384 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 385 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 386 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 387 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 388 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 389 390 return 0; 391 } 392 393 /** 394 * jpeg_v4_0_stop - stop JPEG block 395 * 396 * @adev: amdgpu_device pointer 397 * 398 * stop the JPEG block 399 */ 400 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 401 { 402 int r; 403 404 /* reset JMI */ 405 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 406 UVD_JMI_CNTL__SOFT_RESET_MASK, 407 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 408 409 jpeg_v4_0_enable_clock_gating(adev); 410 411 /* enable power gating */ 412 r = jpeg_v4_0_enable_static_power_gating(adev); 413 if (r) 414 return r; 415 416 if (adev->pm.dpm_enabled) 417 amdgpu_dpm_enable_jpeg(adev, false); 418 419 return 0; 420 } 421 422 /** 423 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 424 * 425 * @ring: amdgpu_ring pointer 426 * 427 * Returns the current hardware read pointer 428 */ 429 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 430 { 431 struct amdgpu_device *adev = ring->adev; 432 433 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 434 } 435 436 /** 437 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 438 * 439 * @ring: amdgpu_ring pointer 440 * 441 * Returns the current hardware write pointer 442 */ 443 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 444 { 445 struct amdgpu_device *adev = ring->adev; 446 447 if (ring->use_doorbell) 448 return *ring->wptr_cpu_addr; 449 else 450 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 451 } 452 453 /** 454 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 455 * 456 * @ring: amdgpu_ring pointer 457 * 458 * Commits the write pointer to the hardware 459 */ 460 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 461 { 462 struct amdgpu_device *adev = ring->adev; 463 464 if (ring->use_doorbell) { 465 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 466 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 467 } else { 468 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 469 } 470 } 471 472 static bool jpeg_v4_0_is_idle(void *handle) 473 { 474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 475 int ret = 1; 476 477 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 478 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 479 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 480 481 return ret; 482 } 483 484 static int jpeg_v4_0_wait_for_idle(void *handle) 485 { 486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 487 488 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 489 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 490 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 491 } 492 493 static int jpeg_v4_0_set_clockgating_state(void *handle, 494 enum amd_clockgating_state state) 495 { 496 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 497 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 498 499 if (enable) { 500 if (!jpeg_v4_0_is_idle(handle)) 501 return -EBUSY; 502 jpeg_v4_0_enable_clock_gating(adev); 503 } else { 504 jpeg_v4_0_disable_clock_gating(adev); 505 } 506 507 return 0; 508 } 509 510 static int jpeg_v4_0_set_powergating_state(void *handle, 511 enum amd_powergating_state state) 512 { 513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 514 int ret; 515 516 if (state == adev->jpeg.cur_state) 517 return 0; 518 519 if (state == AMD_PG_STATE_GATE) 520 ret = jpeg_v4_0_stop(adev); 521 else 522 ret = jpeg_v4_0_start(adev); 523 524 if (!ret) 525 adev->jpeg.cur_state = state; 526 527 return ret; 528 } 529 530 static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev, 531 struct amdgpu_irq_src *source, 532 unsigned type, 533 enum amdgpu_interrupt_state state) 534 { 535 return 0; 536 } 537 538 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 539 struct amdgpu_irq_src *source, 540 struct amdgpu_iv_entry *entry) 541 { 542 DRM_DEBUG("IH: JPEG TRAP\n"); 543 544 switch (entry->src_id) { 545 case VCN_4_0__SRCID__JPEG_DECODE: 546 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 547 break; 548 case VCN_4_0__SRCID_DJPEG0_POISON: 549 case VCN_4_0__SRCID_EJPEG0_POISON: 550 amdgpu_jpeg_process_poison_irq(adev, source, entry); 551 break; 552 default: 553 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 554 entry->src_id, entry->src_data[0]); 555 break; 556 } 557 558 return 0; 559 } 560 561 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 562 .name = "jpeg_v4_0", 563 .early_init = jpeg_v4_0_early_init, 564 .late_init = NULL, 565 .sw_init = jpeg_v4_0_sw_init, 566 .sw_fini = jpeg_v4_0_sw_fini, 567 .hw_init = jpeg_v4_0_hw_init, 568 .hw_fini = jpeg_v4_0_hw_fini, 569 .suspend = jpeg_v4_0_suspend, 570 .resume = jpeg_v4_0_resume, 571 .is_idle = jpeg_v4_0_is_idle, 572 .wait_for_idle = jpeg_v4_0_wait_for_idle, 573 .check_soft_reset = NULL, 574 .pre_soft_reset = NULL, 575 .soft_reset = NULL, 576 .post_soft_reset = NULL, 577 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 578 .set_powergating_state = jpeg_v4_0_set_powergating_state, 579 }; 580 581 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 582 .type = AMDGPU_RING_TYPE_VCN_JPEG, 583 .align_mask = 0xf, 584 .vmhub = AMDGPU_MMHUB_0, 585 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 586 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 587 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 588 .emit_frame_size = 589 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 590 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 591 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 592 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 593 8 + 16, 594 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 595 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 596 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 597 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 598 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 599 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 600 .insert_nop = jpeg_v2_0_dec_ring_nop, 601 .insert_start = jpeg_v2_0_dec_ring_insert_start, 602 .insert_end = jpeg_v2_0_dec_ring_insert_end, 603 .pad_ib = amdgpu_ring_generic_pad_ib, 604 .begin_use = amdgpu_jpeg_ring_begin_use, 605 .end_use = amdgpu_jpeg_ring_end_use, 606 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 607 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 608 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 609 }; 610 611 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 612 { 613 adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs; 614 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); 615 } 616 617 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 618 .set = jpeg_v4_0_set_interrupt_state, 619 .process = jpeg_v4_0_process_interrupt, 620 }; 621 622 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 623 { 624 adev->jpeg.inst->irq.num_types = 1; 625 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 626 } 627 628 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 629 .type = AMD_IP_BLOCK_TYPE_JPEG, 630 .major = 4, 631 .minor = 0, 632 .rev = 0, 633 .funcs = &jpeg_v4_0_ip_funcs, 634 }; 635 636 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 637 uint32_t instance, uint32_t sub_block) 638 { 639 uint32_t poison_stat = 0, reg_value = 0; 640 641 switch (sub_block) { 642 case AMDGPU_JPEG_V4_0_JPEG0: 643 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 644 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 645 break; 646 case AMDGPU_JPEG_V4_0_JPEG1: 647 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 648 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 649 break; 650 default: 651 break; 652 } 653 654 if (poison_stat) 655 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 656 instance, sub_block); 657 658 return poison_stat; 659 } 660 661 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 662 { 663 uint32_t inst = 0, sub = 0, poison_stat = 0; 664 665 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 666 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 667 poison_stat += 668 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 669 670 return !!poison_stat; 671 } 672 673 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 674 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 675 }; 676 677 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 678 .ras_block = { 679 .hw_ops = &jpeg_v4_0_ras_hw_ops, 680 }, 681 }; 682 683 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 684 { 685 switch (adev->ip_versions[JPEG_HWIP][0]) { 686 case IP_VERSION(4, 0, 0): 687 adev->jpeg.ras = &jpeg_v4_0_ras; 688 break; 689 default: 690 break; 691 } 692 } 693