1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 #include "mmsch_v4_0.h" 32 33 #include "vcn/vcn_4_0_0_offset.h" 34 #include "vcn/vcn_4_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 37 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 38 39 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev); 40 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 41 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 42 static int jpeg_v4_0_set_powergating_state(void *handle, 43 enum amd_powergating_state state); 44 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 45 46 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 47 48 /** 49 * jpeg_v4_0_early_init - set function pointers 50 * 51 * @handle: amdgpu_device pointer 52 * 53 * Set ring and irq function pointers 54 */ 55 static int jpeg_v4_0_early_init(void *handle) 56 { 57 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 58 59 60 adev->jpeg.num_jpeg_inst = 1; 61 62 jpeg_v4_0_set_dec_ring_funcs(adev); 63 jpeg_v4_0_set_irq_funcs(adev); 64 jpeg_v4_0_set_ras_funcs(adev); 65 66 return 0; 67 } 68 69 /** 70 * jpeg_v4_0_sw_init - sw init for JPEG block 71 * 72 * @handle: amdgpu_device pointer 73 * 74 * Load firmware and sw initialization 75 */ 76 static int jpeg_v4_0_sw_init(void *handle) 77 { 78 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 79 struct amdgpu_ring *ring; 80 int r; 81 82 /* JPEG TRAP */ 83 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 84 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 85 if (r) 86 return r; 87 88 /* JPEG DJPEG POISON EVENT */ 89 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 90 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq); 91 if (r) 92 return r; 93 94 /* JPEG EJPEG POISON EVENT */ 95 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 96 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq); 97 if (r) 98 return r; 99 100 r = amdgpu_jpeg_sw_init(adev); 101 if (r) 102 return r; 103 104 r = amdgpu_jpeg_resume(adev); 105 if (r) 106 return r; 107 108 ring = &adev->jpeg.inst->ring_dec; 109 ring->use_doorbell = true; 110 ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1); 111 112 sprintf(ring->name, "jpeg_dec"); 113 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 114 AMDGPU_RING_PRIO_DEFAULT, NULL); 115 if (r) 116 return r; 117 118 adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 119 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 120 121 r = amdgpu_jpeg_ras_sw_init(adev); 122 if (r) 123 return r; 124 125 return 0; 126 } 127 128 /** 129 * jpeg_v4_0_sw_fini - sw fini for JPEG block 130 * 131 * @handle: amdgpu_device pointer 132 * 133 * JPEG suspend and free up sw allocation 134 */ 135 static int jpeg_v4_0_sw_fini(void *handle) 136 { 137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 138 int r; 139 140 r = amdgpu_jpeg_suspend(adev); 141 if (r) 142 return r; 143 144 r = amdgpu_jpeg_sw_fini(adev); 145 146 return r; 147 } 148 149 /** 150 * jpeg_v4_0_hw_init - start and test JPEG block 151 * 152 * @handle: amdgpu_device pointer 153 * 154 */ 155 static int jpeg_v4_0_hw_init(void *handle) 156 { 157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 158 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 159 int r; 160 161 if (amdgpu_sriov_vf(adev)) { 162 r = jpeg_v4_0_start_sriov(adev); 163 if (r) 164 return r; 165 ring->wptr = 0; 166 ring->wptr_old = 0; 167 jpeg_v4_0_dec_ring_set_wptr(ring); 168 ring->sched.ready = true; 169 } else { 170 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 171 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 172 173 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 174 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 175 VCN_JPEG_DB_CTRL__EN_MASK); 176 177 r = amdgpu_ring_test_helper(ring); 178 if (r) 179 return r; 180 } 181 182 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); 183 184 return 0; 185 } 186 187 /** 188 * jpeg_v4_0_hw_fini - stop the hardware block 189 * 190 * @handle: amdgpu_device pointer 191 * 192 * Stop the JPEG block, mark ring as not ready any more 193 */ 194 static int jpeg_v4_0_hw_fini(void *handle) 195 { 196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 197 198 cancel_delayed_work_sync(&adev->vcn.idle_work); 199 if (!amdgpu_sriov_vf(adev)) { 200 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 201 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 202 jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 203 } 204 amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0); 205 206 return 0; 207 } 208 209 /** 210 * jpeg_v4_0_suspend - suspend JPEG block 211 * 212 * @handle: amdgpu_device pointer 213 * 214 * HW fini and suspend JPEG block 215 */ 216 static int jpeg_v4_0_suspend(void *handle) 217 { 218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 219 int r; 220 221 r = jpeg_v4_0_hw_fini(adev); 222 if (r) 223 return r; 224 225 r = amdgpu_jpeg_suspend(adev); 226 227 return r; 228 } 229 230 /** 231 * jpeg_v4_0_resume - resume JPEG block 232 * 233 * @handle: amdgpu_device pointer 234 * 235 * Resume firmware and hw init JPEG block 236 */ 237 static int jpeg_v4_0_resume(void *handle) 238 { 239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 240 int r; 241 242 r = amdgpu_jpeg_resume(adev); 243 if (r) 244 return r; 245 246 r = jpeg_v4_0_hw_init(adev); 247 248 return r; 249 } 250 251 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 252 { 253 uint32_t data = 0; 254 255 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 256 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 257 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 258 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 259 } else { 260 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 261 } 262 263 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 264 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 265 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 266 267 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 268 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 269 | JPEG_CGC_GATE__JPEG2_DEC_MASK 270 | JPEG_CGC_GATE__JMCIF_MASK 271 | JPEG_CGC_GATE__JRBBM_MASK); 272 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 273 } 274 275 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 276 { 277 uint32_t data = 0; 278 279 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 280 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 281 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 282 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 283 } else { 284 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 285 } 286 287 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 288 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 289 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 290 291 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 292 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 293 |JPEG_CGC_GATE__JPEG2_DEC_MASK 294 |JPEG_CGC_GATE__JMCIF_MASK 295 |JPEG_CGC_GATE__JRBBM_MASK); 296 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 297 } 298 299 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 300 { 301 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 302 uint32_t data = 0; 303 int r = 0; 304 305 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 306 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 307 308 r = SOC15_WAIT_ON_RREG(JPEG, 0, 309 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 310 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 311 312 if (r) { 313 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 314 return r; 315 } 316 } 317 318 /* disable anti hang mechanism */ 319 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 320 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 321 322 /* keep the JPEG in static PG mode */ 323 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 324 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 325 326 return 0; 327 } 328 329 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 330 { 331 /* enable anti hang mechanism */ 332 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 333 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 334 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 335 336 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 337 uint32_t data = 0; 338 int r = 0; 339 340 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 341 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 342 343 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 344 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 345 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 346 347 if (r) { 348 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 349 return r; 350 } 351 } 352 353 return 0; 354 } 355 356 /** 357 * jpeg_v4_0_start - start JPEG block 358 * 359 * @adev: amdgpu_device pointer 360 * 361 * Setup and start the JPEG block 362 */ 363 static int jpeg_v4_0_start(struct amdgpu_device *adev) 364 { 365 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 366 int r; 367 368 if (adev->pm.dpm_enabled) 369 amdgpu_dpm_enable_jpeg(adev, true); 370 371 /* disable power gating */ 372 r = jpeg_v4_0_disable_static_power_gating(adev); 373 if (r) 374 return r; 375 376 /* JPEG disable CGC */ 377 jpeg_v4_0_disable_clock_gating(adev); 378 379 /* MJPEG global tiling registers */ 380 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 381 adev->gfx.config.gb_addr_config); 382 383 384 /* enable JMI channel */ 385 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 386 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 387 388 /* enable System Interrupt for JRBC */ 389 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 390 JPEG_SYS_INT_EN__DJRBC_MASK, 391 ~JPEG_SYS_INT_EN__DJRBC_MASK); 392 393 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 394 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 395 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 396 lower_32_bits(ring->gpu_addr)); 397 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 398 upper_32_bits(ring->gpu_addr)); 399 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 400 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 401 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 402 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 403 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 404 405 return 0; 406 } 407 408 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev) 409 { 410 struct amdgpu_ring *ring; 411 uint64_t ctx_addr; 412 uint32_t param, resp, expected; 413 uint32_t tmp, timeout; 414 415 struct amdgpu_mm_table *table = &adev->virt.mm_table; 416 uint32_t *table_loc; 417 uint32_t table_size; 418 uint32_t size, size_dw; 419 uint32_t init_status; 420 421 struct mmsch_v4_0_cmd_direct_write 422 direct_wt = { {0} }; 423 struct mmsch_v4_0_cmd_end end = { {0} }; 424 struct mmsch_v4_0_init_header header; 425 426 direct_wt.cmd_header.command_type = 427 MMSCH_COMMAND__DIRECT_REG_WRITE; 428 end.cmd_header.command_type = 429 MMSCH_COMMAND__END; 430 431 header.version = MMSCH_VERSION; 432 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 433 434 header.jpegdec.init_status = 0; 435 header.jpegdec.table_offset = 0; 436 header.jpegdec.table_size = 0; 437 438 table_loc = (uint32_t *)table->cpu_addr; 439 table_loc += header.total_size; 440 441 table_size = 0; 442 443 ring = &adev->jpeg.inst->ring_dec; 444 445 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 446 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW), 447 lower_32_bits(ring->gpu_addr)); 448 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 449 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH), 450 upper_32_bits(ring->gpu_addr)); 451 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 452 regUVD_JRBC_RB_SIZE), ring->ring_size / 4); 453 454 /* add end packet */ 455 MMSCH_V4_0_INSERT_END(); 456 457 /* refine header */ 458 header.jpegdec.init_status = 0; 459 header.jpegdec.table_offset = header.total_size; 460 header.jpegdec.table_size = table_size; 461 header.total_size += table_size; 462 463 /* Update init table header in memory */ 464 size = sizeof(struct mmsch_v4_0_init_header); 465 table_loc = (uint32_t *)table->cpu_addr; 466 memcpy((void *)table_loc, &header, size); 467 468 /* message MMSCH (in VCN[0]) to initialize this client 469 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 470 * of memory descriptor location 471 */ 472 ctx_addr = table->gpu_addr; 473 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 474 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 475 476 /* 2, update vmid of descriptor */ 477 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 478 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 479 /* use domain0 for MM scheduler */ 480 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 481 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 482 483 /* 3, notify mmsch about the size of this descriptor */ 484 size = header.total_size; 485 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 486 487 /* 4, set resp to zero */ 488 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 489 490 /* 5, kick off the initialization and wait until 491 * MMSCH_VF_MAILBOX_RESP becomes non-zero 492 */ 493 param = 0x00000001; 494 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 495 tmp = 0; 496 timeout = 1000; 497 resp = 0; 498 expected = MMSCH_VF_MAILBOX_RESP__OK; 499 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status; 500 while (resp != expected) { 501 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 502 503 if (resp != 0) 504 break; 505 udelay(10); 506 tmp = tmp + 10; 507 if (tmp >= timeout) { 508 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 509 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 510 "(expected=0x%08x, readback=0x%08x)\n", 511 tmp, expected, resp); 512 return -EBUSY; 513 } 514 } 515 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 516 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status); 517 518 return 0; 519 520 } 521 522 /** 523 * jpeg_v4_0_stop - stop JPEG block 524 * 525 * @adev: amdgpu_device pointer 526 * 527 * stop the JPEG block 528 */ 529 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 530 { 531 int r; 532 533 /* reset JMI */ 534 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 535 UVD_JMI_CNTL__SOFT_RESET_MASK, 536 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 537 538 jpeg_v4_0_enable_clock_gating(adev); 539 540 /* enable power gating */ 541 r = jpeg_v4_0_enable_static_power_gating(adev); 542 if (r) 543 return r; 544 545 if (adev->pm.dpm_enabled) 546 amdgpu_dpm_enable_jpeg(adev, false); 547 548 return 0; 549 } 550 551 /** 552 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 553 * 554 * @ring: amdgpu_ring pointer 555 * 556 * Returns the current hardware read pointer 557 */ 558 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 559 { 560 struct amdgpu_device *adev = ring->adev; 561 562 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 563 } 564 565 /** 566 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 567 * 568 * @ring: amdgpu_ring pointer 569 * 570 * Returns the current hardware write pointer 571 */ 572 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 573 { 574 struct amdgpu_device *adev = ring->adev; 575 576 if (ring->use_doorbell) 577 return *ring->wptr_cpu_addr; 578 else 579 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 580 } 581 582 /** 583 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 584 * 585 * @ring: amdgpu_ring pointer 586 * 587 * Commits the write pointer to the hardware 588 */ 589 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 590 { 591 struct amdgpu_device *adev = ring->adev; 592 593 if (ring->use_doorbell) { 594 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 595 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 596 } else { 597 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 598 } 599 } 600 601 static bool jpeg_v4_0_is_idle(void *handle) 602 { 603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604 int ret = 1; 605 606 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 607 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 608 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 609 610 return ret; 611 } 612 613 static int jpeg_v4_0_wait_for_idle(void *handle) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 616 617 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 618 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 619 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 620 } 621 622 static int jpeg_v4_0_set_clockgating_state(void *handle, 623 enum amd_clockgating_state state) 624 { 625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 627 628 if (enable) { 629 if (!jpeg_v4_0_is_idle(handle)) 630 return -EBUSY; 631 jpeg_v4_0_enable_clock_gating(adev); 632 } else { 633 jpeg_v4_0_disable_clock_gating(adev); 634 } 635 636 return 0; 637 } 638 639 static int jpeg_v4_0_set_powergating_state(void *handle, 640 enum amd_powergating_state state) 641 { 642 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 643 int ret; 644 645 if (amdgpu_sriov_vf(adev)) { 646 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 647 return 0; 648 } 649 650 if (state == adev->jpeg.cur_state) 651 return 0; 652 653 if (state == AMD_PG_STATE_GATE) 654 ret = jpeg_v4_0_stop(adev); 655 else 656 ret = jpeg_v4_0_start(adev); 657 658 if (!ret) 659 adev->jpeg.cur_state = state; 660 661 return ret; 662 } 663 664 static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev, 665 struct amdgpu_irq_src *source, 666 unsigned type, 667 enum amdgpu_interrupt_state state) 668 { 669 return 0; 670 } 671 672 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 673 struct amdgpu_irq_src *source, 674 struct amdgpu_iv_entry *entry) 675 { 676 DRM_DEBUG("IH: JPEG TRAP\n"); 677 678 switch (entry->src_id) { 679 case VCN_4_0__SRCID__JPEG_DECODE: 680 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 681 break; 682 case VCN_4_0__SRCID_DJPEG0_POISON: 683 case VCN_4_0__SRCID_EJPEG0_POISON: 684 amdgpu_jpeg_process_poison_irq(adev, source, entry); 685 break; 686 default: 687 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 688 entry->src_id, entry->src_data[0]); 689 break; 690 } 691 692 return 0; 693 } 694 695 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 696 .name = "jpeg_v4_0", 697 .early_init = jpeg_v4_0_early_init, 698 .late_init = NULL, 699 .sw_init = jpeg_v4_0_sw_init, 700 .sw_fini = jpeg_v4_0_sw_fini, 701 .hw_init = jpeg_v4_0_hw_init, 702 .hw_fini = jpeg_v4_0_hw_fini, 703 .suspend = jpeg_v4_0_suspend, 704 .resume = jpeg_v4_0_resume, 705 .is_idle = jpeg_v4_0_is_idle, 706 .wait_for_idle = jpeg_v4_0_wait_for_idle, 707 .check_soft_reset = NULL, 708 .pre_soft_reset = NULL, 709 .soft_reset = NULL, 710 .post_soft_reset = NULL, 711 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 712 .set_powergating_state = jpeg_v4_0_set_powergating_state, 713 }; 714 715 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 716 .type = AMDGPU_RING_TYPE_VCN_JPEG, 717 .align_mask = 0xf, 718 .vmhub = AMDGPU_MMHUB_0, 719 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 720 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 721 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 722 .emit_frame_size = 723 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 724 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 725 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 726 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 727 8 + 16, 728 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 729 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 730 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 731 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 732 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 733 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 734 .insert_nop = jpeg_v2_0_dec_ring_nop, 735 .insert_start = jpeg_v2_0_dec_ring_insert_start, 736 .insert_end = jpeg_v2_0_dec_ring_insert_end, 737 .pad_ib = amdgpu_ring_generic_pad_ib, 738 .begin_use = amdgpu_jpeg_ring_begin_use, 739 .end_use = amdgpu_jpeg_ring_end_use, 740 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 741 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 742 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 743 }; 744 745 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 746 { 747 adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs; 748 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); 749 } 750 751 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 752 .set = jpeg_v4_0_set_interrupt_state, 753 .process = jpeg_v4_0_process_interrupt, 754 }; 755 756 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 757 { 758 adev->jpeg.inst->irq.num_types = 1; 759 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 760 } 761 762 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 763 .type = AMD_IP_BLOCK_TYPE_JPEG, 764 .major = 4, 765 .minor = 0, 766 .rev = 0, 767 .funcs = &jpeg_v4_0_ip_funcs, 768 }; 769 770 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 771 uint32_t instance, uint32_t sub_block) 772 { 773 uint32_t poison_stat = 0, reg_value = 0; 774 775 switch (sub_block) { 776 case AMDGPU_JPEG_V4_0_JPEG0: 777 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 778 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 779 break; 780 case AMDGPU_JPEG_V4_0_JPEG1: 781 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 782 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 783 break; 784 default: 785 break; 786 } 787 788 if (poison_stat) 789 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 790 instance, sub_block); 791 792 return poison_stat; 793 } 794 795 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 796 { 797 uint32_t inst = 0, sub = 0, poison_stat = 0; 798 799 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 800 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 801 poison_stat += 802 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 803 804 return !!poison_stat; 805 } 806 807 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 808 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 809 }; 810 811 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 812 .ras_block = { 813 .hw_ops = &jpeg_v4_0_ras_hw_ops, 814 }, 815 }; 816 817 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 818 { 819 switch (adev->ip_versions[JPEG_HWIP][0]) { 820 case IP_VERSION(4, 0, 0): 821 adev->jpeg.ras = &jpeg_v4_0_ras; 822 break; 823 default: 824 break; 825 } 826 } 827