1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 32 #include "vcn/vcn_4_0_0_offset.h" 33 #include "vcn/vcn_4_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 37 38 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v4_0_set_powergating_state(void *handle, 41 enum amd_powergating_state state); 42 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 43 44 /** 45 * jpeg_v4_0_early_init - set function pointers 46 * 47 * @handle: amdgpu_device pointer 48 * 49 * Set ring and irq function pointers 50 */ 51 static int jpeg_v4_0_early_init(void *handle) 52 { 53 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 54 55 56 adev->jpeg.num_jpeg_inst = 1; 57 58 jpeg_v4_0_set_dec_ring_funcs(adev); 59 jpeg_v4_0_set_irq_funcs(adev); 60 jpeg_v4_0_set_ras_funcs(adev); 61 62 return 0; 63 } 64 65 /** 66 * jpeg_v4_0_sw_init - sw init for JPEG block 67 * 68 * @handle: amdgpu_device pointer 69 * 70 * Load firmware and sw initialization 71 */ 72 static int jpeg_v4_0_sw_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct amdgpu_ring *ring; 76 int r; 77 78 /* JPEG TRAP */ 79 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 80 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 81 if (r) 82 return r; 83 84 r = amdgpu_jpeg_sw_init(adev); 85 if (r) 86 return r; 87 88 r = amdgpu_jpeg_resume(adev); 89 if (r) 90 return r; 91 92 ring = &adev->jpeg.inst->ring_dec; 93 ring->use_doorbell = true; 94 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 95 sprintf(ring->name, "jpeg_dec"); 96 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 97 AMDGPU_RING_PRIO_DEFAULT, NULL); 98 if (r) 99 return r; 100 101 adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 102 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 103 104 return 0; 105 } 106 107 /** 108 * jpeg_v4_0_sw_fini - sw fini for JPEG block 109 * 110 * @handle: amdgpu_device pointer 111 * 112 * JPEG suspend and free up sw allocation 113 */ 114 static int jpeg_v4_0_sw_fini(void *handle) 115 { 116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 117 int r; 118 119 r = amdgpu_jpeg_suspend(adev); 120 if (r) 121 return r; 122 123 r = amdgpu_jpeg_sw_fini(adev); 124 125 return r; 126 } 127 128 /** 129 * jpeg_v4_0_hw_init - start and test JPEG block 130 * 131 * @handle: amdgpu_device pointer 132 * 133 */ 134 static int jpeg_v4_0_hw_init(void *handle) 135 { 136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 138 int r; 139 140 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 141 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 142 143 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 144 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 145 VCN_JPEG_DB_CTRL__EN_MASK); 146 147 r = amdgpu_ring_test_helper(ring); 148 if (r) 149 return r; 150 151 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); 152 153 return 0; 154 } 155 156 /** 157 * jpeg_v4_0_hw_fini - stop the hardware block 158 * 159 * @handle: amdgpu_device pointer 160 * 161 * Stop the JPEG block, mark ring as not ready any more 162 */ 163 static int jpeg_v4_0_hw_fini(void *handle) 164 { 165 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 166 167 cancel_delayed_work_sync(&adev->vcn.idle_work); 168 169 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 170 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 171 jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 172 173 return 0; 174 } 175 176 /** 177 * jpeg_v4_0_suspend - suspend JPEG block 178 * 179 * @handle: amdgpu_device pointer 180 * 181 * HW fini and suspend JPEG block 182 */ 183 static int jpeg_v4_0_suspend(void *handle) 184 { 185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 186 int r; 187 188 r = jpeg_v4_0_hw_fini(adev); 189 if (r) 190 return r; 191 192 r = amdgpu_jpeg_suspend(adev); 193 194 return r; 195 } 196 197 /** 198 * jpeg_v4_0_resume - resume JPEG block 199 * 200 * @handle: amdgpu_device pointer 201 * 202 * Resume firmware and hw init JPEG block 203 */ 204 static int jpeg_v4_0_resume(void *handle) 205 { 206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 207 int r; 208 209 r = amdgpu_jpeg_resume(adev); 210 if (r) 211 return r; 212 213 r = jpeg_v4_0_hw_init(adev); 214 215 return r; 216 } 217 218 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 219 { 220 uint32_t data = 0; 221 222 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 223 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 224 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 225 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 226 } else { 227 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 228 } 229 230 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 231 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 232 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 233 234 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 235 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 236 | JPEG_CGC_GATE__JPEG2_DEC_MASK 237 | JPEG_CGC_GATE__JMCIF_MASK 238 | JPEG_CGC_GATE__JRBBM_MASK); 239 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 240 } 241 242 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 243 { 244 uint32_t data = 0; 245 246 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 247 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 248 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 249 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 250 } else { 251 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 252 } 253 254 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 255 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 256 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 257 258 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 259 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 260 |JPEG_CGC_GATE__JPEG2_DEC_MASK 261 |JPEG_CGC_GATE__JMCIF_MASK 262 |JPEG_CGC_GATE__JRBBM_MASK); 263 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 264 } 265 266 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 267 { 268 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 269 uint32_t data = 0; 270 int r = 0; 271 272 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 273 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 274 275 r = SOC15_WAIT_ON_RREG(JPEG, 0, 276 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 277 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 278 279 if (r) { 280 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 281 return r; 282 } 283 } 284 285 /* disable anti hang mechanism */ 286 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 287 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 288 289 /* keep the JPEG in static PG mode */ 290 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 291 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 292 293 return 0; 294 } 295 296 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 297 { 298 /* enable anti hang mechanism */ 299 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 300 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 301 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 302 303 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 304 uint32_t data = 0; 305 int r = 0; 306 307 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 308 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 309 310 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 311 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 312 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 313 314 if (r) { 315 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 316 return r; 317 } 318 } 319 320 return 0; 321 } 322 323 /** 324 * jpeg_v4_0_start - start JPEG block 325 * 326 * @adev: amdgpu_device pointer 327 * 328 * Setup and start the JPEG block 329 */ 330 static int jpeg_v4_0_start(struct amdgpu_device *adev) 331 { 332 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 333 int r; 334 335 if (adev->pm.dpm_enabled) 336 amdgpu_dpm_enable_jpeg(adev, true); 337 338 /* disable power gating */ 339 r = jpeg_v4_0_disable_static_power_gating(adev); 340 if (r) 341 return r; 342 343 /* JPEG disable CGC */ 344 jpeg_v4_0_disable_clock_gating(adev); 345 346 /* MJPEG global tiling registers */ 347 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 348 adev->gfx.config.gb_addr_config); 349 350 351 /* enable JMI channel */ 352 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 353 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 354 355 /* enable System Interrupt for JRBC */ 356 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 357 JPEG_SYS_INT_EN__DJRBC_MASK, 358 ~JPEG_SYS_INT_EN__DJRBC_MASK); 359 360 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 361 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 362 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 363 lower_32_bits(ring->gpu_addr)); 364 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 365 upper_32_bits(ring->gpu_addr)); 366 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 367 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 368 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 369 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 370 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 371 372 return 0; 373 } 374 375 /** 376 * jpeg_v4_0_stop - stop JPEG block 377 * 378 * @adev: amdgpu_device pointer 379 * 380 * stop the JPEG block 381 */ 382 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 383 { 384 int r; 385 386 /* reset JMI */ 387 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 388 UVD_JMI_CNTL__SOFT_RESET_MASK, 389 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 390 391 jpeg_v4_0_enable_clock_gating(adev); 392 393 /* enable power gating */ 394 r = jpeg_v4_0_enable_static_power_gating(adev); 395 if (r) 396 return r; 397 398 if (adev->pm.dpm_enabled) 399 amdgpu_dpm_enable_jpeg(adev, false); 400 401 return 0; 402 } 403 404 /** 405 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 406 * 407 * @ring: amdgpu_ring pointer 408 * 409 * Returns the current hardware read pointer 410 */ 411 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 412 { 413 struct amdgpu_device *adev = ring->adev; 414 415 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 416 } 417 418 /** 419 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 420 * 421 * @ring: amdgpu_ring pointer 422 * 423 * Returns the current hardware write pointer 424 */ 425 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 429 if (ring->use_doorbell) 430 return *ring->wptr_cpu_addr; 431 else 432 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 433 } 434 435 /** 436 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 437 * 438 * @ring: amdgpu_ring pointer 439 * 440 * Commits the write pointer to the hardware 441 */ 442 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 443 { 444 struct amdgpu_device *adev = ring->adev; 445 446 if (ring->use_doorbell) { 447 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 448 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 449 } else { 450 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 451 } 452 } 453 454 static bool jpeg_v4_0_is_idle(void *handle) 455 { 456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 457 int ret = 1; 458 459 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 460 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 461 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 462 463 return ret; 464 } 465 466 static int jpeg_v4_0_wait_for_idle(void *handle) 467 { 468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 469 470 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 471 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 472 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 473 } 474 475 static int jpeg_v4_0_set_clockgating_state(void *handle, 476 enum amd_clockgating_state state) 477 { 478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 479 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 480 481 if (enable) { 482 if (!jpeg_v4_0_is_idle(handle)) 483 return -EBUSY; 484 jpeg_v4_0_enable_clock_gating(adev); 485 } else { 486 jpeg_v4_0_disable_clock_gating(adev); 487 } 488 489 return 0; 490 } 491 492 static int jpeg_v4_0_set_powergating_state(void *handle, 493 enum amd_powergating_state state) 494 { 495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 496 int ret; 497 498 if (state == adev->jpeg.cur_state) 499 return 0; 500 501 if (state == AMD_PG_STATE_GATE) 502 ret = jpeg_v4_0_stop(adev); 503 else 504 ret = jpeg_v4_0_start(adev); 505 506 if (!ret) 507 adev->jpeg.cur_state = state; 508 509 return ret; 510 } 511 512 static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev, 513 struct amdgpu_irq_src *source, 514 unsigned type, 515 enum amdgpu_interrupt_state state) 516 { 517 return 0; 518 } 519 520 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 521 struct amdgpu_irq_src *source, 522 struct amdgpu_iv_entry *entry) 523 { 524 DRM_DEBUG("IH: JPEG TRAP\n"); 525 526 switch (entry->src_id) { 527 case VCN_4_0__SRCID__JPEG_DECODE: 528 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 529 break; 530 default: 531 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 532 entry->src_id, entry->src_data[0]); 533 break; 534 } 535 536 return 0; 537 } 538 539 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 540 .name = "jpeg_v4_0", 541 .early_init = jpeg_v4_0_early_init, 542 .late_init = NULL, 543 .sw_init = jpeg_v4_0_sw_init, 544 .sw_fini = jpeg_v4_0_sw_fini, 545 .hw_init = jpeg_v4_0_hw_init, 546 .hw_fini = jpeg_v4_0_hw_fini, 547 .suspend = jpeg_v4_0_suspend, 548 .resume = jpeg_v4_0_resume, 549 .is_idle = jpeg_v4_0_is_idle, 550 .wait_for_idle = jpeg_v4_0_wait_for_idle, 551 .check_soft_reset = NULL, 552 .pre_soft_reset = NULL, 553 .soft_reset = NULL, 554 .post_soft_reset = NULL, 555 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 556 .set_powergating_state = jpeg_v4_0_set_powergating_state, 557 }; 558 559 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 560 .type = AMDGPU_RING_TYPE_VCN_JPEG, 561 .align_mask = 0xf, 562 .vmhub = AMDGPU_MMHUB_0, 563 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 564 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 565 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 566 .emit_frame_size = 567 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 568 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 569 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 570 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 571 8 + 16, 572 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 573 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 574 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 575 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 576 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 577 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 578 .insert_nop = jpeg_v2_0_dec_ring_nop, 579 .insert_start = jpeg_v2_0_dec_ring_insert_start, 580 .insert_end = jpeg_v2_0_dec_ring_insert_end, 581 .pad_ib = amdgpu_ring_generic_pad_ib, 582 .begin_use = amdgpu_jpeg_ring_begin_use, 583 .end_use = amdgpu_jpeg_ring_end_use, 584 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 585 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 586 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 587 }; 588 589 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 590 { 591 adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs; 592 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); 593 } 594 595 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 596 .set = jpeg_v4_0_set_interrupt_state, 597 .process = jpeg_v4_0_process_interrupt, 598 }; 599 600 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 601 { 602 adev->jpeg.inst->irq.num_types = 1; 603 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 604 } 605 606 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 607 .type = AMD_IP_BLOCK_TYPE_JPEG, 608 .major = 4, 609 .minor = 0, 610 .rev = 0, 611 .funcs = &jpeg_v4_0_ip_funcs, 612 }; 613 614 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 615 uint32_t instance, uint32_t sub_block) 616 { 617 uint32_t poison_stat = 0, reg_value = 0; 618 619 switch (sub_block) { 620 case AMDGPU_JPEG_V4_0_JPEG0: 621 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 622 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 623 break; 624 case AMDGPU_JPEG_V4_0_JPEG1: 625 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 626 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 627 break; 628 default: 629 break; 630 } 631 632 if (poison_stat) 633 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 634 instance, sub_block); 635 636 return poison_stat; 637 } 638 639 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 640 { 641 uint32_t inst = 0, sub = 0, poison_stat = 0; 642 643 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 644 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 645 poison_stat += 646 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 647 648 return !!poison_stat; 649 } 650 651 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 652 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 653 }; 654 655 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 656 .ras_block = { 657 .hw_ops = &jpeg_v4_0_ras_hw_ops, 658 }, 659 }; 660 661 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 662 { 663 switch (adev->ip_versions[JPEG_HWIP][0]) { 664 case IP_VERSION(4, 0, 0): 665 adev->jpeg.ras = &jpeg_v4_0_ras; 666 break; 667 default: 668 break; 669 } 670 671 jpeg_set_ras_funcs(adev); 672 } 673