1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 31 #include "vcn/vcn_3_0_0_offset.h" 32 #include "vcn/vcn_3_0_0_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 38 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev); 39 static int jpeg_v3_0_set_powergating_state(void *handle, 40 enum amd_powergating_state state); 41 42 /** 43 * jpeg_v3_0_early_init - set function pointers 44 * 45 * @handle: amdgpu_device pointer 46 * 47 * Set ring and irq function pointers 48 */ 49 static int jpeg_v3_0_early_init(void *handle) 50 { 51 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 52 u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); 53 54 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 55 return -ENOENT; 56 57 adev->jpeg.num_jpeg_inst = 1; 58 59 jpeg_v3_0_set_dec_ring_funcs(adev); 60 jpeg_v3_0_set_irq_funcs(adev); 61 62 return 0; 63 } 64 65 /** 66 * jpeg_v3_0_sw_init - sw init for JPEG block 67 * 68 * @handle: amdgpu_device pointer 69 * 70 * Load firmware and sw initialization 71 */ 72 static int jpeg_v3_0_sw_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct amdgpu_ring *ring; 76 int r; 77 78 /* JPEG TRAP */ 79 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 80 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 81 if (r) 82 return r; 83 84 r = amdgpu_jpeg_sw_init(adev); 85 if (r) 86 return r; 87 88 r = amdgpu_jpeg_resume(adev); 89 if (r) 90 return r; 91 92 ring = &adev->jpeg.inst->ring_dec; 93 ring->use_doorbell = true; 94 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 95 sprintf(ring->name, "jpeg_dec"); 96 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 97 AMDGPU_RING_PRIO_DEFAULT, NULL); 98 if (r) 99 return r; 100 101 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 102 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 103 104 return 0; 105 } 106 107 /** 108 * jpeg_v3_0_sw_fini - sw fini for JPEG block 109 * 110 * @handle: amdgpu_device pointer 111 * 112 * JPEG suspend and free up sw allocation 113 */ 114 static int jpeg_v3_0_sw_fini(void *handle) 115 { 116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 117 int r; 118 119 r = amdgpu_jpeg_suspend(adev); 120 if (r) 121 return r; 122 123 r = amdgpu_jpeg_sw_fini(adev); 124 125 return r; 126 } 127 128 /** 129 * jpeg_v3_0_hw_init - start and test JPEG block 130 * 131 * @handle: amdgpu_device pointer 132 * 133 */ 134 static int jpeg_v3_0_hw_init(void *handle) 135 { 136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 137 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 138 int r; 139 140 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 141 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 142 143 r = amdgpu_ring_test_helper(ring); 144 if (r) 145 return r; 146 147 DRM_INFO("JPEG decode initialized successfully.\n"); 148 149 return 0; 150 } 151 152 /** 153 * jpeg_v3_0_hw_fini - stop the hardware block 154 * 155 * @handle: amdgpu_device pointer 156 * 157 * Stop the JPEG block, mark ring as not ready any more 158 */ 159 static int jpeg_v3_0_hw_fini(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 163 cancel_delayed_work_sync(&adev->vcn.idle_work); 164 165 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 166 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 167 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 168 169 return 0; 170 } 171 172 /** 173 * jpeg_v3_0_suspend - suspend JPEG block 174 * 175 * @handle: amdgpu_device pointer 176 * 177 * HW fini and suspend JPEG block 178 */ 179 static int jpeg_v3_0_suspend(void *handle) 180 { 181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 182 int r; 183 184 r = jpeg_v3_0_hw_fini(adev); 185 if (r) 186 return r; 187 188 r = amdgpu_jpeg_suspend(adev); 189 190 return r; 191 } 192 193 /** 194 * jpeg_v3_0_resume - resume JPEG block 195 * 196 * @handle: amdgpu_device pointer 197 * 198 * Resume firmware and hw init JPEG block 199 */ 200 static int jpeg_v3_0_resume(void *handle) 201 { 202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 203 int r; 204 205 r = amdgpu_jpeg_resume(adev); 206 if (r) 207 return r; 208 209 r = jpeg_v3_0_hw_init(adev); 210 211 return r; 212 } 213 214 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev) 215 { 216 uint32_t data = 0; 217 218 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 219 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 220 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 221 else 222 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 223 224 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 225 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 226 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 227 228 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 229 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 230 | JPEG_CGC_GATE__JPEG2_DEC_MASK 231 | JPEG_CGC_GATE__JPEG_ENC_MASK 232 | JPEG_CGC_GATE__JMCIF_MASK 233 | JPEG_CGC_GATE__JRBBM_MASK); 234 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 235 236 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 237 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 238 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 239 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 240 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 241 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 242 } 243 244 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev) 245 { 246 uint32_t data = 0; 247 248 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 249 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 250 |JPEG_CGC_GATE__JPEG2_DEC_MASK 251 |JPEG_CGC_GATE__JPEG_ENC_MASK 252 |JPEG_CGC_GATE__JMCIF_MASK 253 |JPEG_CGC_GATE__JRBBM_MASK); 254 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 255 } 256 257 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev) 258 { 259 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 260 uint32_t data = 0; 261 int r = 0; 262 263 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 264 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 265 266 r = SOC15_WAIT_ON_RREG(JPEG, 0, 267 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 268 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 269 270 if (r) { 271 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 272 return r; 273 } 274 } 275 276 /* disable anti hang mechanism */ 277 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 278 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 279 280 /* keep the JPEG in static PG mode */ 281 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 282 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 283 284 return 0; 285 } 286 287 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev) 288 { 289 /* enable anti hang mechanism */ 290 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 291 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 292 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 293 294 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 295 uint32_t data = 0; 296 int r = 0; 297 298 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 299 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 300 301 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 302 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 303 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 304 305 if (r) { 306 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 307 return r; 308 } 309 } 310 311 return 0; 312 } 313 314 /** 315 * jpeg_v3_0_start - start JPEG block 316 * 317 * @adev: amdgpu_device pointer 318 * 319 * Setup and start the JPEG block 320 */ 321 static int jpeg_v3_0_start(struct amdgpu_device *adev) 322 { 323 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 324 int r; 325 326 if (adev->pm.dpm_enabled) 327 amdgpu_dpm_enable_jpeg(adev, true); 328 329 /* disable power gating */ 330 r = jpeg_v3_0_disable_static_power_gating(adev); 331 if (r) 332 return r; 333 334 /* JPEG disable CGC */ 335 jpeg_v3_0_disable_clock_gating(adev); 336 337 /* MJPEG global tiling registers */ 338 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 343 /* enable JMI channel */ 344 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 345 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 346 347 /* enable System Interrupt for JRBC */ 348 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 349 JPEG_SYS_INT_EN__DJRBC_MASK, 350 ~JPEG_SYS_INT_EN__DJRBC_MASK); 351 352 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 353 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 354 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 355 lower_32_bits(ring->gpu_addr)); 356 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 357 upper_32_bits(ring->gpu_addr)); 358 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 359 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 361 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 362 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 363 364 return 0; 365 } 366 367 /** 368 * jpeg_v3_0_stop - stop JPEG block 369 * 370 * @adev: amdgpu_device pointer 371 * 372 * stop the JPEG block 373 */ 374 static int jpeg_v3_0_stop(struct amdgpu_device *adev) 375 { 376 int r; 377 378 /* reset JMI */ 379 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 380 UVD_JMI_CNTL__SOFT_RESET_MASK, 381 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 382 383 jpeg_v3_0_enable_clock_gating(adev); 384 385 /* enable power gating */ 386 r = jpeg_v3_0_enable_static_power_gating(adev); 387 if (r) 388 return r; 389 390 if (adev->pm.dpm_enabled) 391 amdgpu_dpm_enable_jpeg(adev, false); 392 393 return 0; 394 } 395 396 /** 397 * jpeg_v3_0_dec_ring_get_rptr - get read pointer 398 * 399 * @ring: amdgpu_ring pointer 400 * 401 * Returns the current hardware read pointer 402 */ 403 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 407 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 408 } 409 410 /** 411 * jpeg_v3_0_dec_ring_get_wptr - get write pointer 412 * 413 * @ring: amdgpu_ring pointer 414 * 415 * Returns the current hardware write pointer 416 */ 417 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 418 { 419 struct amdgpu_device *adev = ring->adev; 420 421 if (ring->use_doorbell) 422 return adev->wb.wb[ring->wptr_offs]; 423 else 424 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 425 } 426 427 /** 428 * jpeg_v3_0_dec_ring_set_wptr - set write pointer 429 * 430 * @ring: amdgpu_ring pointer 431 * 432 * Commits the write pointer to the hardware 433 */ 434 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 435 { 436 struct amdgpu_device *adev = ring->adev; 437 438 if (ring->use_doorbell) { 439 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 440 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 441 } else { 442 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 443 } 444 } 445 446 static bool jpeg_v3_0_is_idle(void *handle) 447 { 448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 449 int ret = 1; 450 451 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 452 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 453 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 454 455 return ret; 456 } 457 458 static int jpeg_v3_0_wait_for_idle(void *handle) 459 { 460 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 461 462 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, 463 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 464 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 465 } 466 467 static int jpeg_v3_0_set_clockgating_state(void *handle, 468 enum amd_clockgating_state state) 469 { 470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 472 473 if (enable) { 474 if (!jpeg_v3_0_is_idle(handle)) 475 return -EBUSY; 476 jpeg_v3_0_enable_clock_gating(adev); 477 } else { 478 jpeg_v3_0_disable_clock_gating(adev); 479 } 480 481 return 0; 482 } 483 484 static int jpeg_v3_0_set_powergating_state(void *handle, 485 enum amd_powergating_state state) 486 { 487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 488 int ret; 489 490 if(state == adev->jpeg.cur_state) 491 return 0; 492 493 if (state == AMD_PG_STATE_GATE) 494 ret = jpeg_v3_0_stop(adev); 495 else 496 ret = jpeg_v3_0_start(adev); 497 498 if(!ret) 499 adev->jpeg.cur_state = state; 500 501 return ret; 502 } 503 504 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev, 505 struct amdgpu_irq_src *source, 506 unsigned type, 507 enum amdgpu_interrupt_state state) 508 { 509 return 0; 510 } 511 512 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev, 513 struct amdgpu_irq_src *source, 514 struct amdgpu_iv_entry *entry) 515 { 516 DRM_DEBUG("IH: JPEG TRAP\n"); 517 518 switch (entry->src_id) { 519 case VCN_2_0__SRCID__JPEG_DECODE: 520 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 521 break; 522 default: 523 DRM_ERROR("Unhandled interrupt: %d %d\n", 524 entry->src_id, entry->src_data[0]); 525 break; 526 } 527 528 return 0; 529 } 530 531 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { 532 .name = "jpeg_v3_0", 533 .early_init = jpeg_v3_0_early_init, 534 .late_init = NULL, 535 .sw_init = jpeg_v3_0_sw_init, 536 .sw_fini = jpeg_v3_0_sw_fini, 537 .hw_init = jpeg_v3_0_hw_init, 538 .hw_fini = jpeg_v3_0_hw_fini, 539 .suspend = jpeg_v3_0_suspend, 540 .resume = jpeg_v3_0_resume, 541 .is_idle = jpeg_v3_0_is_idle, 542 .wait_for_idle = jpeg_v3_0_wait_for_idle, 543 .check_soft_reset = NULL, 544 .pre_soft_reset = NULL, 545 .soft_reset = NULL, 546 .post_soft_reset = NULL, 547 .set_clockgating_state = jpeg_v3_0_set_clockgating_state, 548 .set_powergating_state = jpeg_v3_0_set_powergating_state, 549 }; 550 551 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { 552 .type = AMDGPU_RING_TYPE_VCN_JPEG, 553 .align_mask = 0xf, 554 .vmhub = AMDGPU_MMHUB_0, 555 .get_rptr = jpeg_v3_0_dec_ring_get_rptr, 556 .get_wptr = jpeg_v3_0_dec_ring_get_wptr, 557 .set_wptr = jpeg_v3_0_dec_ring_set_wptr, 558 .emit_frame_size = 559 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 560 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 561 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */ 562 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */ 563 8 + 16, 564 .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */ 565 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 566 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 567 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 568 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 569 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 570 .insert_nop = jpeg_v2_0_dec_ring_nop, 571 .insert_start = jpeg_v2_0_dec_ring_insert_start, 572 .insert_end = jpeg_v2_0_dec_ring_insert_end, 573 .pad_ib = amdgpu_ring_generic_pad_ib, 574 .begin_use = amdgpu_jpeg_ring_begin_use, 575 .end_use = amdgpu_jpeg_ring_end_use, 576 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 577 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 578 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 579 }; 580 581 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 582 { 583 adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs; 584 DRM_INFO("JPEG decode is enabled in VM mode\n"); 585 } 586 587 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = { 588 .set = jpeg_v3_0_set_interrupt_state, 589 .process = jpeg_v3_0_process_interrupt, 590 }; 591 592 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev) 593 { 594 adev->jpeg.inst->irq.num_types = 1; 595 adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs; 596 } 597 598 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block = 599 { 600 .type = AMD_IP_BLOCK_TYPE_JPEG, 601 .major = 3, 602 .minor = 0, 603 .rev = 0, 604 .funcs = &jpeg_v3_0_ip_funcs, 605 }; 606