1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu.h"
25 #include "amdgpu_jpeg.h"
26 #include "amdgpu_pm.h"
27 #include "soc15.h"
28 #include "soc15d.h"
29 #include "jpeg_v2_0.h"
30 
31 #include "vcn/vcn_3_0_0_offset.h"
32 #include "vcn/vcn_3_0_0_sh_mask.h"
33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
34 
35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET	0x401f
36 
37 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
38 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
39 static int jpeg_v3_0_set_powergating_state(void *handle,
40 				enum amd_powergating_state state);
41 
42 /**
43  * jpeg_v3_0_early_init - set function pointers
44  *
45  * @handle: amdgpu_device pointer
46  *
47  * Set ring and irq function pointers
48  */
49 static int jpeg_v3_0_early_init(void *handle)
50 {
51 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
52 	u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
53 
54 	if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
55 		return -ENOENT;
56 
57 	adev->jpeg.num_jpeg_inst = 1;
58 
59 	jpeg_v3_0_set_dec_ring_funcs(adev);
60 	jpeg_v3_0_set_irq_funcs(adev);
61 
62 	return 0;
63 }
64 
65 /**
66  * jpeg_v3_0_sw_init - sw init for JPEG block
67  *
68  * @handle: amdgpu_device pointer
69  *
70  * Load firmware and sw initialization
71  */
72 static int jpeg_v3_0_sw_init(void *handle)
73 {
74 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
75 	struct amdgpu_ring *ring;
76 	int r;
77 
78 	/* JPEG TRAP */
79 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
80 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
81 	if (r)
82 		return r;
83 
84 	r = amdgpu_jpeg_sw_init(adev);
85 	if (r)
86 		return r;
87 
88 	r = amdgpu_jpeg_resume(adev);
89 	if (r)
90 		return r;
91 
92 	ring = &adev->jpeg.inst->ring_dec;
93 	ring->use_doorbell = true;
94 	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
95 	sprintf(ring->name, "jpeg_dec");
96 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
97 			     AMDGPU_RING_PRIO_DEFAULT);
98 	if (r)
99 		return r;
100 
101 	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
102 	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
103 
104 	return 0;
105 }
106 
107 /**
108  * jpeg_v3_0_sw_fini - sw fini for JPEG block
109  *
110  * @handle: amdgpu_device pointer
111  *
112  * JPEG suspend and free up sw allocation
113  */
114 static int jpeg_v3_0_sw_fini(void *handle)
115 {
116 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
117 	int r;
118 
119 	r = amdgpu_jpeg_suspend(adev);
120 	if (r)
121 		return r;
122 
123 	r = amdgpu_jpeg_sw_fini(adev);
124 
125 	return r;
126 }
127 
128 /**
129  * jpeg_v3_0_hw_init - start and test JPEG block
130  *
131  * @handle: amdgpu_device pointer
132  *
133  */
134 static int jpeg_v3_0_hw_init(void *handle)
135 {
136 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
137 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
138 	int r;
139 
140 	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
141 		(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
142 
143 	r = amdgpu_ring_test_helper(ring);
144 	if (r)
145 		return r;
146 
147 	DRM_INFO("JPEG decode initialized successfully.\n");
148 
149 	return 0;
150 }
151 
152 /**
153  * jpeg_v3_0_hw_fini - stop the hardware block
154  *
155  * @handle: amdgpu_device pointer
156  *
157  * Stop the JPEG block, mark ring as not ready any more
158  */
159 static int jpeg_v3_0_hw_fini(void *handle)
160 {
161 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
162 	struct amdgpu_ring *ring;
163 
164 	ring = &adev->jpeg.inst->ring_dec;
165 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
166 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
167 		jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
168 
169 	ring->sched.ready = false;
170 
171 	return 0;
172 }
173 
174 /**
175  * jpeg_v3_0_suspend - suspend JPEG block
176  *
177  * @handle: amdgpu_device pointer
178  *
179  * HW fini and suspend JPEG block
180  */
181 static int jpeg_v3_0_suspend(void *handle)
182 {
183 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
184 	int r;
185 
186 	r = jpeg_v3_0_hw_fini(adev);
187 	if (r)
188 		return r;
189 
190 	r = amdgpu_jpeg_suspend(adev);
191 
192 	return r;
193 }
194 
195 /**
196  * jpeg_v3_0_resume - resume JPEG block
197  *
198  * @handle: amdgpu_device pointer
199  *
200  * Resume firmware and hw init JPEG block
201  */
202 static int jpeg_v3_0_resume(void *handle)
203 {
204 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
205 	int r;
206 
207 	r = amdgpu_jpeg_resume(adev);
208 	if (r)
209 		return r;
210 
211 	r = jpeg_v3_0_hw_init(adev);
212 
213 	return r;
214 }
215 
216 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
217 {
218 	uint32_t data = 0;
219 
220 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
221 	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
222 		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
223 	else
224 		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
225 
226 	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
227 	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
228 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
229 
230 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
231 	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
232 		| JPEG_CGC_GATE__JPEG2_DEC_MASK
233 		| JPEG_CGC_GATE__JPEG_ENC_MASK
234 		| JPEG_CGC_GATE__JMCIF_MASK
235 		| JPEG_CGC_GATE__JRBBM_MASK);
236 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
237 
238 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
239 	data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
240 		| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
241 		| JPEG_CGC_CTRL__JMCIF_MODE_MASK
242 		| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
243 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
244 }
245 
246 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
247 {
248 	uint32_t data = 0;
249 
250 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
251 	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
252 		|JPEG_CGC_GATE__JPEG2_DEC_MASK
253 		|JPEG_CGC_GATE__JPEG_ENC_MASK
254 		|JPEG_CGC_GATE__JMCIF_MASK
255 		|JPEG_CGC_GATE__JRBBM_MASK);
256 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
257 }
258 
259 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
260 {
261 	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
262 		uint32_t data = 0;
263 		int r = 0;
264 
265 		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
266 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
267 
268 		r = SOC15_WAIT_ON_RREG(JPEG, 0,
269 			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
270 			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
271 
272 		if (r) {
273 			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
274 			return r;
275 		}
276 	}
277 
278 	/* disable anti hang mechanism */
279 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
280 		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
281 
282 	/* keep the JPEG in static PG mode */
283 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
284 		~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
285 
286 	return 0;
287 }
288 
289 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
290 {
291 	/* enable anti hang mechanism */
292 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
293 		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
294 		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
295 
296 	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
297 		uint32_t data = 0;
298 		int r = 0;
299 
300 		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
301 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
302 
303 		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
304 			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
305 			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
306 
307 		if (r) {
308 			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
309 			return r;
310 		}
311 	}
312 
313 	return 0;
314 }
315 
316 /**
317  * jpeg_v3_0_start - start JPEG block
318  *
319  * @adev: amdgpu_device pointer
320  *
321  * Setup and start the JPEG block
322  */
323 static int jpeg_v3_0_start(struct amdgpu_device *adev)
324 {
325 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
326 	int r;
327 
328 	if (adev->pm.dpm_enabled)
329 		amdgpu_dpm_enable_jpeg(adev, true);
330 
331 	/* disable power gating */
332 	r = jpeg_v3_0_disable_static_power_gating(adev);
333 	if (r)
334 		return r;
335 
336 	/* JPEG disable CGC */
337 	jpeg_v3_0_disable_clock_gating(adev);
338 
339 	/* MJPEG global tiling registers */
340 	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
341 		adev->gfx.config.gb_addr_config);
342 	WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
343 		adev->gfx.config.gb_addr_config);
344 
345 	/* enable JMI channel */
346 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
347 		~UVD_JMI_CNTL__SOFT_RESET_MASK);
348 
349 	/* enable System Interrupt for JRBC */
350 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
351 		JPEG_SYS_INT_EN__DJRBC_MASK,
352 		~JPEG_SYS_INT_EN__DJRBC_MASK);
353 
354 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
355 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
356 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
357 		lower_32_bits(ring->gpu_addr));
358 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
359 		upper_32_bits(ring->gpu_addr));
360 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
361 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
362 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
363 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
364 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
365 
366 	return 0;
367 }
368 
369 /**
370  * jpeg_v3_0_stop - stop JPEG block
371  *
372  * @adev: amdgpu_device pointer
373  *
374  * stop the JPEG block
375  */
376 static int jpeg_v3_0_stop(struct amdgpu_device *adev)
377 {
378 	int r;
379 
380 	/* reset JMI */
381 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
382 		UVD_JMI_CNTL__SOFT_RESET_MASK,
383 		~UVD_JMI_CNTL__SOFT_RESET_MASK);
384 
385 	jpeg_v3_0_enable_clock_gating(adev);
386 
387 	/* enable power gating */
388 	r = jpeg_v3_0_enable_static_power_gating(adev);
389 	if (r)
390 		return r;
391 
392 	if (adev->pm.dpm_enabled)
393 		amdgpu_dpm_enable_jpeg(adev, false);
394 
395 	return 0;
396 }
397 
398 /**
399  * jpeg_v3_0_dec_ring_get_rptr - get read pointer
400  *
401  * @ring: amdgpu_ring pointer
402  *
403  * Returns the current hardware read pointer
404  */
405 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
406 {
407 	struct amdgpu_device *adev = ring->adev;
408 
409 	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
410 }
411 
412 /**
413  * jpeg_v3_0_dec_ring_get_wptr - get write pointer
414  *
415  * @ring: amdgpu_ring pointer
416  *
417  * Returns the current hardware write pointer
418  */
419 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
420 {
421 	struct amdgpu_device *adev = ring->adev;
422 
423 	if (ring->use_doorbell)
424 		return adev->wb.wb[ring->wptr_offs];
425 	else
426 		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
427 }
428 
429 /**
430  * jpeg_v3_0_dec_ring_set_wptr - set write pointer
431  *
432  * @ring: amdgpu_ring pointer
433  *
434  * Commits the write pointer to the hardware
435  */
436 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
437 {
438 	struct amdgpu_device *adev = ring->adev;
439 
440 	if (ring->use_doorbell) {
441 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
442 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
443 	} else {
444 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
445 	}
446 }
447 
448 static bool jpeg_v3_0_is_idle(void *handle)
449 {
450 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
451 	int ret = 1;
452 
453 	ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
454 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
455 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
456 
457 	return ret;
458 }
459 
460 static int jpeg_v3_0_wait_for_idle(void *handle)
461 {
462 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
463 
464 	return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
465 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
466 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
467 }
468 
469 static int jpeg_v3_0_set_clockgating_state(void *handle,
470 					  enum amd_clockgating_state state)
471 {
472 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
474 
475 	if (enable) {
476 		if (!jpeg_v3_0_is_idle(handle))
477 			return -EBUSY;
478 		jpeg_v3_0_enable_clock_gating(adev);
479 	} else {
480 		jpeg_v3_0_disable_clock_gating(adev);
481 	}
482 
483 	return 0;
484 }
485 
486 static int jpeg_v3_0_set_powergating_state(void *handle,
487 					  enum amd_powergating_state state)
488 {
489 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
490 	int ret;
491 
492 	if(state == adev->jpeg.cur_state)
493 		return 0;
494 
495 	if (state == AMD_PG_STATE_GATE)
496 		ret = jpeg_v3_0_stop(adev);
497 	else
498 		ret = jpeg_v3_0_start(adev);
499 
500 	if(!ret)
501 		adev->jpeg.cur_state = state;
502 
503 	return ret;
504 }
505 
506 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
507 					struct amdgpu_irq_src *source,
508 					unsigned type,
509 					enum amdgpu_interrupt_state state)
510 {
511 	return 0;
512 }
513 
514 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
515 				      struct amdgpu_irq_src *source,
516 				      struct amdgpu_iv_entry *entry)
517 {
518 	DRM_DEBUG("IH: JPEG TRAP\n");
519 
520 	switch (entry->src_id) {
521 	case VCN_2_0__SRCID__JPEG_DECODE:
522 		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
523 		break;
524 	default:
525 		DRM_ERROR("Unhandled interrupt: %d %d\n",
526 			  entry->src_id, entry->src_data[0]);
527 		break;
528 	}
529 
530 	return 0;
531 }
532 
533 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
534 	.name = "jpeg_v3_0",
535 	.early_init = jpeg_v3_0_early_init,
536 	.late_init = NULL,
537 	.sw_init = jpeg_v3_0_sw_init,
538 	.sw_fini = jpeg_v3_0_sw_fini,
539 	.hw_init = jpeg_v3_0_hw_init,
540 	.hw_fini = jpeg_v3_0_hw_fini,
541 	.suspend = jpeg_v3_0_suspend,
542 	.resume = jpeg_v3_0_resume,
543 	.is_idle = jpeg_v3_0_is_idle,
544 	.wait_for_idle = jpeg_v3_0_wait_for_idle,
545 	.check_soft_reset = NULL,
546 	.pre_soft_reset = NULL,
547 	.soft_reset = NULL,
548 	.post_soft_reset = NULL,
549 	.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
550 	.set_powergating_state = jpeg_v3_0_set_powergating_state,
551 };
552 
553 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
554 	.type = AMDGPU_RING_TYPE_VCN_JPEG,
555 	.align_mask = 0xf,
556 	.vmhub = AMDGPU_MMHUB_0,
557 	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
558 	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
559 	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
560 	.emit_frame_size =
561 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
562 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
563 		8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
564 		18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
565 		8 + 16,
566 	.emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
567 	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
568 	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
569 	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
570 	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
571 	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
572 	.insert_nop = jpeg_v2_0_dec_ring_nop,
573 	.insert_start = jpeg_v2_0_dec_ring_insert_start,
574 	.insert_end = jpeg_v2_0_dec_ring_insert_end,
575 	.pad_ib = amdgpu_ring_generic_pad_ib,
576 	.begin_use = amdgpu_jpeg_ring_begin_use,
577 	.end_use = amdgpu_jpeg_ring_end_use,
578 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
579 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
580 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
581 };
582 
583 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
584 {
585 	adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
586 	DRM_INFO("JPEG decode is enabled in VM mode\n");
587 }
588 
589 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
590 	.set = jpeg_v3_0_set_interrupt_state,
591 	.process = jpeg_v3_0_process_interrupt,
592 };
593 
594 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
595 {
596 	adev->jpeg.inst->irq.num_types = 1;
597 	adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
598 }
599 
600 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
601 {
602 	.type = AMD_IP_BLOCK_TYPE_JPEG,
603 	.major = 3,
604 	.minor = 0,
605 	.rev = 0,
606 	.funcs = &jpeg_v3_0_ip_funcs,
607 };
608