1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v2_5.h" 30 31 #include "vcn/vcn_2_5_offset.h" 32 #include "vcn/vcn_2_5_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 38 39 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 40 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); 41 static int jpeg_v2_5_set_powergating_state(void *handle, 42 enum amd_powergating_state state); 43 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev); 44 45 static int amdgpu_ih_clientid_jpeg[] = { 46 SOC15_IH_CLIENTID_VCN, 47 SOC15_IH_CLIENTID_VCN1 48 }; 49 50 /** 51 * jpeg_v2_5_early_init - set function pointers 52 * 53 * @handle: amdgpu_device pointer 54 * 55 * Set ring and irq function pointers 56 */ 57 static int jpeg_v2_5_early_init(void *handle) 58 { 59 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 60 u32 harvest; 61 int i; 62 63 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; 64 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 65 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); 66 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 67 adev->jpeg.harvest_config |= 1 << i; 68 } 69 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | 70 AMDGPU_JPEG_HARVEST_JPEG1)) 71 return -ENOENT; 72 73 jpeg_v2_5_set_dec_ring_funcs(adev); 74 jpeg_v2_5_set_irq_funcs(adev); 75 jpeg_v2_5_set_ras_funcs(adev); 76 77 return 0; 78 } 79 80 /** 81 * jpeg_v2_5_sw_init - sw init for JPEG block 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Load firmware and sw initialization 86 */ 87 static int jpeg_v2_5_sw_init(void *handle) 88 { 89 struct amdgpu_ring *ring; 90 int i, r; 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 93 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 94 if (adev->jpeg.harvest_config & (1 << i)) 95 continue; 96 97 /* JPEG TRAP */ 98 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 99 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 100 if (r) 101 return r; 102 } 103 104 r = amdgpu_jpeg_sw_init(adev); 105 if (r) 106 return r; 107 108 r = amdgpu_jpeg_resume(adev); 109 if (r) 110 return r; 111 112 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 113 if (adev->jpeg.harvest_config & (1 << i)) 114 continue; 115 116 ring = &adev->jpeg.inst[i].ring_dec; 117 ring->use_doorbell = true; 118 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 119 sprintf(ring->name, "jpeg_dec_%d", i); 120 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 121 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 122 if (r) 123 return r; 124 125 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 126 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); 127 } 128 129 return 0; 130 } 131 132 /** 133 * jpeg_v2_5_sw_fini - sw fini for JPEG block 134 * 135 * @handle: amdgpu_device pointer 136 * 137 * JPEG suspend and free up sw allocation 138 */ 139 static int jpeg_v2_5_sw_fini(void *handle) 140 { 141 int r; 142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 143 144 r = amdgpu_jpeg_suspend(adev); 145 if (r) 146 return r; 147 148 r = amdgpu_jpeg_sw_fini(adev); 149 150 return r; 151 } 152 153 /** 154 * jpeg_v2_5_hw_init - start and test JPEG block 155 * 156 * @handle: amdgpu_device pointer 157 * 158 */ 159 static int jpeg_v2_5_hw_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct amdgpu_ring *ring; 163 int i, r; 164 165 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 166 if (adev->jpeg.harvest_config & (1 << i)) 167 continue; 168 169 ring = &adev->jpeg.inst[i].ring_dec; 170 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 171 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 172 173 r = amdgpu_ring_test_helper(ring); 174 if (r) 175 return r; 176 } 177 178 DRM_INFO("JPEG decode initialized successfully.\n"); 179 180 return 0; 181 } 182 183 /** 184 * jpeg_v2_5_hw_fini - stop the hardware block 185 * 186 * @handle: amdgpu_device pointer 187 * 188 * Stop the JPEG block, mark ring as not ready any more 189 */ 190 static int jpeg_v2_5_hw_fini(void *handle) 191 { 192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 193 int i; 194 195 cancel_delayed_work_sync(&adev->vcn.idle_work); 196 197 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 198 if (adev->jpeg.harvest_config & (1 << i)) 199 continue; 200 201 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 202 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) 203 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 204 } 205 206 return 0; 207 } 208 209 /** 210 * jpeg_v2_5_suspend - suspend JPEG block 211 * 212 * @handle: amdgpu_device pointer 213 * 214 * HW fini and suspend JPEG block 215 */ 216 static int jpeg_v2_5_suspend(void *handle) 217 { 218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 219 int r; 220 221 r = jpeg_v2_5_hw_fini(adev); 222 if (r) 223 return r; 224 225 r = amdgpu_jpeg_suspend(adev); 226 227 return r; 228 } 229 230 /** 231 * jpeg_v2_5_resume - resume JPEG block 232 * 233 * @handle: amdgpu_device pointer 234 * 235 * Resume firmware and hw init JPEG block 236 */ 237 static int jpeg_v2_5_resume(void *handle) 238 { 239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 240 int r; 241 242 r = amdgpu_jpeg_resume(adev); 243 if (r) 244 return r; 245 246 r = jpeg_v2_5_hw_init(adev); 247 248 return r; 249 } 250 251 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 252 { 253 uint32_t data; 254 255 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 256 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 257 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 258 else 259 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 260 261 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 262 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 263 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 264 265 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 266 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 267 | JPEG_CGC_GATE__JPEG2_DEC_MASK 268 | JPEG_CGC_GATE__JMCIF_MASK 269 | JPEG_CGC_GATE__JRBBM_MASK); 270 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 271 272 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 273 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 274 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 275 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 276 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 277 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 278 } 279 280 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 281 { 282 uint32_t data; 283 284 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 285 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 286 |JPEG_CGC_GATE__JPEG2_DEC_MASK 287 |JPEG_CGC_GATE__JPEG_ENC_MASK 288 |JPEG_CGC_GATE__JMCIF_MASK 289 |JPEG_CGC_GATE__JRBBM_MASK); 290 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 291 } 292 293 /** 294 * jpeg_v2_5_start - start JPEG block 295 * 296 * @adev: amdgpu_device pointer 297 * 298 * Setup and start the JPEG block 299 */ 300 static int jpeg_v2_5_start(struct amdgpu_device *adev) 301 { 302 struct amdgpu_ring *ring; 303 int i; 304 305 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 306 if (adev->jpeg.harvest_config & (1 << i)) 307 continue; 308 309 ring = &adev->jpeg.inst[i].ring_dec; 310 /* disable anti hang mechanism */ 311 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, 312 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 313 314 /* JPEG disable CGC */ 315 jpeg_v2_5_disable_clock_gating(adev, i); 316 317 /* MJPEG global tiling registers */ 318 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, 319 adev->gfx.config.gb_addr_config); 320 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, 321 adev->gfx.config.gb_addr_config); 322 323 /* enable JMI channel */ 324 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, 325 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 326 327 /* enable System Interrupt for JRBC */ 328 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), 329 JPEG_SYS_INT_EN__DJRBC_MASK, 330 ~JPEG_SYS_INT_EN__DJRBC_MASK); 331 332 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); 333 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 334 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 335 lower_32_bits(ring->gpu_addr)); 336 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 337 upper_32_bits(ring->gpu_addr)); 338 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); 339 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 340 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); 341 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 342 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 343 } 344 345 return 0; 346 } 347 348 /** 349 * jpeg_v2_5_stop - stop JPEG block 350 * 351 * @adev: amdgpu_device pointer 352 * 353 * stop the JPEG block 354 */ 355 static int jpeg_v2_5_stop(struct amdgpu_device *adev) 356 { 357 int i; 358 359 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 360 if (adev->jpeg.harvest_config & (1 << i)) 361 continue; 362 363 /* reset JMI */ 364 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 365 UVD_JMI_CNTL__SOFT_RESET_MASK, 366 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 367 368 jpeg_v2_5_enable_clock_gating(adev, i); 369 370 /* enable anti hang mechanism */ 371 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 372 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 373 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 374 } 375 376 return 0; 377 } 378 379 /** 380 * jpeg_v2_5_dec_ring_get_rptr - get read pointer 381 * 382 * @ring: amdgpu_ring pointer 383 * 384 * Returns the current hardware read pointer 385 */ 386 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 387 { 388 struct amdgpu_device *adev = ring->adev; 389 390 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); 391 } 392 393 /** 394 * jpeg_v2_5_dec_ring_get_wptr - get write pointer 395 * 396 * @ring: amdgpu_ring pointer 397 * 398 * Returns the current hardware write pointer 399 */ 400 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 401 { 402 struct amdgpu_device *adev = ring->adev; 403 404 if (ring->use_doorbell) 405 return adev->wb.wb[ring->wptr_offs]; 406 else 407 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 408 } 409 410 /** 411 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 412 * 413 * @ring: amdgpu_ring pointer 414 * 415 * Commits the write pointer to the hardware 416 */ 417 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 418 { 419 struct amdgpu_device *adev = ring->adev; 420 421 if (ring->use_doorbell) { 422 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 423 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 424 } else { 425 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 426 } 427 } 428 429 /** 430 * jpeg_v2_6_dec_ring_insert_start - insert a start command 431 * 432 * @ring: amdgpu_ring pointer 433 * 434 * Write a start command to the ring. 435 */ 436 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring) 437 { 438 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 439 0, 0, PACKETJ_TYPE0)); 440 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 441 442 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 443 0, 0, PACKETJ_TYPE0)); 444 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); 445 } 446 447 /** 448 * jpeg_v2_6_dec_ring_insert_end - insert a end command 449 * 450 * @ring: amdgpu_ring pointer 451 * 452 * Write a end command to the ring. 453 */ 454 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring) 455 { 456 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 457 0, 0, PACKETJ_TYPE0)); 458 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 459 460 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 461 0, 0, PACKETJ_TYPE0)); 462 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); 463 } 464 465 static bool jpeg_v2_5_is_idle(void *handle) 466 { 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 int i, ret = 1; 469 470 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 471 if (adev->jpeg.harvest_config & (1 << i)) 472 continue; 473 474 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & 475 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 476 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 477 } 478 479 return ret; 480 } 481 482 static int jpeg_v2_5_wait_for_idle(void *handle) 483 { 484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 485 int i, ret; 486 487 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 488 if (adev->jpeg.harvest_config & (1 << i)) 489 continue; 490 491 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, 492 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 493 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 494 if (ret) 495 return ret; 496 } 497 498 return 0; 499 } 500 501 static int jpeg_v2_5_set_clockgating_state(void *handle, 502 enum amd_clockgating_state state) 503 { 504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 505 bool enable = (state == AMD_CG_STATE_GATE); 506 int i; 507 508 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 509 if (adev->jpeg.harvest_config & (1 << i)) 510 continue; 511 512 if (enable) { 513 if (!jpeg_v2_5_is_idle(handle)) 514 return -EBUSY; 515 jpeg_v2_5_enable_clock_gating(adev, i); 516 } else { 517 jpeg_v2_5_disable_clock_gating(adev, i); 518 } 519 } 520 521 return 0; 522 } 523 524 static int jpeg_v2_5_set_powergating_state(void *handle, 525 enum amd_powergating_state state) 526 { 527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 528 int ret; 529 530 if(state == adev->jpeg.cur_state) 531 return 0; 532 533 if (state == AMD_PG_STATE_GATE) 534 ret = jpeg_v2_5_stop(adev); 535 else 536 ret = jpeg_v2_5_start(adev); 537 538 if(!ret) 539 adev->jpeg.cur_state = state; 540 541 return ret; 542 } 543 544 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev, 545 struct amdgpu_irq_src *source, 546 unsigned type, 547 enum amdgpu_interrupt_state state) 548 { 549 return 0; 550 } 551 552 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev, 553 struct amdgpu_irq_src *source, 554 struct amdgpu_iv_entry *entry) 555 { 556 uint32_t ip_instance; 557 558 switch (entry->client_id) { 559 case SOC15_IH_CLIENTID_VCN: 560 ip_instance = 0; 561 break; 562 case SOC15_IH_CLIENTID_VCN1: 563 ip_instance = 1; 564 break; 565 default: 566 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 567 return 0; 568 } 569 570 DRM_DEBUG("IH: JPEG TRAP\n"); 571 572 switch (entry->src_id) { 573 case VCN_2_0__SRCID__JPEG_DECODE: 574 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec); 575 break; 576 default: 577 DRM_ERROR("Unhandled interrupt: %d %d\n", 578 entry->src_id, entry->src_data[0]); 579 break; 580 } 581 582 return 0; 583 } 584 585 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 586 .name = "jpeg_v2_5", 587 .early_init = jpeg_v2_5_early_init, 588 .late_init = NULL, 589 .sw_init = jpeg_v2_5_sw_init, 590 .sw_fini = jpeg_v2_5_sw_fini, 591 .hw_init = jpeg_v2_5_hw_init, 592 .hw_fini = jpeg_v2_5_hw_fini, 593 .suspend = jpeg_v2_5_suspend, 594 .resume = jpeg_v2_5_resume, 595 .is_idle = jpeg_v2_5_is_idle, 596 .wait_for_idle = jpeg_v2_5_wait_for_idle, 597 .check_soft_reset = NULL, 598 .pre_soft_reset = NULL, 599 .soft_reset = NULL, 600 .post_soft_reset = NULL, 601 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 602 .set_powergating_state = jpeg_v2_5_set_powergating_state, 603 }; 604 605 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 606 .name = "jpeg_v2_6", 607 .early_init = jpeg_v2_5_early_init, 608 .late_init = NULL, 609 .sw_init = jpeg_v2_5_sw_init, 610 .sw_fini = jpeg_v2_5_sw_fini, 611 .hw_init = jpeg_v2_5_hw_init, 612 .hw_fini = jpeg_v2_5_hw_fini, 613 .suspend = jpeg_v2_5_suspend, 614 .resume = jpeg_v2_5_resume, 615 .is_idle = jpeg_v2_5_is_idle, 616 .wait_for_idle = jpeg_v2_5_wait_for_idle, 617 .check_soft_reset = NULL, 618 .pre_soft_reset = NULL, 619 .soft_reset = NULL, 620 .post_soft_reset = NULL, 621 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 622 .set_powergating_state = jpeg_v2_5_set_powergating_state, 623 }; 624 625 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { 626 .type = AMDGPU_RING_TYPE_VCN_JPEG, 627 .align_mask = 0xf, 628 .vmhub = AMDGPU_MMHUB_1, 629 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 630 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 631 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 632 .emit_frame_size = 633 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 634 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 635 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 636 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 637 8 + 16, 638 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 639 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 640 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 641 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 642 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 643 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 644 .insert_nop = jpeg_v2_0_dec_ring_nop, 645 .insert_start = jpeg_v2_0_dec_ring_insert_start, 646 .insert_end = jpeg_v2_0_dec_ring_insert_end, 647 .pad_ib = amdgpu_ring_generic_pad_ib, 648 .begin_use = amdgpu_jpeg_ring_begin_use, 649 .end_use = amdgpu_jpeg_ring_end_use, 650 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 651 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 652 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 653 }; 654 655 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { 656 .type = AMDGPU_RING_TYPE_VCN_JPEG, 657 .align_mask = 0xf, 658 .vmhub = AMDGPU_MMHUB_0, 659 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 660 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 661 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 662 .emit_frame_size = 663 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 664 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 665 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 666 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 667 8 + 16, 668 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 669 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 670 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 671 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 672 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 673 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 674 .insert_nop = jpeg_v2_0_dec_ring_nop, 675 .insert_start = jpeg_v2_6_dec_ring_insert_start, 676 .insert_end = jpeg_v2_6_dec_ring_insert_end, 677 .pad_ib = amdgpu_ring_generic_pad_ib, 678 .begin_use = amdgpu_jpeg_ring_begin_use, 679 .end_use = amdgpu_jpeg_ring_end_use, 680 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 681 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 682 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 683 }; 684 685 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 686 { 687 int i; 688 689 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 690 if (adev->jpeg.harvest_config & (1 << i)) 691 continue; 692 if (adev->asic_type == CHIP_ARCTURUS) 693 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; 694 else /* CHIP_ALDEBARAN */ 695 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs; 696 adev->jpeg.inst[i].ring_dec.me = i; 697 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); 698 } 699 } 700 701 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = { 702 .set = jpeg_v2_5_set_interrupt_state, 703 .process = jpeg_v2_5_process_interrupt, 704 }; 705 706 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) 707 { 708 int i; 709 710 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 711 if (adev->jpeg.harvest_config & (1 << i)) 712 continue; 713 714 adev->jpeg.inst[i].irq.num_types = 1; 715 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; 716 } 717 } 718 719 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = 720 { 721 .type = AMD_IP_BLOCK_TYPE_JPEG, 722 .major = 2, 723 .minor = 5, 724 .rev = 0, 725 .funcs = &jpeg_v2_5_ip_funcs, 726 }; 727 728 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = 729 { 730 .type = AMD_IP_BLOCK_TYPE_JPEG, 731 .major = 2, 732 .minor = 6, 733 .rev = 0, 734 .funcs = &jpeg_v2_6_ip_funcs, 735 }; 736 737 static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 738 uint32_t instance, uint32_t sub_block) 739 { 740 uint32_t poison_stat = 0, reg_value = 0; 741 742 switch (sub_block) { 743 case AMDGPU_JPEG_V2_6_JPEG0: 744 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS); 745 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 746 break; 747 case AMDGPU_JPEG_V2_6_JPEG1: 748 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS); 749 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 750 break; 751 default: 752 break; 753 } 754 755 if (poison_stat) 756 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 757 instance, sub_block); 758 759 return poison_stat; 760 } 761 762 static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev) 763 { 764 uint32_t inst = 0, sub = 0, poison_stat = 0; 765 766 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 767 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++) 768 poison_stat += 769 jpeg_v2_6_query_poison_by_instance(adev, inst, sub); 770 771 return !!poison_stat; 772 } 773 774 const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = { 775 .query_poison_status = jpeg_v2_6_query_ras_poison_status, 776 }; 777 778 static struct amdgpu_jpeg_ras jpeg_v2_6_ras = { 779 .ras_block = { 780 .hw_ops = &jpeg_v2_6_ras_hw_ops, 781 }, 782 }; 783 784 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev) 785 { 786 switch (adev->ip_versions[JPEG_HWIP][0]) { 787 case IP_VERSION(2, 6, 0): 788 adev->jpeg.ras = &jpeg_v2_6_ras; 789 break; 790 default: 791 break; 792 } 793 794 if (adev->jpeg.ras) { 795 amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block); 796 797 strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg"); 798 adev->jpeg.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; 799 adev->jpeg.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 800 adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm; 801 802 /* If don't define special ras_late_init function, use default ras_late_init */ 803 if (!adev->jpeg.ras->ras_block.ras_late_init) 804 adev->jpeg.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 805 } 806 } 807