1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 30 #include "vcn/vcn_2_5_offset.h" 31 #include "vcn/vcn_2_5_sh_mask.h" 32 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 33 34 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 35 36 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 37 38 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v2_5_set_powergating_state(void *handle, 41 enum amd_powergating_state state); 42 43 static int amdgpu_ih_clientid_jpeg[] = { 44 SOC15_IH_CLIENTID_VCN, 45 SOC15_IH_CLIENTID_VCN1 46 }; 47 48 /** 49 * jpeg_v2_5_early_init - set function pointers 50 * 51 * @handle: amdgpu_device pointer 52 * 53 * Set ring and irq function pointers 54 */ 55 static int jpeg_v2_5_early_init(void *handle) 56 { 57 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 58 u32 harvest; 59 int i; 60 61 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; 62 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 63 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); 64 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 65 adev->jpeg.harvest_config |= 1 << i; 66 } 67 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | 68 AMDGPU_JPEG_HARVEST_JPEG1)) 69 return -ENOENT; 70 71 jpeg_v2_5_set_dec_ring_funcs(adev); 72 jpeg_v2_5_set_irq_funcs(adev); 73 74 return 0; 75 } 76 77 /** 78 * jpeg_v2_5_sw_init - sw init for JPEG block 79 * 80 * @handle: amdgpu_device pointer 81 * 82 * Load firmware and sw initialization 83 */ 84 static int jpeg_v2_5_sw_init(void *handle) 85 { 86 struct amdgpu_ring *ring; 87 int i, r; 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 90 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 91 if (adev->jpeg.harvest_config & (1 << i)) 92 continue; 93 94 /* JPEG TRAP */ 95 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 96 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 97 if (r) 98 return r; 99 } 100 101 r = amdgpu_jpeg_sw_init(adev); 102 if (r) 103 return r; 104 105 r = amdgpu_jpeg_resume(adev); 106 if (r) 107 return r; 108 109 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 110 if (adev->jpeg.harvest_config & (1 << i)) 111 continue; 112 113 ring = &adev->jpeg.inst[i].ring_dec; 114 ring->use_doorbell = true; 115 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 116 sprintf(ring->name, "jpeg_dec_%d", i); 117 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 118 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 119 if (r) 120 return r; 121 122 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 123 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); 124 } 125 126 return 0; 127 } 128 129 /** 130 * jpeg_v2_5_sw_fini - sw fini for JPEG block 131 * 132 * @handle: amdgpu_device pointer 133 * 134 * JPEG suspend and free up sw allocation 135 */ 136 static int jpeg_v2_5_sw_fini(void *handle) 137 { 138 int r; 139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 140 141 r = amdgpu_jpeg_suspend(adev); 142 if (r) 143 return r; 144 145 r = amdgpu_jpeg_sw_fini(adev); 146 147 return r; 148 } 149 150 /** 151 * jpeg_v2_5_hw_init - start and test JPEG block 152 * 153 * @handle: amdgpu_device pointer 154 * 155 */ 156 static int jpeg_v2_5_hw_init(void *handle) 157 { 158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 159 struct amdgpu_ring *ring; 160 int i, r; 161 162 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 163 if (adev->jpeg.harvest_config & (1 << i)) 164 continue; 165 166 ring = &adev->jpeg.inst[i].ring_dec; 167 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 168 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 169 170 r = amdgpu_ring_test_helper(ring); 171 if (r) 172 return r; 173 } 174 175 DRM_INFO("JPEG decode initialized successfully.\n"); 176 177 return 0; 178 } 179 180 /** 181 * jpeg_v2_5_hw_fini - stop the hardware block 182 * 183 * @handle: amdgpu_device pointer 184 * 185 * Stop the JPEG block, mark ring as not ready any more 186 */ 187 static int jpeg_v2_5_hw_fini(void *handle) 188 { 189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 190 struct amdgpu_ring *ring; 191 int i; 192 193 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 194 if (adev->jpeg.harvest_config & (1 << i)) 195 continue; 196 197 ring = &adev->jpeg.inst[i].ring_dec; 198 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 199 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) 200 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 201 202 ring->sched.ready = false; 203 } 204 205 return 0; 206 } 207 208 /** 209 * jpeg_v2_5_suspend - suspend JPEG block 210 * 211 * @handle: amdgpu_device pointer 212 * 213 * HW fini and suspend JPEG block 214 */ 215 static int jpeg_v2_5_suspend(void *handle) 216 { 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 int r; 219 220 r = jpeg_v2_5_hw_fini(adev); 221 if (r) 222 return r; 223 224 r = amdgpu_jpeg_suspend(adev); 225 226 return r; 227 } 228 229 /** 230 * jpeg_v2_5_resume - resume JPEG block 231 * 232 * @handle: amdgpu_device pointer 233 * 234 * Resume firmware and hw init JPEG block 235 */ 236 static int jpeg_v2_5_resume(void *handle) 237 { 238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 239 int r; 240 241 r = amdgpu_jpeg_resume(adev); 242 if (r) 243 return r; 244 245 r = jpeg_v2_5_hw_init(adev); 246 247 return r; 248 } 249 250 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 251 { 252 uint32_t data; 253 254 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 255 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 256 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 257 else 258 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 259 260 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 261 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 262 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 263 264 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 265 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 266 | JPEG_CGC_GATE__JPEG2_DEC_MASK 267 | JPEG_CGC_GATE__JMCIF_MASK 268 | JPEG_CGC_GATE__JRBBM_MASK); 269 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 270 271 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 272 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 273 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 274 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 275 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 276 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 277 } 278 279 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 280 { 281 uint32_t data; 282 283 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 284 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 285 |JPEG_CGC_GATE__JPEG2_DEC_MASK 286 |JPEG_CGC_GATE__JPEG_ENC_MASK 287 |JPEG_CGC_GATE__JMCIF_MASK 288 |JPEG_CGC_GATE__JRBBM_MASK); 289 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 290 } 291 292 /** 293 * jpeg_v2_5_start - start JPEG block 294 * 295 * @adev: amdgpu_device pointer 296 * 297 * Setup and start the JPEG block 298 */ 299 static int jpeg_v2_5_start(struct amdgpu_device *adev) 300 { 301 struct amdgpu_ring *ring; 302 int i; 303 304 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 305 if (adev->jpeg.harvest_config & (1 << i)) 306 continue; 307 308 ring = &adev->jpeg.inst[i].ring_dec; 309 /* disable anti hang mechanism */ 310 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, 311 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 312 313 /* JPEG disable CGC */ 314 jpeg_v2_5_disable_clock_gating(adev, i); 315 316 /* MJPEG global tiling registers */ 317 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, 318 adev->gfx.config.gb_addr_config); 319 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, 320 adev->gfx.config.gb_addr_config); 321 322 /* enable JMI channel */ 323 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, 324 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 325 326 /* enable System Interrupt for JRBC */ 327 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), 328 JPEG_SYS_INT_EN__DJRBC_MASK, 329 ~JPEG_SYS_INT_EN__DJRBC_MASK); 330 331 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); 332 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 333 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 334 lower_32_bits(ring->gpu_addr)); 335 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 336 upper_32_bits(ring->gpu_addr)); 337 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); 338 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 339 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); 340 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 341 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 342 } 343 344 return 0; 345 } 346 347 /** 348 * jpeg_v2_5_stop - stop JPEG block 349 * 350 * @adev: amdgpu_device pointer 351 * 352 * stop the JPEG block 353 */ 354 static int jpeg_v2_5_stop(struct amdgpu_device *adev) 355 { 356 int i; 357 358 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 359 if (adev->jpeg.harvest_config & (1 << i)) 360 continue; 361 362 /* reset JMI */ 363 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 364 UVD_JMI_CNTL__SOFT_RESET_MASK, 365 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 366 367 jpeg_v2_5_enable_clock_gating(adev, i); 368 369 /* enable anti hang mechanism */ 370 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 371 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 372 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 373 } 374 375 return 0; 376 } 377 378 /** 379 * jpeg_v2_5_dec_ring_get_rptr - get read pointer 380 * 381 * @ring: amdgpu_ring pointer 382 * 383 * Returns the current hardware read pointer 384 */ 385 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 386 { 387 struct amdgpu_device *adev = ring->adev; 388 389 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); 390 } 391 392 /** 393 * jpeg_v2_5_dec_ring_get_wptr - get write pointer 394 * 395 * @ring: amdgpu_ring pointer 396 * 397 * Returns the current hardware write pointer 398 */ 399 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 400 { 401 struct amdgpu_device *adev = ring->adev; 402 403 if (ring->use_doorbell) 404 return adev->wb.wb[ring->wptr_offs]; 405 else 406 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 407 } 408 409 /** 410 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 411 * 412 * @ring: amdgpu_ring pointer 413 * 414 * Commits the write pointer to the hardware 415 */ 416 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 417 { 418 struct amdgpu_device *adev = ring->adev; 419 420 if (ring->use_doorbell) { 421 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 422 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 423 } else { 424 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 425 } 426 } 427 428 static bool jpeg_v2_5_is_idle(void *handle) 429 { 430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 431 int i, ret = 1; 432 433 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 434 if (adev->jpeg.harvest_config & (1 << i)) 435 continue; 436 437 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & 438 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 439 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 440 } 441 442 return ret; 443 } 444 445 static int jpeg_v2_5_wait_for_idle(void *handle) 446 { 447 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 448 int i, ret; 449 450 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 451 if (adev->jpeg.harvest_config & (1 << i)) 452 continue; 453 454 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, 455 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 456 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 457 if (ret) 458 return ret; 459 } 460 461 return 0; 462 } 463 464 static int jpeg_v2_5_set_clockgating_state(void *handle, 465 enum amd_clockgating_state state) 466 { 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 bool enable = (state == AMD_CG_STATE_GATE); 469 int i; 470 471 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 472 if (adev->jpeg.harvest_config & (1 << i)) 473 continue; 474 475 if (enable) { 476 if (!jpeg_v2_5_is_idle(handle)) 477 return -EBUSY; 478 jpeg_v2_5_enable_clock_gating(adev, i); 479 } else { 480 jpeg_v2_5_disable_clock_gating(adev, i); 481 } 482 } 483 484 return 0; 485 } 486 487 static int jpeg_v2_5_set_powergating_state(void *handle, 488 enum amd_powergating_state state) 489 { 490 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 491 int ret; 492 493 if(state == adev->jpeg.cur_state) 494 return 0; 495 496 if (state == AMD_PG_STATE_GATE) 497 ret = jpeg_v2_5_stop(adev); 498 else 499 ret = jpeg_v2_5_start(adev); 500 501 if(!ret) 502 adev->jpeg.cur_state = state; 503 504 return ret; 505 } 506 507 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev, 508 struct amdgpu_irq_src *source, 509 unsigned type, 510 enum amdgpu_interrupt_state state) 511 { 512 return 0; 513 } 514 515 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev, 516 struct amdgpu_irq_src *source, 517 struct amdgpu_iv_entry *entry) 518 { 519 uint32_t ip_instance; 520 521 switch (entry->client_id) { 522 case SOC15_IH_CLIENTID_VCN: 523 ip_instance = 0; 524 break; 525 case SOC15_IH_CLIENTID_VCN1: 526 ip_instance = 1; 527 break; 528 default: 529 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 530 return 0; 531 } 532 533 DRM_DEBUG("IH: JPEG TRAP\n"); 534 535 switch (entry->src_id) { 536 case VCN_2_0__SRCID__JPEG_DECODE: 537 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec); 538 break; 539 default: 540 DRM_ERROR("Unhandled interrupt: %d %d\n", 541 entry->src_id, entry->src_data[0]); 542 break; 543 } 544 545 return 0; 546 } 547 548 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 549 .name = "jpeg_v2_5", 550 .early_init = jpeg_v2_5_early_init, 551 .late_init = NULL, 552 .sw_init = jpeg_v2_5_sw_init, 553 .sw_fini = jpeg_v2_5_sw_fini, 554 .hw_init = jpeg_v2_5_hw_init, 555 .hw_fini = jpeg_v2_5_hw_fini, 556 .suspend = jpeg_v2_5_suspend, 557 .resume = jpeg_v2_5_resume, 558 .is_idle = jpeg_v2_5_is_idle, 559 .wait_for_idle = jpeg_v2_5_wait_for_idle, 560 .check_soft_reset = NULL, 561 .pre_soft_reset = NULL, 562 .soft_reset = NULL, 563 .post_soft_reset = NULL, 564 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 565 .set_powergating_state = jpeg_v2_5_set_powergating_state, 566 }; 567 568 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 569 .name = "jpeg_v2_6", 570 .early_init = jpeg_v2_5_early_init, 571 .late_init = NULL, 572 .sw_init = jpeg_v2_5_sw_init, 573 .sw_fini = jpeg_v2_5_sw_fini, 574 .hw_init = jpeg_v2_5_hw_init, 575 .hw_fini = jpeg_v2_5_hw_fini, 576 .suspend = jpeg_v2_5_suspend, 577 .resume = jpeg_v2_5_resume, 578 .is_idle = jpeg_v2_5_is_idle, 579 .wait_for_idle = jpeg_v2_5_wait_for_idle, 580 .check_soft_reset = NULL, 581 .pre_soft_reset = NULL, 582 .soft_reset = NULL, 583 .post_soft_reset = NULL, 584 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 585 .set_powergating_state = jpeg_v2_5_set_powergating_state, 586 }; 587 588 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { 589 .type = AMDGPU_RING_TYPE_VCN_JPEG, 590 .align_mask = 0xf, 591 .vmhub = AMDGPU_MMHUB_1, 592 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 593 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 594 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 595 .emit_frame_size = 596 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 597 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 598 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 599 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 600 8 + 16, 601 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 602 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 603 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 604 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 605 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 606 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 607 .insert_nop = jpeg_v2_0_dec_ring_nop, 608 .insert_start = jpeg_v2_0_dec_ring_insert_start, 609 .insert_end = jpeg_v2_0_dec_ring_insert_end, 610 .pad_ib = amdgpu_ring_generic_pad_ib, 611 .begin_use = amdgpu_jpeg_ring_begin_use, 612 .end_use = amdgpu_jpeg_ring_end_use, 613 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 614 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 615 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 616 }; 617 618 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { 619 .type = AMDGPU_RING_TYPE_VCN_JPEG, 620 .align_mask = 0xf, 621 .vmhub = AMDGPU_MMHUB_0, 622 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 623 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 624 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 625 .emit_frame_size = 626 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 627 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 628 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 629 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 630 8 + 16, 631 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 632 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 633 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 634 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 635 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 636 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 637 .insert_nop = jpeg_v2_0_dec_ring_nop, 638 .insert_start = jpeg_v2_0_dec_ring_insert_start, 639 .insert_end = jpeg_v2_0_dec_ring_insert_end, 640 .pad_ib = amdgpu_ring_generic_pad_ib, 641 .begin_use = amdgpu_jpeg_ring_begin_use, 642 .end_use = amdgpu_jpeg_ring_end_use, 643 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 644 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 645 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 646 }; 647 648 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 649 { 650 int i; 651 652 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 653 if (adev->jpeg.harvest_config & (1 << i)) 654 continue; 655 if (adev->asic_type == CHIP_ARCTURUS) 656 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; 657 else /* CHIP_ALDEBARAN */ 658 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs; 659 adev->jpeg.inst[i].ring_dec.me = i; 660 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); 661 } 662 } 663 664 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = { 665 .set = jpeg_v2_5_set_interrupt_state, 666 .process = jpeg_v2_5_process_interrupt, 667 }; 668 669 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) 670 { 671 int i; 672 673 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 674 if (adev->jpeg.harvest_config & (1 << i)) 675 continue; 676 677 adev->jpeg.inst[i].irq.num_types = 1; 678 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; 679 } 680 } 681 682 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = 683 { 684 .type = AMD_IP_BLOCK_TYPE_JPEG, 685 .major = 2, 686 .minor = 5, 687 .rev = 0, 688 .funcs = &jpeg_v2_5_ip_funcs, 689 }; 690 691 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = 692 { 693 .type = AMD_IP_BLOCK_TYPE_JPEG, 694 .major = 2, 695 .minor = 6, 696 .rev = 0, 697 .funcs = &jpeg_v2_6_ip_funcs, 698 }; 699