1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __JPEG_V2_0_H__
25 #define __JPEG_V2_0_H__
26 
27 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET				0x1bfff
28 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
29 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
30 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
31 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
32 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40eb
33 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
34 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
35 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET			0x40e8
36 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
37 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
38 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
39 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40ed
40 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
41 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
42 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
43 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
44 
45 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
46 
47 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
48 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
49 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
50 				unsigned flags);
51 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
52 				struct amdgpu_ib *ib, uint32_t flags);
53 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
54 				uint32_t val, uint32_t mask);
55 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
56 				unsigned vmid, uint64_t pd_addr);
57 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
58 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
59 
60 extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
61 
62 #endif /* __JPEG_V2_0_H__ */
63