1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 31 #include "vcn/vcn_2_0_0_offset.h" 32 #include "vcn/vcn_2_0_0_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 36 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 37 static int jpeg_v2_0_set_powergating_state(void *handle, 38 enum amd_powergating_state state); 39 40 /** 41 * jpeg_v2_0_early_init - set function pointers 42 * 43 * @handle: amdgpu_device pointer 44 * 45 * Set ring and irq function pointers 46 */ 47 static int jpeg_v2_0_early_init(void *handle) 48 { 49 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 50 51 adev->jpeg.num_jpeg_inst = 1; 52 53 jpeg_v2_0_set_dec_ring_funcs(adev); 54 jpeg_v2_0_set_irq_funcs(adev); 55 56 return 0; 57 } 58 59 /** 60 * jpeg_v2_0_sw_init - sw init for JPEG block 61 * 62 * @handle: amdgpu_device pointer 63 * 64 * Load firmware and sw initialization 65 */ 66 static int jpeg_v2_0_sw_init(void *handle) 67 { 68 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 69 struct amdgpu_ring *ring; 70 int r; 71 72 /* JPEG TRAP */ 73 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 74 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 75 if (r) 76 return r; 77 78 r = amdgpu_jpeg_sw_init(adev); 79 if (r) 80 return r; 81 82 r = amdgpu_jpeg_resume(adev); 83 if (r) 84 return r; 85 86 ring = &adev->jpeg.inst->ring_dec; 87 ring->use_doorbell = true; 88 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 89 ring->vm_hub = AMDGPU_MMHUB_0; 90 sprintf(ring->name, "jpeg_dec"); 91 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 92 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 93 if (r) 94 return r; 95 96 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 97 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 98 99 return 0; 100 } 101 102 /** 103 * jpeg_v2_0_sw_fini - sw fini for JPEG block 104 * 105 * @handle: amdgpu_device pointer 106 * 107 * JPEG suspend and free up sw allocation 108 */ 109 static int jpeg_v2_0_sw_fini(void *handle) 110 { 111 int r; 112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 113 114 r = amdgpu_jpeg_suspend(adev); 115 if (r) 116 return r; 117 118 r = amdgpu_jpeg_sw_fini(adev); 119 120 return r; 121 } 122 123 /** 124 * jpeg_v2_0_hw_init - start and test JPEG block 125 * 126 * @handle: amdgpu_device pointer 127 * 128 */ 129 static int jpeg_v2_0_hw_init(void *handle) 130 { 131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 132 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 133 int r; 134 135 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 136 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 137 138 r = amdgpu_ring_test_helper(ring); 139 if (!r) 140 DRM_INFO("JPEG decode initialized successfully.\n"); 141 142 return r; 143 } 144 145 /** 146 * jpeg_v2_0_hw_fini - stop the hardware block 147 * 148 * @handle: amdgpu_device pointer 149 * 150 * Stop the JPEG block, mark ring as not ready any more 151 */ 152 static int jpeg_v2_0_hw_fini(void *handle) 153 { 154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 155 156 cancel_delayed_work_sync(&adev->vcn.idle_work); 157 158 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 159 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 160 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 161 162 return 0; 163 } 164 165 /** 166 * jpeg_v2_0_suspend - suspend JPEG block 167 * 168 * @handle: amdgpu_device pointer 169 * 170 * HW fini and suspend JPEG block 171 */ 172 static int jpeg_v2_0_suspend(void *handle) 173 { 174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 175 int r; 176 177 r = jpeg_v2_0_hw_fini(adev); 178 if (r) 179 return r; 180 181 r = amdgpu_jpeg_suspend(adev); 182 183 return r; 184 } 185 186 /** 187 * jpeg_v2_0_resume - resume JPEG block 188 * 189 * @handle: amdgpu_device pointer 190 * 191 * Resume firmware and hw init JPEG block 192 */ 193 static int jpeg_v2_0_resume(void *handle) 194 { 195 int r; 196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 197 198 r = amdgpu_jpeg_resume(adev); 199 if (r) 200 return r; 201 202 r = jpeg_v2_0_hw_init(adev); 203 204 return r; 205 } 206 207 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 208 { 209 uint32_t data; 210 int r = 0; 211 212 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 213 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 214 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 215 216 r = SOC15_WAIT_ON_RREG(JPEG, 0, 217 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 218 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 219 220 if (r) { 221 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 222 return r; 223 } 224 } 225 226 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 227 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 228 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 229 230 return 0; 231 } 232 233 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev) 234 { 235 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 236 uint32_t data; 237 int r = 0; 238 239 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); 240 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 241 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 242 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 243 244 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 245 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 246 247 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 248 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 249 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 250 251 if (r) { 252 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 253 return r; 254 } 255 } 256 257 return 0; 258 } 259 260 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev) 261 { 262 uint32_t data; 263 264 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 265 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 266 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 267 else 268 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 269 270 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 271 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 272 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 273 274 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 275 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 276 | JPEG_CGC_GATE__JPEG2_DEC_MASK 277 | JPEG_CGC_GATE__JPEG_ENC_MASK 278 | JPEG_CGC_GATE__JMCIF_MASK 279 | JPEG_CGC_GATE__JRBBM_MASK); 280 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 281 } 282 283 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev) 284 { 285 uint32_t data; 286 287 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 288 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 289 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 290 else 291 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 292 293 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 294 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 295 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 296 297 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 298 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 299 |JPEG_CGC_GATE__JPEG2_DEC_MASK 300 |JPEG_CGC_GATE__JPEG_ENC_MASK 301 |JPEG_CGC_GATE__JMCIF_MASK 302 |JPEG_CGC_GATE__JRBBM_MASK); 303 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 304 } 305 306 /** 307 * jpeg_v2_0_start - start JPEG block 308 * 309 * @adev: amdgpu_device pointer 310 * 311 * Setup and start the JPEG block 312 */ 313 static int jpeg_v2_0_start(struct amdgpu_device *adev) 314 { 315 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 316 int r; 317 318 if (adev->pm.dpm_enabled) 319 amdgpu_dpm_enable_jpeg(adev, true); 320 321 /* disable power gating */ 322 r = jpeg_v2_0_disable_power_gating(adev); 323 if (r) 324 return r; 325 326 /* JPEG disable CGC */ 327 jpeg_v2_0_disable_clock_gating(adev); 328 329 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 330 331 /* enable JMI channel */ 332 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 333 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 334 335 /* enable System Interrupt for JRBC */ 336 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 337 JPEG_SYS_INT_EN__DJRBC_MASK, 338 ~JPEG_SYS_INT_EN__DJRBC_MASK); 339 340 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 341 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 342 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 343 lower_32_bits(ring->gpu_addr)); 344 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 345 upper_32_bits(ring->gpu_addr)); 346 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 347 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 348 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 349 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 350 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 351 352 return 0; 353 } 354 355 /** 356 * jpeg_v2_0_stop - stop JPEG block 357 * 358 * @adev: amdgpu_device pointer 359 * 360 * stop the JPEG block 361 */ 362 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 363 { 364 int r; 365 366 /* reset JMI */ 367 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 368 UVD_JMI_CNTL__SOFT_RESET_MASK, 369 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 370 371 /* enable JPEG CGC */ 372 jpeg_v2_0_enable_clock_gating(adev); 373 374 /* enable power gating */ 375 r = jpeg_v2_0_enable_power_gating(adev); 376 if (r) 377 return r; 378 379 if (adev->pm.dpm_enabled) 380 amdgpu_dpm_enable_jpeg(adev, false); 381 382 return 0; 383 } 384 385 /** 386 * jpeg_v2_0_dec_ring_get_rptr - get read pointer 387 * 388 * @ring: amdgpu_ring pointer 389 * 390 * Returns the current hardware read pointer 391 */ 392 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 393 { 394 struct amdgpu_device *adev = ring->adev; 395 396 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 397 } 398 399 /** 400 * jpeg_v2_0_dec_ring_get_wptr - get write pointer 401 * 402 * @ring: amdgpu_ring pointer 403 * 404 * Returns the current hardware write pointer 405 */ 406 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 407 { 408 struct amdgpu_device *adev = ring->adev; 409 410 if (ring->use_doorbell) 411 return *ring->wptr_cpu_addr; 412 else 413 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 414 } 415 416 /** 417 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 418 * 419 * @ring: amdgpu_ring pointer 420 * 421 * Commits the write pointer to the hardware 422 */ 423 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 424 { 425 struct amdgpu_device *adev = ring->adev; 426 427 if (ring->use_doorbell) { 428 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 429 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 430 } else { 431 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 432 } 433 } 434 435 /** 436 * jpeg_v2_0_dec_ring_insert_start - insert a start command 437 * 438 * @ring: amdgpu_ring pointer 439 * 440 * Write a start command to the ring. 441 */ 442 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 443 { 444 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 445 0, 0, PACKETJ_TYPE0)); 446 amdgpu_ring_write(ring, 0x68e04); 447 448 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 449 0, 0, PACKETJ_TYPE0)); 450 amdgpu_ring_write(ring, 0x80010000); 451 } 452 453 /** 454 * jpeg_v2_0_dec_ring_insert_end - insert a end command 455 * 456 * @ring: amdgpu_ring pointer 457 * 458 * Write a end command to the ring. 459 */ 460 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 461 { 462 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 463 0, 0, PACKETJ_TYPE0)); 464 amdgpu_ring_write(ring, 0x68e04); 465 466 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 467 0, 0, PACKETJ_TYPE0)); 468 amdgpu_ring_write(ring, 0x00010000); 469 } 470 471 /** 472 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command 473 * 474 * @ring: amdgpu_ring pointer 475 * @addr: address 476 * @seq: sequence number 477 * @flags: fence related flags 478 * 479 * Write a fence and a trap command to the ring. 480 */ 481 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 482 unsigned flags) 483 { 484 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 485 486 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 487 0, 0, PACKETJ_TYPE0)); 488 amdgpu_ring_write(ring, seq); 489 490 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 491 0, 0, PACKETJ_TYPE0)); 492 amdgpu_ring_write(ring, seq); 493 494 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 495 0, 0, PACKETJ_TYPE0)); 496 amdgpu_ring_write(ring, lower_32_bits(addr)); 497 498 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 499 0, 0, PACKETJ_TYPE0)); 500 amdgpu_ring_write(ring, upper_32_bits(addr)); 501 502 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 503 0, 0, PACKETJ_TYPE0)); 504 amdgpu_ring_write(ring, 0x8); 505 506 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 507 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 508 amdgpu_ring_write(ring, 0); 509 510 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 511 0, 0, PACKETJ_TYPE0)); 512 amdgpu_ring_write(ring, 0x3fbc); 513 514 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 515 0, 0, PACKETJ_TYPE0)); 516 amdgpu_ring_write(ring, 0x1); 517 518 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 519 amdgpu_ring_write(ring, 0); 520 } 521 522 /** 523 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer 524 * 525 * @ring: amdgpu_ring pointer 526 * @job: job to retrieve vmid from 527 * @ib: indirect buffer to execute 528 * @flags: unused 529 * 530 * Write ring commands to execute the indirect buffer. 531 */ 532 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 533 struct amdgpu_job *job, 534 struct amdgpu_ib *ib, 535 uint32_t flags) 536 { 537 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 538 539 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, 540 0, 0, PACKETJ_TYPE0)); 541 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); 542 543 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 544 0, 0, PACKETJ_TYPE0)); 545 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 546 547 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 548 0, 0, PACKETJ_TYPE0)); 549 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 550 551 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 552 0, 0, PACKETJ_TYPE0)); 553 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 554 555 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 556 0, 0, PACKETJ_TYPE0)); 557 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 558 559 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 560 0, 0, PACKETJ_TYPE0)); 561 amdgpu_ring_write(ring, ib->length_dw); 562 563 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 564 0, 0, PACKETJ_TYPE0)); 565 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 566 567 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 568 0, 0, PACKETJ_TYPE0)); 569 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 570 571 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 572 amdgpu_ring_write(ring, 0); 573 574 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 575 0, 0, PACKETJ_TYPE0)); 576 amdgpu_ring_write(ring, 0x01400200); 577 578 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 579 0, 0, PACKETJ_TYPE0)); 580 amdgpu_ring_write(ring, 0x2); 581 582 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 583 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 584 amdgpu_ring_write(ring, 0x2); 585 } 586 587 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 588 uint32_t val, uint32_t mask) 589 { 590 uint32_t reg_offset = (reg << 2); 591 592 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 593 0, 0, PACKETJ_TYPE0)); 594 amdgpu_ring_write(ring, 0x01400200); 595 596 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 597 0, 0, PACKETJ_TYPE0)); 598 amdgpu_ring_write(ring, val); 599 600 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 601 0, 0, PACKETJ_TYPE0)); 602 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 603 amdgpu_ring_write(ring, 0); 604 amdgpu_ring_write(ring, 605 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 606 } else { 607 amdgpu_ring_write(ring, reg_offset); 608 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 609 0, 0, PACKETJ_TYPE3)); 610 } 611 amdgpu_ring_write(ring, mask); 612 } 613 614 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 615 unsigned vmid, uint64_t pd_addr) 616 { 617 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 618 uint32_t data0, data1, mask; 619 620 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 621 622 /* wait for register write */ 623 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 624 data1 = lower_32_bits(pd_addr); 625 mask = 0xffffffff; 626 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 627 } 628 629 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 630 { 631 uint32_t reg_offset = (reg << 2); 632 633 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 634 0, 0, PACKETJ_TYPE0)); 635 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 636 amdgpu_ring_write(ring, 0); 637 amdgpu_ring_write(ring, 638 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 639 } else { 640 amdgpu_ring_write(ring, reg_offset); 641 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 642 0, 0, PACKETJ_TYPE0)); 643 } 644 amdgpu_ring_write(ring, val); 645 } 646 647 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 648 { 649 int i; 650 651 WARN_ON(ring->wptr % 2 || count % 2); 652 653 for (i = 0; i < count / 2; i++) { 654 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 655 amdgpu_ring_write(ring, 0); 656 } 657 } 658 659 static bool jpeg_v2_0_is_idle(void *handle) 660 { 661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662 663 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 664 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 665 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 666 } 667 668 static int jpeg_v2_0_wait_for_idle(void *handle) 669 { 670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 671 int ret; 672 673 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 674 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 675 676 return ret; 677 } 678 679 static int jpeg_v2_0_set_clockgating_state(void *handle, 680 enum amd_clockgating_state state) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 bool enable = (state == AMD_CG_STATE_GATE); 684 685 if (enable) { 686 if (!jpeg_v2_0_is_idle(handle)) 687 return -EBUSY; 688 jpeg_v2_0_enable_clock_gating(adev); 689 } else { 690 jpeg_v2_0_disable_clock_gating(adev); 691 } 692 693 return 0; 694 } 695 696 static int jpeg_v2_0_set_powergating_state(void *handle, 697 enum amd_powergating_state state) 698 { 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 int ret; 701 702 if (state == adev->jpeg.cur_state) 703 return 0; 704 705 if (state == AMD_PG_STATE_GATE) 706 ret = jpeg_v2_0_stop(adev); 707 else 708 ret = jpeg_v2_0_start(adev); 709 710 if (!ret) 711 adev->jpeg.cur_state = state; 712 713 return ret; 714 } 715 716 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev, 717 struct amdgpu_irq_src *source, 718 unsigned type, 719 enum amdgpu_interrupt_state state) 720 { 721 return 0; 722 } 723 724 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev, 725 struct amdgpu_irq_src *source, 726 struct amdgpu_iv_entry *entry) 727 { 728 DRM_DEBUG("IH: JPEG TRAP\n"); 729 730 switch (entry->src_id) { 731 case VCN_2_0__SRCID__JPEG_DECODE: 732 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 733 break; 734 default: 735 DRM_ERROR("Unhandled interrupt: %d %d\n", 736 entry->src_id, entry->src_data[0]); 737 break; 738 } 739 740 return 0; 741 } 742 743 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 744 .name = "jpeg_v2_0", 745 .early_init = jpeg_v2_0_early_init, 746 .late_init = NULL, 747 .sw_init = jpeg_v2_0_sw_init, 748 .sw_fini = jpeg_v2_0_sw_fini, 749 .hw_init = jpeg_v2_0_hw_init, 750 .hw_fini = jpeg_v2_0_hw_fini, 751 .suspend = jpeg_v2_0_suspend, 752 .resume = jpeg_v2_0_resume, 753 .is_idle = jpeg_v2_0_is_idle, 754 .wait_for_idle = jpeg_v2_0_wait_for_idle, 755 .check_soft_reset = NULL, 756 .pre_soft_reset = NULL, 757 .soft_reset = NULL, 758 .post_soft_reset = NULL, 759 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 760 .set_powergating_state = jpeg_v2_0_set_powergating_state, 761 }; 762 763 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 764 .type = AMDGPU_RING_TYPE_VCN_JPEG, 765 .align_mask = 0xf, 766 .get_rptr = jpeg_v2_0_dec_ring_get_rptr, 767 .get_wptr = jpeg_v2_0_dec_ring_get_wptr, 768 .set_wptr = jpeg_v2_0_dec_ring_set_wptr, 769 .emit_frame_size = 770 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 771 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 772 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 773 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 774 8 + 16, 775 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */ 776 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 777 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 778 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 779 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 780 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 781 .insert_nop = jpeg_v2_0_dec_ring_nop, 782 .insert_start = jpeg_v2_0_dec_ring_insert_start, 783 .insert_end = jpeg_v2_0_dec_ring_insert_end, 784 .pad_ib = amdgpu_ring_generic_pad_ib, 785 .begin_use = amdgpu_jpeg_ring_begin_use, 786 .end_use = amdgpu_jpeg_ring_end_use, 787 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 788 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 789 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 790 }; 791 792 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 793 { 794 adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs; 795 DRM_INFO("JPEG decode is enabled in VM mode\n"); 796 } 797 798 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = { 799 .set = jpeg_v2_0_set_interrupt_state, 800 .process = jpeg_v2_0_process_interrupt, 801 }; 802 803 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev) 804 { 805 adev->jpeg.inst->irq.num_types = 1; 806 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; 807 } 808 809 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = 810 { 811 .type = AMD_IP_BLOCK_TYPE_JPEG, 812 .major = 2, 813 .minor = 0, 814 .rev = 0, 815 .funcs = &jpeg_v2_0_ip_funcs, 816 }; 817